low noise amplifier
DESCRIPTION
consideration in designing LNATRANSCRIPT
1
Low-Noise Amplifier
2
RF Receiver
BPF1 BPF2LNA
LO
Mixer BPF3 IF Amp
Demodulator
Antenna
RF front end
3
Low-Noise Amplifier• First gain stage in receiver
– Amplify weak signal• Significant impact on noise performance
– Dominate input-referred noise of front end
• Impedance matching– Efficient power transfer– Better noise performance– Stable circuit
LNA
subsequentLNAfrontend G
NFNFNF
1
4
LNA Design Consideration
• Noise performance• Power transfer• Impedance matching• Power consumption• Bandwidth• Stability• Linearity
5
Noise Figure• Definition
• As a function of device
G: Power gain of the device
outout
inin
out
in
NSNS
SNRSNRNF
source
sourcedevice
NGNGNNF
6
NF of Cascaded Stages
• Overall NF dominated by NF1
[1] F. Friis, “Noise Figure of Radio Receivers,” Proc. IRE, Vol. 32, pp.419-422, July 1944.
Sin/Nin
G1, N1, NF1
Gi, Ni, NFi
GK, NK, NFK
Sout/Nout
12121
3
1
21
11111
K
K
...GGGNF...
GGNF
GNFNFNF
7
Simple Model of Noise in MOSFET
fWLCkfV
oxg )(2
• Flicker noise– Dominant at low frequency
• Thermal noise– : empirical constant
2/3 for long channelmuch larger for short channel
– PMOS has less thermal noise
• Input-inferred noise
md gkTfI 4)(2
Vg
Id
Vi
fWLCk
gkTfV
oxmi
4)(2
8
Noise Approximation
Thermal noise
1/f noise
Band of interest Frequency
Noise spectral density
Thermal noise dominant
9
Power Transfer and Impedance Matching
LLLss
sdel R
jXRjXRVP
2
s
ssXXRRL R
VVPPLsLs 4
*
0,max
• Power delivered to load
• Maxim available power
Rs
Vs
jXs jXL
RLI V
• Impedance matching– Load and source impedances conjugate pair– Real part matched to 50 ohm
10
Available Power
Equal power on load and source resistors
11
Reflection Coefficient
***
max 4))((
4aa
RIZVIZV
RVVP
s
ss
s
ss
s
s
RIZVa
2
****
max 4))(( bb
RZIVIZVPPP
s
ssdelref
Rs
Vs
jXs jXL
RLI V
s
s
RIZVb
2
*
sL
sL
ZZZZ
ab
*
2)( **
LLdel
ZZIIP
LIZV
12
Reflection Coefficient
No reflectionMaximum power transfer
13
S-Parameters• Parameters for two-port system analysis• Suitable for distributive elements• Inputs and outputs expressed in powers
– Transmission coefficients– Reflection coefficients
14
S-Parameters
2221212
2121111
aSaSbaSaSb
a1
b1
b2
a2
S11
S12
S22
S21
15
S-Parameters• S11 – input reflection coefficient with
the output matched
• S21 – forward transmission gain or loss
• S12 – reverse transmission or isolation
• S22 – output reflection coefficient with the input matched
012
222
012
112
021
221
021
111
a
a
a
a
abS
abS
abS
abS
16
S-Parameters
SZ1 Z2
Vs1 Vs2
I1
V1
I2
V2
0222
*222
22
01
2
222
*111
12
02
1
111
*222
210111
*111
11
11
22
)Re()Re(
)Re()Re(
ss
ss
VV
VV
ZIVZIVS
ZZ
ZIVZIVS
ZZ
ZIVZIVS
ZIVZIVS
17
Stability Condition
• Necessary condition
where• Stable iff
where
1||2
||||||1
2112
2211
222
SSSSK S
21122211 SSSSS
1|| 2 LLS
2||||||2
222
112112
SSSSL
18
A First LNA Example
• Assume– No flicker noise– ro = infinity
– Cgd = 0– Reasonable for appropriate
bandwidth• Effective transconductance
Rs
Vs
Vs
Rs 4kTRs
Vgs gmVgs 4kTgmins
inm
s
omeff ZR
ZgViG
io
19
Power Gain• Voltage input• Current output
2
22
2
22
22
*
*
1)(1
1)(1)(1
||
s
T
gss
m
gss
m
gss
gsm
ins
inmmeff
ss
oo
RCRg
CRjg
CjRCjg
ZRZgG
VViiG
20
Noise Figure Calculation• Power ratio @ output
– Device noise + input-induced noise– Input-induced noise
2
2
222
22
2
)/(1
)1(1
)(14
41
gsmms
ms
gssms
gss
ms
m
in
indevice
CggR
gR
CRgR
CRgkTR
gkTNG
NGNNF
gs
mT C
g
21
Unity Current Gain Frequency
Device ioutiin
1ωω
Tin
Touti
in
outi
iiA
iiA
T
0dB
fT
Ai
ffrequency
22
Small-Signal Model of MOSFET
• Cgs
• Cgd
• rds
• Cdb
• Rg: Gate resistance
• ri: Channel charging resistance
V’gs
gmV’gs
Cgdi1 i2
ri
Cgs
i1
i2
Cdb
rds
Rg
V1 V2
V1
V2
23
T Calculation
gdgsiggsiggdgs
gdgsigdgs
VCCrRsCsrRCCs
CCrsCCsVIY 2
2
01
111 )(1
)(
2
V’gs
gmV’gs
Cgdi1 i2
ri
CgsCdb
rds
Rg
V1
V’gs
gmV’gs
Cgdi1 i2
ri
Cgs
Rg
V1
gdgsiggsiggdgs
gdgsigdgsim
VCCrRsCsrRCCs
CCrssCCsrgVIY 2
2
01
221 )(1
)1(
2
24
T of NMOS and PMOS• 0.25um CMOS Process*
[2] Tajinder Manku, “Microwave CMOS - Device Physics and Design,” IEEE J. Solid-State Circuits, vol. 34, pp. 277 - 285, March 1999.
mgdgs
mT g
CCg
1)()(
21
11 T
T
jYjY
Set:
Solve for T
25
Noise Performance
• Low frequency– Rsgm >> ~ 1– gm >> 1/50 @ Rs = 50 ohm– Power consuming
• CMOS technology– gm/ID lower than other tech– T lower than other tech
2
2
1T
msms
gRgR
NF
26
Review of First Example• No impedance matching
– Capacitive input impedance– Output not matched
• Power transfer– S11=(1-sRCgs)/(1+sRCgs)
– S21=2Rgm/(1+sRCgs), R=Rs=RL
• Power consumption– High power for NF– High power for S21
27
Impedance Matching for LNA• Resistive termination• Series-shunt feedback• Common-gate connection• Inductor degeneration
28
Resistive Termination
2
/1/1 gsIs
m
CjRRgG
• Current-current power gain
• Noise figure
Rs
Vs Is Rs
4kT/Rs
Vgs gmVgs
io
RI RI
4kT/RI4kTgm
2
22111
Tsm
Ism
s
I
s RgRRg
RRRNF
29
Comparison with Previous Example• Previous example
• Resistive-termination
2
22
11T
smI
s
smI
s RgRR
RgRRNF
2
2
1T
msms
gRgR
NF
Introduced by input resistance Signal attenuated
30
Summary - Resistive Termination• Noise performance
– Low-frequency approximation– Input matched Rs = RI = R
• Broadband input match• Attenuate signal• Introduce noise due to RI
• NF > 3 dB (best case)
RgNF
m
42
31
Series-Shunt Feedback• Broadband matching
• Could be noisy
Rs
Vs
Ra
RF
RL
Vgs gmVgs
RFiout
Ra
Cgs
Rs
Vs
RL
gsLFaaLm
gsaamLFin CRRRsRRg
CsRRgRRR
)()(1)1)((
))((1)(
))((1))(1(
asgsm
saFsFags
asgsm
sFamout
RRsCgRRRRRRsC
RRsCgRRRgR
32
Common-Gate Structure
RsRL
Vs
Rs 4kTRs
VgsgmVgs
RL
4kTgm
Vs
Rs 4kTRs
Vgs gmVgs
RL
4kTgm
gm
gsssm
m
s
outeff
CsRRgg
VIG
1
33
Input Impedance of CG Structure• Input impedance
Yin=gm+sCgs
• Input-impedance matching– Low frequency approximation– Direct without passive components
1/gm=Rs=50 ohm
34
Noise Performance of CG Structure
2
2
2222
222
2
41
)1(1
)()1(4
41
T
gsssmms
gsssm
ms
m
in
indevice
CRRggR
CRRggkTR
gkTNG
NGNNF
222
22
)()1( gsssm
meff CRRg
gGG
Signal attenuated
35
Power Transfer of CG Structure• Rs = RL = R = 50 ohm
• S11=0, S21=1 @ Low frequency
gss
gss
gsssm
gsssm
sin
sin
CsRCsR
CsRRgCsRRg
ZZZZS
2
11*
11
gs
gsssm
mLeffL
sC
CsRRggRGRS
22
12221
36
Summary – CG Structure• Noise performance
– No extra resistive noise source– Independent of power consumption
• Impedance matching– Broadband input matching– No passive components
• Power consumption– gm=1/50
• Power transfer– Independent of power consumption
37
Inductor Degeneration Structure
Rs
Vs
Ls
Lg
Vgs gmVgs
iout
Cgs
Rs
Vs
Lg
Ls
Zin
Vin
iin
gs
sm
gssgin
sgs
inmings
ingin
sgsmings
inginin
CLg
sCLLsI
sLsC
IgIsC
IsLI
sLVgIsC
IsLIV
1)(
)1(1
)(1
Zin
38
Input Matching for ID Structure
• Zin=Rs
– IM{Zin}=0
– RE{Zin}=Rs
gs
sm
gssgin C
LgsC
LLsZ 1)(
gssg CLL )(12
0
sgs
sm RC
Lg
Vgs gmVgs
iout
Cgs
Rs
Vs
LgLs
Zin
gmLs/Cgs
39
Effective Transconductance
Vgs gmVgs
iout
Cgs
Rs
Vs
LgLs
Zin
gmLs/Cgs
)()(1
)(
2sggssmgss
m
ins
gsm
s
outeff
LLCsLgCRsgZR
sCgVIG
40
Noise Factor of ID Structure
• Calculate NF at 0
22
22
2
)(1
)(4
410
smgssms
smgss
ms
m
in
indevice
LgCRgR
LgCRgkTR
gkTNG
NGNNF
2222
22
)()](1[ smgsssggs
meff LgCRLLC
gGG
= 0 @ 0
41
Input Quality Factor of ID Structure
CRRIICII
powerLostpowerStoredQ
1*
*
Cgs
Rs
Vs
LgLs
gmLs/Cgs
C
R
V
L
gsssmgss
gssmsgsin
CRLgCR
CLgRCCRQ
21
)(1
)/(11
I
42
Noise Factor of ID Structure
2
22
11
)(1
0
inms
smgssms
QgR
LgCRgR
NF
)(1
smgssin LgCR
Q
• Increase power transfergmLs/Cgs = Rs
• Decrease NFgmLs/Cgs = 0
• Conflict between– Power transfer– Noise performance
43
Further Discussion on NF
sg
s
sggsms
sm
smgssms
LLL
LLCgRLg
LgCRgR
NF
41
)(1)(41
)(1
2
22
0
• Frequency @ 0
2 ~= 1/Cgs/(Lg+Ls)• Input impedance
matched to Rs
RsCgs=gmLs
• Suitable for hand calculation and design
• Large Lg and small Ls
Tss RL
gsgs CLL 201
44
Power Transfer of ID Structure• Rs = RL = R = 50 ohm
• @
)()(1)(1
)(1)(1
2
2
2
2*
11
sggsgsssm
sggs
gsssmsggs
gsssmsggs
sin
sin
LLCsCRLgsLLCs
CsRLsgLLCsCsRLsgLLCs
ZZZZS
)()(122 221
sggssmgss
LmLeff LLCsLgCRs
RgRGS
)(1
smgssin LgCR
Q
gssg CLL )(
120
s
LTinLm
smgss
Lm
RRjQRgj
LgCRjRgSS
002111 2
)(2 ;0
45
Computing Av without S-ParaRs
Vs
Ls
Lg
)(2/1
22
;2 :matchimput and resonanceAt
0
00
0
oos
T
s
ov
sTssgssmo
gsinmgsmossin
sin
YYRj
VVA
RjVRCjVgI
CjIgVgIRVIRZ
46
Power Consumption
DDTgsox
DDD VVVLWCVIP 2)(
2
WLCC oxgs 32
)( Tgsoxm VVLWCg
222
23
Tgsoxgs
m VVLWC
CLg
gs
sms C
LgR s
gssm L
CRg
)/1(31
)(31
3
)(333
320
2222
0
22
20
2
22
2
2222
sgs
DDs
sg
DDTDDgs
T
sg
DD
s
sDDgs
s
sDD
gs
m
LLLVRL
LLVLVCLP
LLV
LRLVC
LRLV
CLgP
47
Power Consumption
)/1(1
320
22
sgs
s
LLLRLP
• Technology constant– L: minimum feature size– : mobility, avoid mobility saturation region
• Standard specification– Rs: source impedance
– 0: carrier frequency
• Circuit parameter– Lg, Ls: gate and source degeneration inductance
sg
s
LLLNF
410
48
Summary of ID Structure• Noise performance
– No resistive noise source– Large Lg
• Impedance matching – Matched at carrier frequency– Applicable to wideband application, S11<-10dB
• Power transfer– Narrowband– Increase with gm
• Power consumption– Large Lg
49
Cascode
• Isolation to improve S12 @ high frequency– Small range at Vd1
– Reduced feedback effect of Cgd
• Improve noise performance
Rs
Vs
Ls
Lg
Vbias
LL
M2
M1
Vd1
Vo
50
Rs
Vs
Ls
Lg
LL
M1
Vo
Vgs gmVgsCgs
Rs
Vs
Lg
Ls LL
Vo
51
LNA Design Example (1)
Rs
Vs Ls
Lg
Ld
M2
M1
Lvdd
Vbias
M4
Lb1
Cb1
Tm
Cm
M3
Lgnd
Lout
Input bias Off-chip
matching[3] D. Shaeffer and T. Lee, “A 1.5-V, 1.5-GHz CMOS low noise amplifier,” IEEE J. Solid-State Circuits, vol. 32, pp. 745 – 759, May 1997.
Lb2Cb2 Vout
Output bias
Vdd
52
LNA Design Example (1)
Rs
Vs Ls
Lg
Ld
M2
M1
Lvdd
Vbias
M4
Lb1
Cb1
Tm
Cm
M3
Lgnd
Lout
[3] D. Shaeffer and T. Lee, “A 1.5-V, 1.5-GHz CMOS low noise amplifier,” IEEE J. Solid-State Circuits, vol. 32, pp. 745 – 759, May 1997.
Unwanted parasitics
Supply filtering
53
Circuit Details• Two-stage cascoded structure in 0.6 m• First stage
– W1 = 403 m determined from NF
– Ls accurate value, bondwire inductance
– Ld = 7nH, resonating with cap at drain of M2
• Second– 4.6 dB gain– W3 = 200 m
54
55
LNA Design Example (2)
[4] A. Karanicolas, “A 2.7-V 900-MHz CMOS LNA and Mixer,” IEEE J. Solid-State Circuits, vol. 31, pp 1939 – 1944, Dec. 1996.
Cs
M2
M1
M3
Off-chip matching
Ns
RB
VRF
CB
IREF
IB1
VB1M4
M5
M7
M6
Vout1
RX
CX
NL
Off-chip matching
NF = 1 + K/gm
gm = gm1 + gm2
56
Simplified view
57
LNA Design Example (2)
[4] A. Karanicolas, “A 2.7-V 900-MHz CMOS LNA and Mixer,” IEEE J. Solid-State Circuits, vol. 31, pp 1939 – 1944, Dec. 1996.
Cs
M2
M1
M3Bias feedback
Ns
RB
VRF
CB
IREF
IB1
VB1M4
M5
M7
M6
Vout1
RX
CX
NL
M8
58
LNA Design Example (2)
[4] A. Karanicolas, “A 2.7-V 900-MHz CMOS LNA and Mixer,” IEEE J. Solid-State Circuits, vol. 31, pp 1939 – 1944, Dec. 1996.
Cs
M2
M1
M3Bias feedback
Ns
RB
VRF
CB
IREF
IB1
VB1M4
M5
M7
M6
Vout1
RX
CX
NL
M8
59
LNA Design Example (2)
[4] A. Karanicolas, “A 2.7-V 900-MHz CMOS LNA and Mixer,” IEEE J. Solid-State Circuits, vol. 31, pp 1939 – 1944, Dec. 1996.
Cs
M2
M1
M3Bias feedback
Ns
RB
VRF
CB
IREF
IB1
VB1M4
M5
M7
M6
Vout1
RX
CX
NL
M8
VA
DC output = VB1
60
61
LNA Design Example (3)
• Objective is to design tunable RF LNA that would:
– Operate over very wide frequency range with very fine selectivity
– Achieve a good noise performance
– Have a good linearity performance
– Consume minimum power
62
LNA Architecture • The cascode architecture
provides a good input – output isolation
• Transistor M2 isolates the Miller capacitance
• Input Impedance is obtained using the source degeneration inductor Ls
• Gate inductor Lg sets the resonant frequency
• The tuning granularity is achieved by the output matching network
VDD
LS
LG
M1
M2
LD
R2
R1
M3
Output to Mixer
Input to LNA
Matching Network
63
Matching Network • The output matching tuning
network is composed of a varactor and an inductor.
• The LC network is used to convert the load impedance into the input impedance of the subsequent stage.
• A well designed matching network allows for a maximum power transfer to the load.
• By varying the DC voltage applied to the varactor, the output frequency is tuned to a different frequency.
64
Simulation Results - S11• The input return loss
S11 is less than – 10dB at a frequency range between 1.4 GHz and 2GHz
Input return loss
65
Simulation results - NF • The noise figure is 1.8
dB at 1.4 GHz and rises to 3.4 dB at 2 GHz.
Noise Figure
66
Simulation Results - S22
S22 at 1.7725 GHz S22 at 1.77 GHz
• By controlling the voltage applied to the varactor the output frequency is tuned by 2.5 MHz.
• The output return loss at 1.77 GHz is – 44.73 dB and the output return loss at 1.7725 GHz – 45.69 dB.
67
Simulation Results - S22
S22 at 1.9975 GHz S22 at 2 GHz
• The output return loss at 2 GHz is – 26.47 dB and the output return loss at 1.9975 GHz – 26.6 dB.
68
Simulation Results - S21• The overall gain of
the LNA is 12 dB
S21 at 1.4025 GHz
69
Simulation Results - Linearity
-1dB compression point IIP3
• The third order input intercept is –3.16 dBm
• -1 dB compression point ( the output level at which the actual gain departs from the theoretical gain) is –12 dBm
70
From an earlier slide:
fWLCkfV
oxg )(2
• Flicker noise– Dominant at low frequency
• Thermal noise– : empirical constant
2/3 for long channelmuch larger for short channel
– PMOS has less thermal noise• Input-inferred noise
md gkTfI 4)(2
Vg
Id
Vi
fWLCk
gkTfV
oxmi
4)(2
Not accurate for low voltage short channel devices
71
Modifications
is called excess noise factor = 2/3 in long channel = 2 to 3 (or higher!) in short channel NMOS (less in PMOS)
m
dodgkTgkTfI 44)(2
Thermonoise
72
gdo vs gm in short channel
73
gdo vs gm in short channel
74
Fliker noise• Traps at channel/oxide interface randomly
capture/release carriers
– Parameterized by Kf and n • Provided by fab (note n ≈ 1) • Currently: Kf of PMOS << Kf of NMOS due to buried channel
– To minimize: want large area (high WL)
fK
fK
fI
fWLCkfV
fnf
d
oxg
)(
)(
2
2
75
Induced Gate Noise• Fluctuating channel potential couples
capacitively into the gate terminal, causing a noise gate current
– is gate noise coefficient• Typically assumed to be 2
– Correlated to drain noise!
2
2
54
Tdong gkTi
76
Input impedance
Set to be real and equal to source resistance:
real
gs
m
gsgin C
LgsC
LLssZ degdeg
1)()(
gsg CLL )(1
deg
20
sgs
m RCLg
deg
77
Output noise current
)14(21)( 222 QcgkTfI dddod
Noise scaling factor:
)14(2141 22 Qc dd
Where for 0.18 processc=-j0.55, =3, =6, gdo=2gm,
d = 0.32
5do
md g
g
s
g
gss RLL
CRQ
2)(
21 deg0
0
78
Noise factor
Noise factor scaling coefficient:
22 )14(212 dd
m
donf Qc
gg
QK
22 )14(212
1 ddm
do
T
o Qcgg
QF
42
1)(41 0220
0 QCR
gRNGNGNNF
Tgss
msin
indevice
Compare:
79
Noise factor scaling coefficient versus Q
80
Example • Assume Rs = 50 Ohms, Q = 2, fo = 1.8 GHz, ft = 47.8
GHz• From
gss CRQ
021
fFeQR
Cs
gs 442)2(98.12)50(2
12
1
0
nHe
RgCR
LT
s
m
gss 17.098.472
50deg
nHLC
LCLL gs
ggsg
5.171)(
1deg2
0deg
20
81
Have We Chosen the Correct Bias Point?
IIP3 is also a function of Q
82
If we choose Vgs=1V• Idens = 175 A/m
• From Cgs = 442 fF, W=274m
• Ibias = IdensW = 48 mA, too large!
• Solution 1: lower Idens => lower power, lower fT, lower IIP3
• Solution 2: lower W => lower power, lower Cgs, higher Q, higher NF
83
Lower current density to 100
Need to verify that IIP3 still OK (once we know Q)
84
We now need to re-plot the Noise Factor scaling coefficient - Also plot over a wider range of Q
Lower current density to 100
43.05268.0
568.0
15.178.0
do
md
do
m
gg
gg
GHz 8.4229.2
78.0
fFmS
Cg
gs
mT
22 )14(21211 dd
m
do
T
o QcQg
gF
85
86
Recall
We previously chose Q = 2, let’s now choose Q = 6 - Cuts power dissipation by a factor of 3! - New value of W is one third the old one
mmW 913
274
87
• Rs = 50 Ohms, Q = 6, fo = 1.8 GHz, ft = 42.8 GHz
• Ibias = IdensW =100A/m*91m=9.1mA• Power = 9.1 * 1.8 = 16.4 mW• Noise factor scaling coeff = 10• Noise factor = 1+ wo/wt * 10
= 1+ 1.8G/42.8G *10 = 1.42• Noise figure = 10*log(1.42) = 1.52 dB• Cgs=442/3=147fF• Ldeg=Rs/wt=0.19nH• Lg=1/(wo^2Cgs) –Ldeg = 53 nH
88
Other architectures of LNAs
•Add output load to achieve voltage gain•In practice, use cascode to boost gain
•Added benefit of removing Cgd effect
89
Differential LNAValue of Ldeg is now much better controlled
Much less sensitivity to noise from other circuits But: Twice the power as the single-ended version
Requires differential input at the chip
90
LNA Employing Current Re-Use
•PMOS is biased using a current mirror •NMOS current adjusted to match the PMOS current •Note: not clear how the matching network is achieving a 50 Ohm match
Perhaps parasitic bondwire inductance is degenerating the PMOS or NMOS transistors?
91
Combining inductive degeneration and current reuse
Current reuse to save power
Larger area due to two degenerationinductor if implemented on chip
NF: 2dB, Power gain: 17.5dB, IIP3: -6dBm, Id: 8mA from 2.7V power supply
Can have differential version
F. Gatta, E. Sacchi, et al, “A 2-dB Noise Figure 900MHz Differential CMOS LNA,” IEEE JSSC, Vol. 36, No. 10, Oct. 2001 pp. 1444-1452
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At DC, M1 and M2 are in cascodeAt AC, M1 and M2 are in cascadeS of M2 is AC shortedGm of M1 and M2 are multiplied.Same biasing current in M1 & M2
LIANG-HUI LI AND HUEY-RU CHUANG, MICROWAVE JOURNAL® from the February 2004 issue.
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amamama
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3
3
33
221
•IM3 components in the drain current of the main transistor has the required information of its nonlinearity•Auxiliary circuit is used to tune the magnitude and phase of IM3 components•Addition of main and auxiliary transistor currents results in negligible IM3 components at output
Sivakumar Ganesan, Edgar Sánchez-sinencio, And Jose Silva-martinezIEEE Transactions On Microwave Theory And Techniques, Vol. 54, No. 12, December 2006
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MOS in weak inversion has speed problemMOS transistor in weak inversion acts like bipolarBipolar available in TSMC 0.18 technology (not a parasitic BJT)Why not using that bipolar transistor to improve linearity ?
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Inter-stage Inductor gain boost
Inter-stage inductor withparasitic capacitance formimpedance match network betweeninput stage and cascoded stageboost gain lower noise figure.
Input match condition will beaffected
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Folded cascode
Low supply voltage
Ld reduces or eliminatesEffect of Cgd1
Good fT
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Design Procedure for Inductive Source Degenerated LNA
Noise factor equations:
22 )14(21211 dd
m
do
T
o QcQg
gF
22 )14(2121
ddm
donf Qc
QggK
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Targeted Specifications
• Frequency 2.4 GHz ISM Band• Noise Figure 1.6 dB• IIP3 -8 dBm• Voltage gain 20 dB• Power < 10mA from 1.8V
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Step 1: Know your process• A 0.18um CMOS Process• Process related
– tox = 4.1e-9 m– = 3.9*(8.85e-12) F/m– = 3.274e-2 m^2/V.s– Vth = 0.52 V
• Noise related– = gm/gdo– ~ 2– ~ 3– c = -j0.55
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Step 2: Obtain design guide plots
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Insights:• gdo increases all the way with current
density Iden
• gm saturates when Iden larger than 120A/m– Velocity saturation, mobility degradation ----
short channel effects– Low gm/current efficiency– High linearity
• deviates from long channel value (1) with large Iden
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Obtain design guide plots
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Insights:• fT increases with Vod when Vod is small and
saturates after Vod > 0.3V --- short channel effects
• Cgs/W increases slowly after Vod > 0.2V
• fT begins to degrade when Vod > 0.8V– gm saturates
– Cgs increases
• Should keep Vod ~0.2 to 0.4 V
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Obtain design guide plots
3-D plot for visualinspection
2-D plots fordesign reference
knf vs input Q and current density
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Design trade-offs• For fixed Iden, increasing Q will reduce the
size of transistor thus reduce total power ---- noise figure will become larger
• For fixed Q, reducing Iden will reduce power, but will increase noise factor
• For large Iden, there is an optimal Q for minimum noise factor, but power may be too high
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Obtain design guide plotsLinearity plots :IIP3 vs. gate overdrive and transistor size
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Insights:• MOS transistor IIP3 only, when embedded into
actual circuit:– Input Q will degrade IIP3– Non-linear memory effect will degrade IIP3– Output non-linearity will degrade IIP3
• IIP3 is a very weak function of device size• Generally, large overdrive means large IIP3
– But the relationship between IIP3 and gate overdrive is not monotonic
– There is a local maxima around 0.1V overdrive
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Step 4: Estimate fT
Small current budget ( < 10mA )does not allow large gate over drive :
Vod ~ 0.2 V ~ 0.4 VfT ~ 40 ~ 44 GHz
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Step 4: Determine Iden, Q andCalculate Device Size
Select Iden = 70 A/m, =>Vod~0.23V
Gm/W~0.4
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If Q = 4, IIP3 will have enough margin:Estimated IIP3:IIP3(from curve) – 20log(Q) = 8-12 = -4dBmSpecs require: -8 dBm
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Q=4 and Iden = 70A/m meet thenoise factor requirement
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Gm=0.4*128 ~ 50 mS fT = gm/(Cgs*2pi) = 48 GHz
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Step 6: Simulation Verification
Large deviation
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Comparison between targeted specs and simulation results
Parameter Target SimulatedNoise Figure 1.6 dB 0.8 dBDrain Current < 10mA 8 mAVoltage gain 20 dB 21 dBIIP3 -8 dBm -6.4 dBmP1dB -20dbmS11 -17 dBPower supply 1.8 V 1.8 V