low level programming and computer architecture …...low level programming and computer...

Low Level Programming and Computer ArchitectureLecture 2

Carl Henrik Ek{chek}@csc.kth.se

Royal Institute of Technology

March 22, 2013

Ek KTH

Low Level Programming and Computer Architecture

Last Lecture• Introduction to course• Structure of course• What is computer science?

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This Lecture• What is a computer?• Computer architecture• What is a program?• Program execution

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Remote Access

Remote Access• We will try evaluate labs on

CSC machines• CSC Remote Access

• Straight forward on any *nixOS

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http://www.kth.se/en/csc/it-support-csc/environment/remote/remote-1.70565

What is a computer?

Alan Turing• Father of Computer Science• Enigma code-breaker• Turing Test

I what can be considered intelligence

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What is a computer?

Turing Complete• Turing Machine

I Programming LanguageI What can be done by algorithmic

computation!• Church-Turing thesis

I Functions that are algorithmicallycomputable only if it is computable by aTuring machine.

• Cannot be proven (Godel) “HaltingProblem”

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Computer Architecture

CPU• Computational Unit• “Brain”• Is in specific state• Logic

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Control Unit• Controls execution• Fetches instruction• Decodes instruction• Flow

ALU• Arithmetic and Logic Unit• INPUT

I operands• OUTPUT

I Result of computation

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Registers• Stores Data in the CPU• General Purpose

I Data, Address• Special Purpose

I Program counterI Stack pointerI Status register

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Introduction

1-2

M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL

MOTOROLA

1.1 INTEGER UNIT USER PROGRAMMING MODEL

Figure 1-1 illustrates the integer portion of the user programming model. It consists of thefollowing registers:

• 16 General-Purpose 32-Bit Registers (D7 – D0, A7 – A0) • 32-Bit Program Counter (PC) • 8-Bit Condition Code Register (CCR)

.

1.1.1 Data Registers (D7 – D0)

These registers are for bit and bit field (1 – 32 bits), byte (8 bits), word (16 bits), long-word(32 bits), and quad-word (64 bits) operations. They also can be used as index registers.

1.1.2 Address Registers (A7 – A0)

These registers can be used as software stack pointers, index registers, or base addressregisters. The base address registers can be used for word and long-word operations.Register A7 is used as a hardware stack pointer during stacking for subroutine calls andexception handling. In the user programming model, A7 refers to the user stack pointer(USP).

Figure 1-1. M68000 Family User Programming Model

A0A1A2A3A4A5A6

A7 (USP)

PC

D0D1D2D3D4D5D6D7

DATA REGISTERS

ADDRESS REGISTERS

USER STACK POINTERPROGRAM COUNTER

CCRCONDITION CODE REGISTER

01531

01531

0715

031

01531

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Introduction

MOTOROLA


1-11

supported, where T0 is always zero, and only one system stack where the M-bit is alwayszero. I2, I1, and I0 define the interrupt mask level.

.

1.3.3 Vector Base Register (VBR)

The VBR contains the base address of the exception vector table in memory. Thedisplacement of an exception vector adds to the value in this register, which accesses thevector table.

1.3.4 Alternate Function Code Registers (SFC and DFC)

The alternate function code registers contain 3-bit function codes. Function codes can beconsidered extensions of the 32-bit logical address that optionally provides as many as eight4-Gbyte address spaces. The processor automatically generates function codes to selectaddress spaces for data and programs at the user and supervisor modes. Certaininstructions use SFC and DFC to specify the function codes for operations.

1.3.5 Acu Status Register (MC68EC030 only)

The access control unit status register (ACUSR) is a 16-bit register containing the statusinformation returned by execution of the PTEST instruction. The PTEST instructionsearches the access control (AC) registers to determine a match for a specified address. Amatch in either or both of the AC registers sets bit 6 in the ACUSR. All other bits in theACUSR are undefined and must not be used.

Figure 1-8. Status Register

T1 T0 S M 0 I2 I1 I0 X N Z V C 0 0 0

SYSTEM BYTE USER BYTE

(CONDITION CODE REGISTER)

TRACE ENABLE

INTERRUPT PRIORITY MASK

SUPERVISOR/USER STATE

MASTER/INTERRUPT STATE EXTEND

NEGATIVE

ZERO OVERFLOW CARRY

15 14 13 12 11 10 9 8 7 5 6 4 3 2 1 0

T1 T0

0 0

1 0

0 1

1 1

NO TRACE

TRACE ON ANY INSTRUCTION

TRACE ON CHANGE OF FLOW

UNDEFINED

S M

0 x

1 0

1 1

USP

ISP

MSP

ACTIVE STACK TRACE MODE

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Machine Language

Instructions• RISC - Reduced Instruction

SetI Few, simple and fast

instructionsI ARM, PowerPC

• CISC - Complex InstructionSetI Lots of powerful instructionsI Intel, AMD

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Machine Language

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Instructions

Addressing Capabilities

2-2


MOTOROLA

An instruction specifies the function to be performed with an operation code and defines thelocation of every operand. Instructions specify an operand location by register specification,the instruction’s register field holds the register’s number; by effective address, theinstruction’s effective address field contains addressing mode information; or by implicitreference, the definition of the instruction implies the use of specific registers.

The single effective address operation word format is the basic instruction word (see Figure2-2). The encoding of the mode field selects the addressing mode. The register fieldcontains the general register number or a value that selects the addressing mode when themode field contains opcode 111. Some indexed or indirect addressing modes use acombination of the simple effective address operation word followed by a brief extensionword. Other indexed or indirect addressing modes consist of the simple effective addressoperation word and a full extension word. The longest instruction is a MOVE instruction witha full extension word for both the source and destination effective addresses and eight otherextension words. It also contains 32-bit base displacements and 32-bit outer displacementsfor both source and destination addresses. Figure 2-2 illustrates the three formats used inan instruction word; Table 2-1 lists the field definitions for these three formats.

SINGLE EFFECTIVE ADDRESS OPERATION WORD FORMAT

BRIEF EXTENSION WORD FORMAT

FULL EXTENSION WORD FORMAT

Figure 2-2. Instruction Word Specification Formats

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

X X X X X X X X X XEFFECTIVE ADDRESS

MODE REGISTER

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D/A REGISTER W/L SCALE 0 DISPLACEMENT

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D/A REGISTER W/L SCALE 1 BS IS BD SIZE 0 I/IS

BASE DISPLACEMENT (0, 1, OR 2 WORDS) OUTER DISPLACEMENT (0, 1, OR 2 WORDS)

Structure• OP-Code

I Decides operation• Operand

I OP-code dependentI “Parameters”

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Instructions

Data Transfer• MOVE, LOAD, STORE• SWAP

• ConditionalI zero-extend, sign-extend

• LEA

• Size dependent

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InstructionsInteger Instructions

4-116 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

MOVE Move Data from Source to Destination MOVE (M68000 Family)

Operation: Source → Destination

Assembler Syntax: MOVE < ea > , < ea >

Attributes: Size = (Byte, Word, Long)

Description: Moves the data at the source to the destination location and sets the conditioncodes according to the data. The size of the operation may be specified as byte, word,or long. Condition Codes:

X — Not affected. N — Set if the result is negative; cleared otherwise. Z — Set if the result is zero; cleared otherwise. V — Always cleared. C — Always cleared.

Instruction Format:

Instruction Fields: Size field—Specifies the size of the operand to be moved.

01 — Byte operation 11 — Word operation 10 — Long operation

X N Z V C — ∗ ∗ 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 SIZEDESTINATION SOURCE

REGISTER MODE MODE REGISTER

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Instructions

Flow Control• Non-Conditional

I JUMP, BRANCH• Conditional

I STATUS REGISTER

• Determine state of CPU• Set state TST, CMP

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InstructionsInteger Instructions

MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-25

Bcc Branch Conditionally Bcc (M68000 Family)

Operation: If Condition True Then PC + dn → PC

Assembler Syntax: Bcc < label >

Attributes: Size = (Byte, Word, Long*) *(MC68020, MC68030, and MC68040 only)

Description: If the specified condition is true, program execution continues at location (PC)+ displacement. The program counter contains the address of the instruction word forthe Bcc instruction plus two. The displacement is a twos-complement integer thatrepresents the relative distance in bytes from the current program counter to thedestination program counter. If the 8-bit displacement field in the instruction word iszero, a 16-bit displacement (the word immediately following the instruction) is used. Ifthe 8-bit displacement field in the instruction word is all ones ($FF), the 32-bitdisplacement (long word immediately following the instruction) is used. Condition codecc specifies one of the following conditional tests (refer to Table 3-19 for moreinformation on these conditional tests):

Condition Codes: Not affected.

Mnemonic Condition Mnemonic ConditionCC(HI) Carry Clear LS Low or Same

CS(LO) Carry Set LT Less Than

EQ Equal MI Minus

GE Greater or Equal NE Not Equal

GT Greater Than PL Plus

HI High VC Overflow Clear

LE Less or Equal VS Overflow Set

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Instructions

Arithmetic/Logic• Logic

I AND, OR, XORI masking

• Rotate and Shift• Arithmetic

I ADD, SUB

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Instructions

Integer Instructions

4-4


MOTOROLA

ADD

Add

ADD

(M68000 Family)

Operation:

Source + Destination

→

Destination

Assembler

ADD < ea > ,Dn

Syntax:

ADD Dn, < ea >

Attributes:

Size = (Byte, Word, Long)

Description:

Adds the source operand to the destination operand using binary addition andstores the result in the destination location. The size of the operation may be specifiedas byte, word, or long. The mode of the instruction indicates which operand is thesource and which is the destination, as well as the operand size.

Condition Codes:

X — Set the same as the carry bit. N — Set if the result is negative; cleared otherwise. Z — Set if the result is zero; cleared otherwise. V — Set if an overflow is generated; cleared otherwise. C — Set if a carry is generated; cleared otherwise.

Instruction Format:

X N Z V C

∗ ∗ ∗ ∗ ∗

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1 1 0 1 REGISTER OPMODEEFFECTIVE ADDRESS

MODE REGISTER

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Instructions


MOTOROLA


4-5

ADD

Add

ADD

(M68000 Family)

Instruction Fields:

Register field—Specifies any of the eight data registers.

Opmode field

Effective Address field—Determines addressing mode.

a. If the location specified is a source operand, all addressing modes can be used as listed in the following tables:

*Word and long only**Can be used with CPU32.

Byte Word Long Operation

000 001 010 < ea > + Dn

→

Dn 100 101 110 Dn + < ea >

→

< ea >

Addressing Mode Mode Register Addressing Mode Mode Register

Dn 000 reg. number:Dn (xxx).W 111 000

An* 001 reg. number:An (xxx).L 111 001

(An) 010 reg. number:An #<data> 111 100

(An) + 011 reg. number:An

– (An) 100 reg. number:An

(d

16

,An) 101 reg. number:An (d

16

,PC) 111 010

(d

8

,An,Xn) 110 reg. number:An (d

8

,PC,Xn) 111 011

MC68020, MC68030, and MC68040 only

(bd,An,Xn)** 110 reg. number:An (bd,PC,Xn)† 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

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Memory

• Connected to CPU by BUS• BUS

I Width

• Additional devices connected to BUS• IRQ, I/O Adresses

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Memory

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Memory

Types• Registers• Cache• Main Memory• Storage

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Memory

Addressing• Address space• Specific address locations• byte addressable• Word size, size of address space

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Program Execution

Program Counter• Address to memory to “execute”• Start position

Instruction Register• Stores instruction

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Program Execution

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Assembler• Assigns mnemonics• Symbolic references• “Assembles” program to

memory

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Example

Writing Code• Move 127 bytes in memory

1. Move data from memory to CPU2. Move data from CPU to memory3. Loop

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4-110 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

LEA Load Effective Address LEA (M68000 Family)

Operation: < ea > → An

Assembler Syntax: LEA < ea > ,An

Attributes: Size = (Long)

Description: Loads the effective address into the specified address register. All 32 bits ofthe address register are affected by this instruction.

Condition Codes: Not affected.

Instruction Format:

Instruction Fields: Register field—Specifies the address register to be updated with the effective address.

Effective Address field—Specifies the address to be loaded into the address register.Only control addressing modes can be used as listed in the following tables:

*Can be used with CPU32.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 1 0 0 REGISTER 1 1 1EFFECTIVE ADDRESS

MODE REGISTER

Addressing Mode Mode Register Addressing Mode Mode RegisterDn — — (xxx).W 111 000

An — — (xxx).L 111 001

(An) 010 reg. number:An #<data> — —

(An) + — —

– (An) — —

(d16,An) 101 reg. number:An (d16,PC) 111 010

(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) 111 011

MC68020, MC68030, and MC68040 only(bd,An,Xn) 110 reg. number:An (bd,PC,Xn)* 111 011

([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011

([bd,An],Xn,od) 110 reg. number:An ([bd,PC],Xn,od) 111 011

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Code

move .l #0 ,d1lea src ,a0lea dest ,a1loopmove .b (a0 ) ,d0move .b d0 , ( a1 )adda .l #1 ,a0adda .l #1 ,a1add .l #1 ,d0cmp .l #128−1,d1bne loop

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8-4 MC68000 8-/16-/32-MICROPROCESSORS UISER'S MANUAL MOTOROLA

Table 8-4. Standard Instruction Execution TimesInstruction Size op<ea>, An† op<ea>, Dn op Dn, <M>

ADD/ADDA Byte, Word 8(1/0)+ 4(1/0)+ 8(1/1)+

Long 6(1/0)+** 6(1/0)+** 12(1/2)+

AND Byte, Word — 4(1/0)+ 8(1/1)+

Long — 6(1/0)+** 12(1/2)+

CMP/CMPA Byte, Word 6(1/0)+ 4(1/0)+ —

Long 6(1/0)+ 6(1/0)+ —

DIVS — — 158(1/0)+* —

DIVU — — 140(1/0)+* —

EOR Byte, Word — 4(1/0)*** 8(1/1)+

Long — 8(1/0)*** 12(1/2)+

MULS — — 70(1/0)+* —

MULU — — 70(1/0)+* —

OR Byte, Word — 4(1/0)+ 8(1/1)+

Long — 6(1/0)+** 12(1/2)+

SUB Byte, Word 8(1/0)+ 4(1/0)+ 8(1/1)+

Long 6(1/0)+** 6(1/0)+** 12(1/2)+

+ Add effective address calculation time.† Word or long only* Indicates maximum basic value added to word effective address time

** The base time of six clock periods is increased to eight if the effective address mode isregister direct or immediate (effective address time should also be added).

*** Only available effective address mode is data register direct.DIVS, DIVU — The divide algorithm used by the MC68000 provides less than 10% difference

between the best- and worst-case timings.MULS, MULU — The multiply algorithm requires 38+2n clocks where n is defined as:

MULU: n = the number of ones in the <ea>MULS: n=concatenate the <ea> with a zero as the LSB; n is the resultant number of 10

or 01 patterns in the 17-bit source; i.e., worst case happens when the sourceis $5555.

8.4 IMMEDIATE INSTRUCTION EXECUTION TIMESThe numbers of clock periods shown in Table 8-5 include the times to fetch immediateoperands, perform the operations, store the results, and read the next operation. The totalnumber of clock periods, the number of read cycles, and the number of write cycles areshown in the previously described format. The number of clock periods, the number ofread cycles, and the number of write cycles, respectively, must be added to those of theeffective address calculation where indicated by a plus sign (+).

In Table 8-5, the following notation applies:# — Immediate operandDn — Data register operandAn — Address register operandM — Memory operand

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Table 8-1. Effective Address Calculation TimesAddressing Mode Byte, Word Long

DnAn

RegisterData Register DirectAddress Register Direct

0(0/0)0(0/0)

0(0/0)0(0/0)

(An)(An)+

MemoryAddress Register IndirectAddress Register Indirect with Postincrement

4(1/0)4(1/0)

8(2/0)8(2/0)

–(An)(d16, An)

Address Register Indirect with PredecrementAddress Register Indirect with Displacement

6(1/0)8(2/0)

10(2/0)12(3/0)

(d8, An, Xn)*(xxx).W

Address Register Indirect with IndexAbsolute Short

10(2/0)8(2/0)

14(3/0)12(3/0)

(xxx).L(d8, PC)

Absolute LongProgram Counter Indirect with Displacement

12(3/0)8(2/0)

16(4/0)12(3/0)

(d16, PC, Xn)*#<data>

Program Counter Indirect with IndexImmediate

10(2/0)4(1/0)

14(3/0)8(2/0)

*The size of the index register (Xn) does not affect execution time.

8.2 MOVE INSTRUCTION EXECUTION TIMESTables 8-2 and 8-3 list the numbers of clock periods for the move instructions. The totalsinclude instruction fetch, operand reads, and operand writes. The total number of clockperiods, the number of read cycles, and the number of write cycles are shown in thepreviously described format.

Table 8-2. Move Byte and Word Instruction Execution TimesDestination

Source Dn An (An) (An)+ –(An) (d16, An) (d8, An, Xn)* (xxx).W (xxx).L

DnAn(An)

4(1/0)4(1/0)8(2/0)

4(1/0)4(1/0)8(2/0)

8(1/1)8(1/1)

12(2/1)

8(1/1)8(1/1)

12(2/1)

8(1/1)8(1/1)

12(2/1)

12(2/1)12(2/1)16(3/1)

14(2/1)14(2/1)18(3/1)

12(2/1)12(2/1)16(3/1)

16(3/1)16(3/1)20(4/1)

(An)+–(An)(d16, An)

8(2/0)10(2/0)12(3/0)

8(2/0)10(2/0)12(3/0)

12(2/1)14(2/1)16(3/1)

12(2/1)14(2/1)16(3/1)

12(2/1)14(2/1)16(3/1)

16(3/1)18(3/1)20(4/1)

18(3/1)20(3/1)22(4/1)

16(3/1)18(3/1)20(4/1)

20(4/1)22(4/1)24(5/1)

(d8, An, Xn)*(xxx).W(xxx).L

14(3/0)12(3/0)16(4/0)

14(3/0)12(3/0)16(4/0)

18(3/1)16(3/1)20(4/1)

18(3/1)16(3/1)20(4/1)

18(3/1)16(3/1)20(4/1)

22(4/1)20(4/1)24(5/1)

24(4/1)22(4/1)26(5/1)

22(4/1)20(4/1)24(5/1)

26(5/1)24(5/1)28(6/1)

(d16, PC)(d8, PC, Xn)*#<data>

12(3/0)14(3/0)8(2/0)

12(3/0)14(3/0)8(2/0)

16(3/1)18(3/1)12(2/1)

16(3/1)18(3/1)12(2/1)

16(3/1)18(3/1)12(2/1)

20(4/1)22(4/1)16(3/1)

22(4/1)24(4/1)18(3/1)

20(4/1)22(4/1)16(3/1)

24(5/1)26(5/1)20(4/1)

*The size of the index register (Xn) does not affect execution time.

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MOTOROLA MC68000 8-/16-/32-MICROPROCESSORS USER’S MANUAL 8-7

8.7 BIT MANIPULATION INSTRUCTION EXECUTION TIMESTable 8-8 lists the timing data for the bit manipulation instructions. The total number ofclock periods, the number of read cycles, and the number of write cycles are shown in thepreviously described format. The number of clock periods, the number of read cycles, andthe number of write cycles, respectively, must be added to those of the effective addresscalculation where indicated by a plus sign (+).

Table 8-8. Bit Manipulation Instruction Execution TimesDynamic Static

Instruction Size Register Memory Register Memory

BCHG Byte — 8(1/1)+ — 12(2/1)+

Long 8(1/0)* — 12(2/0)* —

BCLR Byte — 8(1/1)+ — 12(2/1)+

Long 10(1/0)* — 14(2/0)* —

BSET Byte — 8(1/1)+ — 12(2/1)+

Long 8(1/0)* — 12(2/0)* —

BTST Byte — 4(1/0)+ — 8(2/0)+

Long 6(1/0) — 10(2/0) —

+Add effective address calculation time.* Indicates maximum value; data addressing mode only.

8.8 CONDITIONAL INSTRUCTION EXECUTION TIMESTable 8-9 lists the timing data for the conditional instructions. The total number of clockperiods, the number of read cycles, and the number of write cycles are shown in thepreviously described format.

Table 8-9. Conditional Instruction Execution Times

Instruction DisplacementBranchTaken

Branch NotTaken

Bcc Byte 10(2/0) 8(1/0)

Word 10(2/0) 12(2/0)

BRA Byte 10(2/0) —

Word 10(2/0) —

BSR Byte 18(2/2) —

Word 18(2/2) —

DBcc cc true — 12(2/0)

cc false, Count Not Expired 10(2/0) —

cc false, Counter Expired — 14(3/0)

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Code2

move .l #256−2,d1lea src ,a0lea dest ,a1loopmove .b (a0 ) ,d0move .b d0 , ( a1 )adda .l #1 ,a0adda .l #1 ,a1sub .b #2 ,d1beq loop

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Table 8-4. Standard Instruction Execution TimesInstruction Size op<ea>, An† op<ea>, Dn op Dn, <M>

ADD/ADDA Byte, Word 8(1/0)+ 4(1/0)+ 8(1/1)+

Long 6(1/0)+** 6(1/0)+** 12(1/2)+

AND Byte, Word — 4(1/0)+ 8(1/1)+

Long — 6(1/0)+** 12(1/2)+

CMP/CMPA Byte, Word 6(1/0)+ 4(1/0)+ —

Long 6(1/0)+ 6(1/0)+ —

DIVS — — 158(1/0)+* —

DIVU — — 140(1/0)+* —

EOR Byte, Word — 4(1/0)*** 8(1/1)+

Long — 8(1/0)*** 12(1/2)+

MULS — — 70(1/0)+* —

MULU — — 70(1/0)+* —

OR Byte, Word — 4(1/0)+ 8(1/1)+

Long — 6(1/0)+** 12(1/2)+

SUB Byte, Word 8(1/0)+ 4(1/0)+ 8(1/1)+

Long 6(1/0)+** 6(1/0)+** 12(1/2)+

+ Add effective address calculation time.† Word or long only* Indicates maximum basic value added to word effective address time

** The base time of six clock periods is increased to eight if the effective address mode isregister direct or immediate (effective address time should also be added).

*** Only available effective address mode is data register direct.DIVS, DIVU — The divide algorithm used by the MC68000 provides less than 10% difference

between the best- and worst-case timings.MULS, MULU — The multiply algorithm requires 38+2n clocks where n is defined as:

MULU: n = the number of ones in the <ea>MULS: n=concatenate the <ea> with a zero as the LSB; n is the resultant number of 10

or 01 patterns in the 17-bit source; i.e., worst case happens when the sourceis $5555.

8.4 IMMEDIATE INSTRUCTION EXECUTION TIMESThe numbers of clock periods shown in Table 8-5 include the times to fetch immediateoperands, perform the operations, store the results, and read the next operation. The totalnumber of clock periods, the number of read cycles, and the number of write cycles areshown in the previously described format. The number of clock periods, the number ofread cycles, and the number of write cycles, respectively, must be added to those of theeffective address calculation where indicated by a plus sign (+).

In Table 8-5, the following notation applies:# — Immediate operandDn — Data register operandAn — Address register operandM — Memory operand

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Interupts• Avoid polling• Interupt Handler• Trap (software)• Hardware

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I/O - Input/Output

Memory Mapped• Device connected to same BUS• Allows for DMA

Port Mapped• Separate address space

Interupt• Dedicated Interupt line• IRQ

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Advanced Topics

Pipelining• communication is bottle-neck• Pre-fetch

Multiprocessor• Share computations• GPU

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Optimisation

Instruction Level• Efficient use of instructions• Reduce to bit-wise operations• Order instructions• Compilers can do a lot of this for you

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Optimisation

Memory Level• Most programs will need to use lots of different memory• Speed of loading/storing

1. Register2. Cache3. Main memory4. Storage

• Structure computations with respect to memory• Reduce waitstate, “von Neumann bottleneck”

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Next Lecture• Tuesday 26th of March 10-12

D42• How is data stored in a

computer• Manipulation of data• Binary Arithmetics• Boolean Logic• All material for Lab 2

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e.o.f.

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low level programming and computer architecture …...low level programming and computer...

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