low-latency polar codes via hybrid...
TRANSCRIPT
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Low-Latency Polar Codes via Hybrid Decoding
Bin Li*, Hui Shen*, David Tse+, Wen Tong*
*Huawei Technologies, China + Stanford University, USA
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Contents
Excellent Performance of Polar Codes
Polar SC Decoder: Latency Problem
Proposed Hybrid Decoder
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Contents
Excellent Performance of Polar Codes
Polar SC Decoder: Latency Problem
Proposed Hybrid Decoder
4
Excellent Performance can be achieved by
1) Concatenation with CRC [1]
2) SC-LIST Decoding [1]
3) Adaptive SC-LIST Decoding [2]
[1] I. Tal, A. Vardy, “List Decoding of Polar Codes”, arXiv.1206.0050.
[2] B. Li, H.Shen, D. Tse,” An Adaptive Successive Cancellation List Decoder of Polar
Codes with Cyclic Redundancy Check”, IEEE Communications Letters, Dec. 2012.
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Adaptive List decoded Polar Code (N=2048, R=1/2), 16-CRC
0.25dB from finite block size limit with Lmax=2^18 Li-Shen-Tse, 2012.
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.910
-4
10-3
10-2
10-1
Eb/No (dB)
FE
R
Polar Code (2048,1040) concatenated with 16-Bit CRC, R=1/2
FER,Lmax=32
FER,Lmax=2048
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N=256, R=1/2, 16-CRC
Much better than state-of-the-art LDPC code
1.8 1.9 2 2.1 2.2 2.3 2.4 2.510
-4
10-3
10-2
10-1
Eb/No(dB)
FE
R
Polar Code (256,144) Concatenated with 16-Bit CRC, R=1/2
LDPC(256,128),T.Richardson
Polar code, Lmax=32
Polar code ,Lmax=2048
Polar code,Lmax=32768
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Contents
Excellent Performance of Polar Codes
Polar SC Decoder: Latency Problem
Proposed Hybrid Decoder
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SC Decoder: Latency Problem
SC decoder decodes bit-by-it in serial fashion
2N-2 cycles are needed to decode one code of length N
This latency cannot be reduced by hardware parallelization
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ML Decoder: Low Latency
ML decoder decodes all bits simultaneously
Latency can be made arbitrarily small by
increasing hardware parallelization.
Infeasible to implement in practice.
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Contents
Excellent Performance of Polar Codes
SC Decoder: Latency Problem
Our Proposed Hybrid Decoder
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General Decoder Decomposition
2k Outer SC Decoders+ 2n-k Inner SC Decoders
Inner SC
decoders
operate in
parallel:
2k+1-2 cycles
Outer SC
decoders
operate
serially:
2k[ 2n-k+1-2]
=2n+1-2k+1
cycles
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Our Proposed Hybrid Decoder
Hybrid Decoder, k=n, SC decoder, k=0, ML decoder
Inner SC
decoders
operate in
parallel:
2k+1-2 cycles
Outer ML
decoders
operate
serially:
2k cycles
Replace SC
decoder with
ML decoder
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Latency Reduction by Hybrid Decoder
The latency ratio of hybrid over SC decoder is
3*2n-k+1/2n+1=3/2n-k
If k=n-4, 16 inner decoders working in parallel, the above
ration is 3/16.
The parameter k is used to tradeoff latency and complexity
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Pictorially Explain of Simplified ML Search
Pictorially Explain the Simplification of ML Search:
)1(
1C )1(
1C
)1(
1D )2(
1D
One code is decomposed:
one repetition and two independent codes
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Recursive ML Decoder
Recursive Simplification of ML Search:
)1(
1C )1(
1C
)1(
2C )1(
2C )2(
2C )2(
2C
)5(
2D )6(
2D )7(
2D )8(
2D)1(
2D )3(
2D)2(
2D )4(
2D
)1(
1C )1(
1C
)1(
2C )1(
2C )2(
2C )2(
2C
)1(
3C )1(
3C )2(
3C )2(
3C )3(
3C )3(
3C )4(
3C )4(
3C
)1(
3D )3(
3D )5(
3D )7(
3D)2(
3D )4(
3D )6(
3D )8(
3D