low k (k=3.0)/cu dual damascene process for sub-40nm dram · low k (k=3.0)/cu dual damascene...
TRANSCRIPT
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AMC20102010.10.05
Process Development TeamSamsung Electronics
S. D. Nam
Contents
DRAM BEOL vs. Logic BEOL
Why Low-k IMD into DRAM ?
Low-k/Cu Dual Damascene Test Structure
Dual Damascene Process- Low-k & Integration Processes
Electrical Properties & EM Reliability
Effective-k after Integration
Packaging- Laser Fusing, Sawing, Wire Bonding
Conclusion
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Process Development TeamSamsung Electronics
S. D. Nam
DRAM BEOL vs. Logic BEOL
DRAM Logic
Dual damascene A/R > 4.0 < 3.0
Low-k application Global metal Intermediate metal
Crack-stop layer No Yes
Fusing method Laser blowing Electrical
More Difficult Structure
Speed Critical Layer !vs.Mechanically Vurnerable to Harsh Package Processes
Thermal Expansion DifferenceAdhesion, Modulus/Hardness
Chip Size Consideration !vs.Crack Propagation into Main Chip
Forget about Low-k ! Simply Add a Metal ! :) Even though, it is More Expensive ! :(
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AMC20102010.10.05
Process Development TeamSamsung Electronics
S. D. Nam
DRAM BEOL vs. Logic BEOL
M2
Cu
TEOSPE-SiN
PSPI
TEOS
PAD-Al
M1
Cu
TEOS
SiNTEOS
Global
Passivation
Intermediate
PSPI
TEOS
PAD-AlPE-SiN
※ Arbitrary scale
For conventional 2Cu + 1Al pad DRAM,Only 1 intermediate and 1 global metal under passivation
Low-k
IMD SiCN
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AMC20102010.10.05
Process Development TeamSamsung Electronics
S. D. Nam
1.5
2.0
2.5
3.0
3.5
4.0
4.5
1998
1999
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2004
2005
2006
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2008
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2010
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2015
2016
2017
2018
2019
2020
2021
2022
2023
Year
Die
lect
ric
Const
ant
ITRS 2000
ITRS 2006
ITRS 2008
Historical ITRS roadmap for DRAM BEOL
Shift of Low-k adoptioninto DRAM
Still, no DRAM chip makers use Low-k IMD for their major products. Why ?→ Hesitation in Adopting Low-k to DRAM BEOL
Adding a metal instead of Low-k adoption→ Low-k reliabilty issue
* ITRS 2000, 2006, 2008 interconnect roadmap
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AMC20102010.10.05
Process Development TeamSamsung Electronics
S. D. Nam
Test Vehicle (sub-40nm)
M2
Cu
TEOSPE-SiN
PSPI
TEOS
PAD-Al
M1
Cu
TEOS
SiNTEOS
M2
Cu
TEOSPE-SiN
PSPI
TEOS
PAD-Al
M1
Cu
Low-k
IMD
SiNTEOS
SiCN
Comparison of Conventional 2Cu +1Al pad /w TEOS and /w Low-k V1/M2 IMD
Electrical properties, Reliability, Packaging Issues
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AMC20102010.10.05
Process Development TeamSamsung Electronics
S. D. Nam
TEM of Test Structure
M2
Cu
TEOSPE-SiN
PSPI
TEOS
PAD-Al
M1
Cu
Low-k
IMD
SiNTEOS
SiCN
M2 Cu
M1 CuW
Low-k
IMD
Low-k IMD & SiCN DB @ V1/M2
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Process Development TeamSamsung Electronics
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VFDD process scheme
⑩ CMP
① Via photo
SiCN
Low-k
IMD
PR
Oxide
② Via etch ③ Via fill
Via filler
④ Oxide HM
Oxide
⑤ Trench photo
PR
⑦ Via filler ashing ⑨ clean/PVD/EP⑥ Trench etch
Cu
⑧ SiCN open
※ VFDD (Via First Dual Damascene)
Conventional VFDD processes
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Process Development TeamSamsung Electronics
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Low-k & Integration processes
Low-k IMD
Deposition Method PECVD
Deposition Chemistry Siloxane based precursor / Oxygen ambient
Pristine k 3.0
SiCN ESL/DB
Deposition Method PECVD
Deposition Chemistry Silane based precursor / Ammonia ambient
Pristine k 5.0
Pre-treatment Ammonia ambient plasma
Integration
Design rule < 40nm (Gate size)
Scheme VFDD
Etching Fluorocarbon / Oxygen based ambient
Ashing Oxygen based ambient
Wet Cleaning Diluted Hydrofluorine acid
Cu BM Ta based PVD
EP Cu Pure Cu
Cu CMP Same as SiO2 IMD
Conventional VFDD processes for Low-k IMD & SiCN DB @ V1/M2
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Process Development TeamSamsung Electronics
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Electrical properties
0
20
40
60
80
100
Normalized via-1 Rc (a.u.)
Dis
trib
uti
on
(%
)
SiO2 / Cu
Low-k / Cu
0
20
40
60
80
100
Normalized metal-2 Rs (a.u.)
Dis
trib
uti
on
(%
)
SiO2 / Cu
Low-k / Cu
0
20
40
60
80
100
Normalized metal-2 leakage (a.u.)
Dis
trib
uti
on
(%
)
SiO2 / Cu
Low-k / Cu
0
20
40
60
80
100
Normalized time to failure (a.u.)
Dis
trib
uti
on
(%
)
SiO2 / Cu
Low-k / Cu
Via-1 Rc Metal-2 Rs
Metal-2 Leakage Metal-2 EM Reliability
No difference of Via-1 Rc, Metal-2 Rs, Metal-2 Leakage and EM Reliability
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Process Development TeamSamsung Electronics
S. D. Nam
42
44
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54
56
2.8 3.0 3.2 3.4 3.6 3.8 4.0
k-valueC
ap
ac
ita
nc
e [
pF
]
Effective-k of Low-k IMD after Integration
M2Cu
3.14
M2 Effective-k = 3.14 (Pristine k = 3.0)
< 5% Increase(Robust Enough to be Compatible with the Conventional DRAM BEOL)
Computational Simulation
with the Pattern Dimensions by TEM
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AMC20102010.10.05
Process Development TeamSamsung Electronics
S. D. Nam
Packaging : Laser Fusing
CTE
(ppm/℃)
Relative adhesion energy
with low-k (a.u.)
@ 4pts bending technique
Low-k 14 * -
SiCN 3.9 * 2.5
SiN 1.5 * 1.0
Cu 16 * N/A
* N. Che´rault, Microelectronic Engineering, vol. 82, pp. 368–373, 2005.* Myung-Chan Jo, Applied Surface Science, vol. 140, pp. 12–18, 1999.
M2
Cu
TEOSPE-SiN
PSPI
TEOS
PAD-Al
M1
Cu
Low-k
IMD
SiNTEOS
SiCN
SiN/SiO2 SiN/Low-k
SiCN/Low-k SiCN/Low-k (Modified)
Successful Laser Fusing with Modified Scheme@ Low-k/Cu Fuse
Poor adhesion
Better adhesionBut, Lower modulus
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Process Development TeamSamsung Electronics
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Packaging : Sawing
Top view Vertical view
No encroachment into PSPI edge No severe chipping
PSPI edge
Mainchip
Scribelane
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AMC20102010.10.05
Process Development TeamSamsung Electronics
S. D. Nam
Packaging : Wire Bonding
Failure analysis
With Optimized NH3 plasma pre-treatment,No delamination was observed during Bond Pull Test
Delamination @ M2 SiCN DB and Low-k IMD interface→ Due to the low interfacial adhesion energy
Al pad
TEOSSiCN
Low-k IMDSiCN
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AMC20102010.10.05
Process Development TeamSamsung Electronics
S. D. Nam
Conclusion
Tough environment for Low-k Adoption into DRAM BEOL compared toLogic BEOL
Low-k/Cu Dual Damascene Evaluation with Conventional DRAM BEOL
Electrically No Difference(Via-1 Rc, Metal-2 Rs, Metal-2 Leakage and EM Reliability)
Effective-k of Low-k IMD < 5% Increase(Robust enough to be compatible with the conventional DRAM BEOL)
Compatible with Conventional DRAM Packaging(Laser Fusing, Sawing and Wire Bonding)
Promising Candidate for the Next Generation DRAM Interconnection
Further Study on Integration and Package is Required