low frequency noise in advanced cmos technologypf645xz5659/cy_thesis-augment… · to find the...

LOW FREQUENCY NOISE IN ADVANCED CMOS TECHNOLOGY

A DISSERTATION

SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING

AND THE COMMITTEE ON GRADUATE STUDIES

OF STANFORD UNIVERSITY

IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF

DOCTOR OF PHILOSOPHY

Chia-Yu Chen

August 2010

http://creativecommons.org/licenses/by-nc/3.0/us/

This dissertation is online at: http://purl.stanford.edu/pf645xz5659

© 2011 by Chia-Yu Chen. All Rights Reserved.

Re-distributed by Stanford University under license with the author.

This work is licensed under a Creative Commons Attribution-Noncommercial 3.0 United States License.

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http://purl.stanford.edu/pf645xz5659

I certify that I have read this dissertation and that, in my opinion, it is fully adequatein scope and quality as a dissertation for the degree of Doctor of Philosophy.

Robert Dutton, Primary Adviser


Boris Murmann


Yoshio Nishi

Approved for the Stanford University Committee on Graduate Studies.

Patricia J. Gumport, Vice Provost Graduate Education

This signature page was generated electronically upon submission of this dissertation in electronic format. An original signed hard copy of the signature page is on file inUniversity Archives.

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v

Abstract

The main topic of this thesis is to investigate the CMOS scaling impacts on

low-frequency noise properties. Such effects come from size (channel length/width)

scaling, adoption of advanced doping profiles (halo pocket implantation), incorporation

of alternative gate oxide (high-κ) and channel materials (SiGe).

Device-level simulation capabilities have been developed to investigate

low-frequency noise behavior. The numerical model is based on the impedance field

method; it accounts for a trap-induced carrier number fluctuation and a Hooge mobility

fluctuation. Simulations based on such models have been conducted for high-κ, SiGe

and small gate area transistors, and the results have been correlated with experimental

data, which reveals the important role of the CMOS scaling in the low-frequency noise

behavior.

In the study of high-κ gate dielectric it is found that carrier number fluctuation

becomes the dominant noise source and the non-uniform trap energy distribution is

critical to explain low frequency noise behavior. The negative impact of substrate halo

doping on the low frequency noise is also studied quantitatively.

Low frequency noise characteristics of Si/SiGe/Si hetero-channel MOSFETs

(SiGe MOSFETs) are discussed; the study has been obtained in terms of the noise level

dependence on gate bias, drain currents, and body bias, revealing the important role of

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the dual channels in the low-frequency noise behavior of Si/SiGe/Si hetero-channel

devices.

Low frequency noise characteristics in small gate area MOSFETs are studied in

detail. Due to the ever decreasing gate area, the number of charge carriers in a

MOSFET channel is continually going down, and single-electron low frequency noise

phenomena (random telegraph noise, RTN) becomes visible, which is quite different

from 1/f noise in standard MOSFETs. It is found that random telegraph noise is

directly linked to Positive Bias Temperature Instability (PBTI): PBTI and RTN

originate from the same physical process, charge trapping in the high-κ dielectric. The

correlation between Id- and Ig-RTN is clearly observed. Ig-RTN is directly related to

physical trapping or de-trapping and the Id-RTN reflects sensitivity to charge trapping

as determined by gm.

This dissertation has explored advanced TCAD simulations to overcome obstacles

in low frequency noise and explained a comprehensive view and the underlying

physics for low frequency noise in advanced CMOS technology.

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Acknowledgments

The past five years I have spent at Stanford University have been an incredible

enriching and enjoyable journey. This journey would not have been successful without

many people motivating, supporting, accompanying, and encouraging me.

First and foremost, I would like to thank Prof. Robert W. Dutton for supervising

my doctoral researches and for his generous support and guidance during my graduate

career at Stanford. "I do not want to pre-order a PhD thesis; the most important thing is

to find the topic you really feel interested." "In researches sometimes you do not get

predictable results. However the study can be meaningful in other problems." said Prof.

Robert W. Dutton. He always encourages students' innovation and independent

thinking, which has become the most valuable experience in my study. During my

Ph.D. study, I have come to respect Prof. Dutton not only for his deep insight in

semiconductor technology but for his approach to educating young scholars in this

area.

I would like to extend my gratitude to Professor Yoshio Nishi for serving as my

associate advisor. His help and advice support my graduate studies at Stanford. The

breadth and depth of his knowledge in electrical engineering has never failed to

surprise me. I am grateful to Professor Boris Murmann who served as my orals

committee and reading committee. Professor Murmann gave freely of his time and

expertise and as a result this dissertation is significantly improved for which I am

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deeply appreciative. I am also grateful to Prof. Subhasish Mitra who served as the chair

for my oral defense on very short notice.

I would like to thank Dr. Yang Liu for his great guidance and kind help in my

research. When I discussed research with Dr. Yang Liu he always gives me deeper

physics insight. Special thanks also go to all other members of the Stanford TCAD

group: Evelyn Mintarno, Victor Cao, Jae Wook Kim, Patrick Au, and Qiushi Ran.

I have benefited tremendously through interactions with great people in industry. I

am especially appreciated Dr. Jin Cho in Global-foundries, who is my best mentor.

Under his oversight and help, I was able to study random telegraph noise and complete

a critical chapter of this dissertation. Dr. Jin Cho taught me the latest advanced device

physics and shared his experiences in semiconductor industry. I would like to

especially thank Dr. Olof Tornblad (Infineon) for his guidance in transistor linearity

and his continuous encouragement. Because of his guidance I can explore these

interesting research areas--device linearity and distortion. Especially, Dr. Alex Chuang

and David Brown have brought up many interesting research topics and mentored me

to solve noise/sensor problems during the internship in KLA-Tencor. Dr. Alex Chuang

and David Brown are not just good mentors, but they are also like my family. With

their support and care I can continue my Ph.D. study in Stanford. I would like to thank

Dr. Raj Raghuram and David Lee for sharing their ideas and generously providing

invaluable data during my internship in Berkeley Design Automation (BDA). I wish to

express my thanks to Junko Sato-Iwanaga in Panasonic, Meikei Ieong in TSMC, and

Nick Huang in Intel for their supporting and encouragement.

The financial support of Center for Integrated Systems (CIS), Material Structure

Devices (MSD), Advanced Micro Devices (AMD), Global foundries, Semiconductor

Research Cooperation (SRC), and Taiwan government is greatly appreciated.

I was also fortunate to have the sufficient academic collaboration from Prof. Yu

Cao (Arizona State University), Prof. Zhiping Yu (Tsinghua University, China), Eric

Wang (Arizona State University), and Ye Yun (Arizona State University).

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I offer my regards and blessings to my family: my father, Chin-Tao Chen, my mother,

Lee-Ing Tsao, my twin brother, Chia-Hung Chen, and my youngest sister, Chia-Ming

Chen, who supported me in any respect during the completion of the project. I heartily

appreciate my family who has given meaning to all the effort I have done. I would like

to express my deepest gratitude to my mother, Lee-Ing Tsao the woman who was not

only my mother but also one of my best friends and teachers in life. Her unconditional

love and belief in me was my main encouragement in all the achievements I had in life.

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Table of Contents

Abstract ······················································································· v

Acknowledgments ·········································································· vii

Table of Contents ··········································································· xi

List of Tables ················································································ xv

List of Figures ············································································· xvii

Chapter 1 Introduction ···································································· 1

1.1 Motivation ·············································································· 2

1.2 CMOS Scaling ········································································· 4

1.3 Organization ··········································································· 6

Chapter 2 Origin of Low Frequency Noise ············································· 9

2.1 Introduction ············································································ 9

2.2 Number Fluctuation ·································································· 10 2.2.1 Random Telegraph Noise and 1/f Noise ······································· 13 2.2.2 Gate Bias Dependence ··························································· 24 2.2.3 Time Domain Waveform ························································ 30

2.3 Mobility Fluctuation ································································· 31

2.4 Diagnosis ·············································································· 37

2.5 Summary ·············································································· 39

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Chapter 3 Methodology ··································································· 41

3.1 Introduction ··········································································· 41

3.2 Noise Characterization ······························································ 42 3.2.1 Low frequency noise characterization: frequency domain ·················· 43 3.2.2 Low frequency noise characterization: Time domain ························ 50

3.3 TCAD Simulations ··································································· 52 3.3.1 Impedance field method ························································· 52 3.3.2 Low frequency noise simulations ·············································· 54

3.4 Summary ·············································································· 57

Chapter 4 Gate-Dielectrics: Low Frequency Noise in High-κ MOSFETs ······ 59

4.1 Introduction ··········································································· 59

4.2 Low Frequency Noise in High-κ MOSFETs ····································· 61

4.3 Halo Doping ·········································································· 69

4.4 Summary ·············································································· 70

Chapter 5 Channel Material: Low Frequency Noise in SiGe MOSFETs ······· 73

5.1 Introduction ··········································································· 73

5.2 Device Schematic ······································································ 75

5.3 Numerical Low Frequency Noise Model in a SiGe p-HMOS ··················· 79

5.4 Results and Discussions ····························································· 81

5.5 Compact Model ········································································ 93 5.5.1 Equivalent device model ························································ 93 5.5.2 Results and Discussions ························································· 99

5.6 Summary ·············································································· 101

Chapter 6 Size Effect: Low Frequency Noise in Small Area MOSFETs ······· 103

6.1 Introduction ········································································· 103

6.2 Device Schematic ···································································· 105

6.3 Experimental Results ································································ 106

6.4 Simulation Work ····································································· 115

6.5 Statistical Property ··································································· 117

6.6 Summary ·············································································· 120

Chapter 7 Conclusions ···································································· 121

7.1 Summary ············································································ 121

7.2 Suggestions for Future Work ······················································· 122

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Appendix A Low Frequency Noise Simulation Code ····························· 125

Appendix B Compact Model Code for Dual-Channel Behavior ··············· 133

Bibliography ················································································ 147

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List of Tables

Table 5.1: Summary of simulated device parameters .............................................. 76

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List of Figures

Figure 1.1: Low frequency noise is a research topic in many different areas ············ 2

Figure 1.2: Low frequency noise is up-converted and contributes to phase noise in

a VCO ························································································ 3

Figure 1.3: Low frequency noise impacts the noise margin in SRAM cells;

measurement data is extracted from [1] ·················································· 4

Figure 1.4: Historical trend of MOSFET scaling; measurement data is extracted

from [3] ······················································································ 4

Figure 1.5: Schematic of the conventional MOSFET, identifying the various

problems faced in CMOS scaling ························································ 5

Figure 2.1: The origin of low frequency noise is interaction between slow traps in

the gate oxide and the carriers in the channel ·········································· 11

Figure 2.2: Based on number fluctuation model low frequency noise can be

classified as two types: 1) random telegraph noise and 2) 1/f noise ················ 13

Figure 2.3: Random telegraph noise waveform (a) time domain and (b) frequency

domain ······················································································ 14

Figure 2.4: Random telegraph noise power for different values of τupper/ τlower. It

can be clearly seen that the noise power reaches its maximum when the ratio

is 1 ··························································································· 15

Figure 2.5: Both trap depth and energy level determine the tunneling time of

trapping/de-trapping mechanism ························································ 16

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Figure 2.6: a) The sum of Lorentzian causes 1/f noise spectrum and b) measured

1/f noise spectrum ········································································· 17

Figure 2.7: The coordinate system in real space for a MOS transistor ·················· 18

Figure 2.8: The product f(E)(1-f(E)) is sharply peaked around the quasi-Fermi

level ························································································· 20

Figure 2.9: Uniform spatial distribution near the interface causes exponentially

distributed tunneling time ································································ 22

Figure 2.10: Low frequency noise spectrum from a number fluctuation model ········ 23

Figure 2.11: Gate bias dependence of low frequency noise ······························· 25

Figure 2.12: The location of charges in an MOS structure ································ 26

Figure 2.13: Capacitances related to trapping/de-trapping in a MOSFET ·············· 27

Figure 2.14: The evolution of time domain wave of low frequency noise based on

number fluctuation model ································································ 31

Figure 2.15: A schematic for Hooge mobility fluctuation for a homogenous material ··· 32

Figure 2.16: Different mobility mechanisms in a MOSFET ······························ 34

Figure 2.17: Different scattering mechanisms that limit the channel mobility in

MOSFETs ·················································································· 35

Figure 2.18: Hooge mobility fluctuation shows 1/Qn trend in gate bias dependence ···· 36

Figure 2.19: Improved Hooge model includes the impact from parasitics source/

drain resistance. ··········································································· 37

Figure 2.20: Gate bias dependence of Sid/Id2 based on (a) number fluctuation

model and (b) gate bias dependence of Sid/Id2 predicted by Hooge mobility

fluctuation model. ········································································· 38

Figure 2.21: Drain current dependence of Sid/Id2 based on (a) number fluctuation

model and (b) Hooge mobility fluctuation model. ···································· 40

Figure 3.1: A schematic of the methodology used in this thesis. ························· 42

Figure 3.2: A schematic of a low frequency noise measurement bench ················· 43

Figure 3.3: Low frequency noise characterization: an on-wafer noise ·················· 44

Figure 3.4: Low frequency noise characterization: an in-package system ·············· 44

Figure 3.5: Ground loop and DC power supply can significantly impact low

frequency noise measurement results ··················································· 47

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Figure 3.6: Center-shape ground for all equipments in the measurements ·············· 48

Figure 3.7: A circuit board for in-package noise measurements ························· 48

Figure 3.8: Low frequency noise measurement results from the built test bench.

Device Lg=1μm, width=1μm, Vth=0.6V, Vgs=0.45V and Id=8e-8A ················ 50

Figure 3.9: Time-domain low frequency noise measurement bench ····················· 51

Figure 3.10: Random telegraph noise performed by the built test benches ············· 52

Figure 3.11: A schematic of impedance field method ····································· 53

Figure 3.12: a) Schematic plot of an n-type MOSFET and the IFM based physical

model. b) Band diagram along the gate stacks ········································ 54

Figure 4.1: A schematic of the hafnium-based n-type MOS transistor. ················· 60

Figure 4.2: Measured and simulated Id-Vgs curve for a high-κ MOSFET with 1μm

gate length and 1μm gate width ························································· 60

Figure 4.3: Band diagram along high-κ gate stack in an n-type MOSFET. ············· 61

Figure 4.4: Measured and simulated noise power spectrum for high-κ MOSFET

with 1μm gate length. ····································································· 62

Figure 4.5: Low frequency noise comparison between high-κ and SiON gate stack:

in general a high- κ MOSFET shows higher low frequency noise. ················· 62

Figure 4.6: (a) Simulated drain current noise spectrum based on the built TCAD

noise model. Devices with varying gate length of 30, 130, 230, 630, and

1230nm with width 1μm are simulated, respectively. Bias condition is Vd =

0.1V and Vg-Vth = 0.2V. (b) Low frequency noise at 1Hz and thermal noise as

a function of gate length. ································································· 64

Figure 4.7: Reduction of trap density in high-κ material can suppress low

frequency noise in high-κ n-type MOSFETs. ·········································· 65

Figure 4.8: Simulated profiles of distributed drain current noise contributions at

inside the gate oxide using the built TCAD noise model. Two frequencies are

simulated: (a) 1Hz and (b) 10k Hz. The device gate length is 0.18μm.

Vd=50mV and Vg-Vth=0.3V. ····························································· 66

Figure 4.9: Normalized drain current noise as a function of overdrive gate voltage

from simulations using the built TCAD noise model. The device gate length

is 1μm and Vd is 50mV ··································································· 67

xx

Figure 4.10: Measured and simulated normalized drain current noise as a function

of overdrive gate voltage. The simulations are based on the built

numerical TCAD noise model with both the uniform and exponential

trap energy distributions. In this simulation the device gate length

is 0.18μm and Vd is 50mV ····················································· 68

Figure 4.11: Halo doping profiles are used in highly scaled MOS transistors. ········· 69

Figure 4.12: a) Simulated profile of noise contribution at 1Hz for a high-κ n-type

MOSFET with halo doping. (b) Normalized drain current noise as a function

of over drive gate voltage for two devices with and without halo doping

respectively. The device gate length is 0.18μm and Vd is 50mV. ··················· 71

Figure 5.1: Virtual-source velocity as a function of the gate length; data is

extracted from [37, 38]. Red symbols represent strain-engineered devices ······· 74

Figure 5.2: Schematic plots of a SiGe p-HMOS device structure and a band

diagram along the vertical direction ···················································· 75

Figure 5.3: Measured and simulated Id-Vg characteristics for (a) bulk Si0.7Ge0.3

p-HMOS, (b) control Si bulk pMOS, (c) PD Si0.7Ge0.3 p-HMOS, (d) PD

control Si pMOS. ········································································ 77

Figure 5.4: Simulated SiGe p-HMOS carrier density for both surface and buried

channel as a function of gate voltage. ·················································· 78

Figure 5.5: Parasitic surface channel and SiGe buried channel show different low

frequency noise performance. ··························································· 80

Figure 5.6: Measured and simulated normalized drain current noise Sid/Id2 at 10

Hz as a function of the gate voltage for (a) Si pMOS and (b) SiGe p-HMOS. ···· 83

Figure 5.7: Measured and simulated drain current noise Sid at 10 Hz as a function

of the gate bias for SiGe p-HMOS. The gray dotted line neglects the layer

dependent contribution of the correlated mobility fluctuation, whereas, in this

work, different fitting mobility scattering parameters are used in the Si cap

layer and in the SiGe channel, and Hooge mobility fluctuations are accounted ·· 84

Figure 5.8: Measured and simulated normalized drain noise, Sid/Id2 at 10Hz (right

y-axis), together with (gm/Id)2 (left y-axis), as functions of the drain current.

Data for both (a) Si pMOS and (b) SiGe p-HMOS are shown ······················ 85

xxi

Figure 5.9: Measured and simulated drain current noise spectra for (a) Si pMOS

and (b) SiGe p-HMOS. The frequency range is 10 Hz to 1 kHz. Four body

biases are used ranging from 0.2 to −0.4 V ············································ 87

Figure 5.10: Hole density in the Si cap layer and carrier density in the SiGe

channel as functions of the body bias. The small plot is from TCAD

simulations of the band diagrams along the vertical direction for two body

bias conditions (Vb = 0.2 V and Vb = −0.4 V) ········································· 88

Figure 5.11: Drain current noise, Sid (left y-axis) at 100 Hz, together with hole

density in Si cap layer (right y-axis), as functions of body bias ····················· 89

Figure 5.12: Simulation data for the drain current noise Sid as a function of the

overdrive voltage at a frequency of 100 Hz ············································ 90

Figure 5.13: Carrier density for both surface and buried channels as a function of

the overdrive voltage in two different body biases, −0.4 and 0.2 V ················ 91

Figure 5.14: (a) Improved Hooge model without number fluctuation. (b) Improved

Hooge model with the contribution of number fluctuation ·························· 92

Figure 5.15: The proposed model for screening behavior: under low Vg the

dual-channel behavior is like two uncorrelated MOS. When Vg is larger than

Vth_buried surface channel behavior can be modeled as a thin body device. If Vg

is larger than Vth_surface, buried channel charges are saturated.······················· 94

Figure 5.16: Equivalent capacitance model (a) before and (b) after buried channel

turns on ····················································································· 96

Figure 5.17: Schematic plot of a SiGe HMOS and a band diagram along vertical

direction ···················································································· 98

Figure 5.18: Hole density in dual channels versus Vg: different subthreshold

slopes indicates different EOT for two channels and the flat part in strong

inversion for Qburied explains the screening effect from Qsurface (Parameters are

from set I in Table 5.1) ································································· 100

Figure 5.19: Low frequency noise behavior at various gate biases in a SiGe

p-HMOS. ················································································· 100

Figure 6.1: Random telegraph noise results performed by the built test benches ···· 104

Figure 6.2: Compared to SiON, high-κ material shows different band structure

xxii

and tunneling characteristics, which complicates the random telegraph noise

mechanism ··············································································· 105

Figure 6.3: Device area is aggressively scaled down to save cost and improve

performance ·············································································· 106

Figure 6.4: Current-Voltage characteristics of a high-κ n-type MOSFET (W/L=

450nm/30nm) before (solid line) and after stress. Stresses are conducted with

positive stress (1.8V, dashed line) and followed by negative stress (-1.8V,

triangle). Notice that large Vth shift and increased Ig occur after positive stress.

Both Vth shift and high gate current recover during negative stress ·············· 107

Figure 6.5: Measured electron mobility values at Ninv=3x1012cm-2 as a function of

interfacial oxide thickness. The mobility values are corrected for ionized

impurity Coulomb scattering. Thicker interfacial layer can reduce the

Coulomb scattering between traps inside high-κ stack and channel carriers ···· 108

Figure 6.6: Gate current noise with respect to gate bias. Clean random telegraph

noise signature is observed from Vg=0.8V to Vg=1.0V (W/L = 70nm/40nm) ·· 109

Figure 6.7: The ratio of average time spent in the upper gate current state to

average time spent in the lower Ig state ratio with respect to gate bias for

high-κ n-type MOSFETs (W/L = 70nm/40nm) ····································· 110

Figure 6.8: Definition of trapped time and de-trapped time (a): t+ means the

system is in the upper state and a charge is trapped in the trap (trapped state).

On the other hand t- means that the system is in the lower state and a charge is

de-trapped (de-trapped state). This definition is consistent with our PBTI and

Id-RTN results in high-κ n-type MOSFETs. The schematic illustration of

electron trap during the RTN (b): demonstrates that a higher gate bias

narrows the energy gap between quasi-Fermi level (Ef) and trap level (Et),

resulting in higher probability of capturing electron into the existing traps ····· 111

Figure 6.9: Drain and gate current noise signal. Notice that the drain and gate

currents track each other. Electron trapping increases Ig and decreases Id.

Electron de-trapping recovers both Ig and Id (W/L = 70nm/40nm) ··············· 112

Figure 6.10: Id-RTN and Ig-RTN measured in different gate bias conditions (W/L

=70nm/40nm). A high correlation between Id- and Ig-RTN is observed in (b)

xxiii

and in (c); no correlation in (a) and in (d) ············································ 113

Figure 6.11: Gate bias dependence of Id-RTN and corresponding noise spectra

extracted from Fourier transform of time domain signals (W/L = 70nm/40nm).

····························································································· 114

Figure 6.12: Sid/Id2 is not proportional to (gm/Id)

2, which suggests that the main

mechanism for 1/f noise in small area devices is Hooge mobility fluctuation ·· 115

Figure 6.13: The single trap location in the simulation in real space (a) and in

energy (b) ················································································· 116

Figure 6.14: Schematic of the Hooge mobility fluctuation originating from bulk

phonon scattering ········································································ 116

Figure 6.15: Noise simulation results in different gate bias conditions. The low

frequency noise mechanism changes between the Hooge mobility fluctuation

(1/f) and RTN (Lorentzian spectrum) depending on the gm value

(W/L=70nm/40nm) ···································································· 117

Figure 6.16: Drain and gate current noise signal. Notice that the drain and gate

currents track each other. Electron trapping (capture) increases Ig and

decreases Id. Electron de-trapping (emission) recovers both Ig and Id (W/L =

70nm/40nm)·············································································· 118

Figure 6.17: The trap occupancy fluctuations happen inside the space charge

region of the MOSFETs can possibly cause Id-RTN without Ig-RTN. ··········· 119

Figure 6.18: About twelve percent (12%) of MOSFETs (W/L=70nm/40nm) show

RTN: 9% Ig-RTN, 2% Id-RTN, and 1% Ig-/Id-RTN. The statistical results are

from one thousand devices with the same technology and structures. ··········· 120

Figure B.1 Charge distribution in dual-channel as a function of gate bias ············ 146

CHAPTER 2. INTRODUCTION 1

1

Chapter 1

Introduction

Spontaneous fluctuations in current, voltage, and temperature in a system are referred

to "noise" which ultimately limits a system’s performance and becomes a fundamental

issue in electrical engineering. The noise frequency spectrum is, in general, constant at

high frequencies (white noise and shot noise). In this regime the physical mechanisms

are well known and noise levels can usually be accurately predicted. However at low

frequency, noise is usually found to be proportional to 1/f and currently many

inconsistencies still exist among the experimental results from different workers and

between theory and experiment.

In the past fifty years, low frequency (LF) noise in electronic systems has turned

out to become a high impact research interest for many disciplines such as electrical

engineering, physics, and mathematics; nerveless the mechanisms have not been

clearly identified and understood as shown in Figure 1.1.

2 CHAPTER 1. INTRODUCTION

To physicists, the low frequency noise in an electronic system represents a

practical phenomena described by statistical mechanics; an understanding of the practical

consequences helps to illuminate and clarify some concepts of the physical theory. To

the mathematicians, low frequency noise is based on the framework of random process

theory; general formulas for 1/f noise; stationary and non-stationary process have

become the focus of their research. To the electrical engineers, noise is a constraint of

real systems, but a better understanding of its origins helps the engineer to reduce its

effects by optimized integrated circuit design. Since the origin of the low frequency

noise still raises many questions, this thesis deals with low-frequency from an

electrical engineering viewpoint.

1.1 Motivation

Before getting into the main topic, motivation to study low frequency noise is now

given. Low frequency noise is one of the key issues in analog applications, especially

in radio-frequency (RF) integrated circuits such as phase noise in voltage control

Figure 1.1: Low frequency noise is a research topic in many different areas.


oscillators (Figure 1.2). In a VCO, low frequency noise is up-converted to phase noise

at small frequency offsets from the carrier frequency and therefore sets the ultimate

separation limit of two channels.

In addition to analog applications there has been a growing concern with regard to

low frequency noise in digital applications. It has been reported that a special kind of

low frequency noise, random telegraph noise (RTN), increases with scaling and causes

threshold voltage variation (ΔVth), which impacts SRAM noise margin as shown in

Figure 1.3 [1]. Moreover, it is predicted that at the 15nm technology node random

telegraph noise will become the major source of device variability [2].

Low frequency noise is very sensitive to traps and defects in the device and is

strongly related to physical processes such as the trapping and release phenomena.

Thus, low-frequency noise can be an important diagnostic tool to estimate the quality

and reliability of gate oxide dielectrics.

Figure 1.2: Low frequency noise is up-converted and contributes to phase noise in a VCO.

f

LF

Si

up‐convert LF

noise

Io

f

carrier frequency

Io

f

phase noise

f


Figure 1.3: Low frequency noise impacts the noise margin in SRAM cells; measurement data is extracted from [1].

1.2 CMOS scaling

Historically, scaling of planar bulk silicon (Si) metal-oxide-silicon field-effect

transistors (MOSFETs) had been incredibly successful; device performance is

enhanced roughly 17% per year over several decades as shown in Figure 1.4. [3]. The

number of devices on a chip is almost quadrupled every three years.

Figure 1.4: Historical trend of MOSFET scaling; measurement data is extracted from [3].

-0.2 -0.1 0.0 0.1 0.2-0.2

-0.1

0.0

0.1

0.2

Pu

ll u

p p

-MO

SF

ET

s d

elt

a-V

th (

V)

Pull-down n-MOSFET delta-Vth (V)

With RTN W/O RTN

Vth window

Noise margin is reduced

Pull‐down nMOS

Pull‐up pMOS

1985 1990 1995 2000 20050.1

1

IEDM benchmark technologies

No

rmal

ized

per

form

ance

Year

Historical trend~17% enhancement/year


According to the requirements of ITRS 2009 (International Technology Roadmap

for Semiconductors) [4], every device parameter has to be shrunk continuously with

almost the same rate to maintain the continuous progress of semiconductor industry.

However, it is anticipated that shrinking the parameters beyond the sub-50 nm

dimension faces severe difficulties due to various kinds of limitations. The limits most

often cited are 1) quantum-mechanical tunneling of carriers through the thin gate oxide;

2) quantum-mechanical tunneling of carriers from source to drain, and from drain to

the body of the MOSFET; and 3) not enough low field mobility in Si channel material.

These and other issues in transistor scaling are shown schematically in Figure 1.5.

Innovation of methods to circumvent the many barriers in conventional MOSFET

scaling is required to achieve progress. Various options have been studied to improve

device scaling and achieve better performance including high-κ gate oxide [5], high

mobility channel material [6], and better electrostatics [7].

Figure 1.5: Schematic of the conventional MOSFET, identifying the various problems faced in scaling.


However new device designs and altering material properties can directly impact

low frequency noise significantly. Moreover, the downscaling of the device dimensions

also entails a downscaling of the voltage levels, which lowers the signal-to-noise ratio.

With these changes, the low-frequency noise performance for future CMOS

technology needs to be carefully evaluated; such factors as size (channel length/width)

scaling, adoption of advanced doping profiles (pocket implantation), alternative gate

oxide (high-κ) and channel materials (SiGe) all need to be considered.

The main topic of this thesis is to investigate the low-frequency noise properties

of advanced CMOS devices that may reside in future analog and digital applications

and to improve the understanding of the physical mechanisms of low-frequency noise.

This work can serve as a guideline for device engineers to design low noise transistors

or as a roadmap to inform IC designers how to optimize system noise performance.

1.3 Organization

The introduction has provided motivation to study low frequency noise. The

remainder of the dissertation is organized as follows.

Chapter 2 and Chapter 3 provide the background of this dissertation. Chapter 2

reviews low frequency noise mechanisms in a MOSFET for better understanding.

There are three parts in this chapter: 1) Number fluctuation model (ΔN model), 2)

Hooge mobility fluctuation model (Δμ model), and 3) noise mechanism diagnosis. The

ΔN model starts from random telegraph noise and discusses the origin of 1/f noise

spectrum. The Δμ model is reviewed based on the current understanding of this

empirical model. Different noise models show different bias dependence; in the final

section the bias dependence is used to diagnosis the main noise mechanism in the

MOSFETs.

Chapter 3 introduces the primary methodologies used in this thesis, which include

TCAD noise simulations and device noise characterization. In TCAD simulations, the


Impedance Field Method and physical trapping/de-trapping noise sources will be

introduced. In the noise characterization section, the test benches for frequency and

time domain measurement are provided, and detailed settings are discussed.

From Chapter 4 to Chapter 6 the impact of transistor scaling engineering in low

frequency noise is discussed including gate dielectric, channel material, and size

effects. In Chapter 4, the low frequency noise in MOSFETs with high-κ gate stacks

(SiON/HfO2) and scaling trends are investigated, through TCAD simulations and

careful measurement. The degradation of low frequency noise performance due to Halo

doping is also studied.

Chapter 5 deals with low frequency noise in high mobility channel MOSFETs,

Si/SiGe/Si hetero-FETs, which is one promising approach for future scaling; it is also

very useful for RF/analog applications. In this chapter device-level simulation

capabilities have been developed to investigate low-frequency noise behavior in p-type

SiGe heterostructure MOS (SiGe p-HMOS) transistors. Through the comparisons

between the developed noise model and measurements, details of the low frequency

noise mechanisms in SiGe p-HMOS are discussed.

In Chapter 6, low frequency noise in small gate area MOSFETs is studied. For

small devices, the number of mobile charge carriers is reduced to the point that

behavior of individual charge carriers becomes visible and significant. In this chapter a

comprehensive view for low frequency noise in small gate area MOSFETs is presented

based on measurement results and TCAD simulations.

Finally, Chapter 7 summarizes the contributions of this dissertation and discusses

recommended research for present and future generations of low frequency noise

research.

CHAPTER 2. THE ORIGIN OF LOW FREQUENCY NOISE 9

9

Chapter 2

The Origin of Low Frequency Noise

In this chapter the origin of low frequency noise is discussed. Two low frequency noise

models are summarized and included: the number fluctuation model (ΔN model) and

Hooge empirical mobility fluctuation model (Δμ model). In this thesis we will use

these two models as the basis to understand the details of low frequency noise

mechanism in advanced CMOS technology.

2.1 Introduction

Unlike thermal or shot noise, low frequency noise is defined in terms of the nature of

frequency domain noise power spectra (such as 1/f noise) or time-domain wave forms

(such as random telegraph noise), without reference to a specific physical mechanism.

It is, to a certain extent, a reflection of our understanding about low frequency noise.

Even though several mechanisms of low frequency noise have been proposed, no

conclusive theory has appeared so far. Among these models, McWhorter's number

fluctuation model [8] and the Hooge mobility fluctuation model [9] were among the

most popular ones. In this chapter these two models are reviewed to provide the

background of this thesis.

10 CHAPTER 2. THE ORIGIN OF LOW FREQUENCY NOISE

The origin of electronic device noise is based on conductivity fluctuations; the

conductivity can be expressed as

N (2-1-1)

where N is the number of carriers and μ is carrier mobility. From Eq. (2-1-1) it is clear

that there are essentially two physical mechanisms behind any fluctuations in the

conductivity: fluctuations in the number of carriers or variation in the mobility. Thus,

there are two schools of thought regarding the origin of low frequency noise: number

fluctuation (ΔN) and mobility fluctuation (Δu). McWhorter's model is mainly based on

carrier number fluctuations. On the other hand, Hooge model is based on mobility

fluctuations.

In the following sections the origins of low frequency noise are discussed. In

Section 2.1 the ΔN model is presented and in Section 2.2 the focus shifts to the Δu

model. The diagnosis for ΔN and Δu model is provided in Section 2.3; a brief

summary will be provided in Section 2.4.

2.2 Number Fluctuation

In 1957 McWhorter [8] proposed a sophisticated model in which low frequency noise

was attributed to channel carrier number fluctuations. Currently McWhorter's model

has remained the most acceptable representation for low frequency noise in MOSFETs.

In this model, McWhorter considered the carrier number fluctuations to result from

trapping of charge carriers in traps located at a distance from the semiconductor–oxide

interface as the noise source; namely, the low frequency noise is a surface related

effect.

The physical mechanism behind this model is the interaction between slow traps

in the gate oxide and the carriers in the channel, which is schematically illustrated in

Figure 2.1. The oxide traps dynamically exchange carriers with the channel, causing


fluctuations in the surface potential, in turn giving rise to fluctuations in the inversion

charge density as shown in Eq. (2-2-1).

/fb oxV N C (2-2-1)

where Vfb is the flat band voltage, Cox is oxide capacitance, ΔNt is oxide trap

fluctuation, and ΔN is channel carrier fluctuation. This in turn leads to noise in the

drain current.

d dd t fb

t fb

I INI N V

N N V

(2-2-2)

Although McWhorter's model can explain n-type MOSFETs well, it cannot

predict experimental results of low frequency noise in p-type MOSFETs. Ideally, a

single model, based on physical principles, should describe the low frequency noise in

both n-type and p-type MOSFETs. In 1990, Hung el. [10], [11] modified McWhorter's

model; they proposed a "unified model", which combines carrier number fluctuations

and correlated mobility fluctuations. Beside the carrier number fluctuations,

fluctuations in the occupancy of the oxide traps induces "correlated" fluctuations in the

surface mobility through Columbic scattering [11], which can be expressed as

Figure 2.1: The origin of low frequency noise is interaction between slow traps in the gate oxide and the carriers in the channel.


effdt

eff t

IN

N

(2-2-3)

where μeff is effective mobility. When considering both number fluctuations and

correlated mobility fluctuations the total drain current fluctuations can be expressed as

eff effd d d dd t fb t

t eff t fb eff t

I I I INI N V N

N N N V N

(2-2-4)

This equation can be further simplified as

( )d m fb d eff ox fbI g V I C V (2-2-5)

This equation is for n-MOSFETs; for p-MOSFETs “+gm” should be used, instead

of “-gm”. Here we define a scattering parameter “α” that reflects how variations in the

oxide charge couple to the mobility term.

2

1 eff

eff tN

(2-2-6)

This equation is for n-type MOSFETs; for p-type MOSFETs "-α" should be used.

The power spectrum density of drain current can be expressed as

2

21fb

eff ox did V m

m

C IS S g

g

(2-2-7)

The first term in parentheses in Eq. (2-2-7) is due to fluctuating number of

inversion carriers and the second term corresponds to mobility fluctuations that are

correlated to the number fluctuations. Note that α can be negative or positive

depending on whether the mobility increases or decreases upon trapping of charge.

This correlated mobility fluctuation term was later critically reviewed in [12],

where an improvement was suggested to consider the dependence on the inversion

carrier density in the modeling of screening effects.


2

2

0

1fb

invid V m

C

NS S g

(2-2-8)

where Ninv is the 2-D inversion carrier density, and uc0 is a mobility fitting parameter,

which depends on the interface properties and the material of the gate oxide. Such a

modified version of the unified model is used in this thesis.

2.2.1 Random Telegraph Noise and 1/f Noise

Based on the number of active traps, number fluctuations can be classified as two types

as shown in Figure 2.2. In the first type, there are only a few traps involved, the current

can switch between two or more states resembling a random telegraph signal (RTS)

waveform, which causes “Random telegraph noise (RTN)”. The second type includes

multiple traps, which causes 1/f noise that exhibits a triangle-like time-domain

waveform.

Figure 2.2: Based on number fluctuation model low frequency noise can be classified as two types: 1) random telegraph noise and 2) 1/f noise.

In the following, we will discuss random telegraph noise and 1/f noise respectively.

time

Id

freq

Sid

time

freq

Sid

Id


(a) Random telegraph noise:

Physically, RTN is caused by the capture and emission of a mobile charge carrier

in a so-called trap -- a localized energy state somewhere in the band gap.

In the time domain, the RTN is characterized by three parameters: the amplitude,

ΔI, the mean ‘high’ time τupper and the mean ‘low’ time τlower as shown in Figure 2.3 (a).

Figure 2.3: Random telegraph noise waveform (a) time domain and (b) frequency domain.

In the frequency domain the power spectral density (PSD) of RTN is given in

Figure 2.3 (b). The spectrum can be expressed as

0

2

2 20

2

20

1 1

1 12

1 11

upper

lower

RTSupper lower

RTSRTS

RTS

S I

2 /A Hz (2-2-9)

τlow

τup

ΔId

1 10 100 1000 10000 100000

1E-19

1E-18

1E-17

1E-16

1E-15

1E-14

1E-13

Corner frequency

Sid

(A

2 /H

z)

Frequency (Hz)

RTNLorentzian spectrum

1/f2

0 5 10

3.0x10-6

3.2x10-6

3.4x10-6

3.6x10-6

3.8x10-6

Dra

in c

urr

ent

(A)

Time (s)


where β is a symmetry factor for the trap and ω0RT is the corner frequency of the Lorentzian. τupper denotes the average time spent in the upper state and τlower represents the average time spent in the lower state. From Eq. 2-2-9 the noise power of the RTN is inversely proportional to ω0RTS and the RTN spectrum can be also defined: flat at low frequencies and decaying with 1/ω2 above ω0RTS.

Note that the spectrum of the RTS is symmetrical with respect to τ1 and τ0; only

the DC term is sensitive to the difference. The power of the PSD depends on the

‘asymmetry factor’ β. This is shown in Figure 2.4. If β = 1; i.e. τ0 =τ1, the PSD of the

RTS will be at a maximum.

The tunneling time constants are obtained using the Wentzel–Kramer–Brillouin

(WKB) approximation as follows [13]. For the forward tunneling process (dwell time

in the upper level) from channel to traps, it is given by Eq. (2-2-10).

*

3/2 3/20 0 * *0

4 2exp

3ox ox

upper c t c t

m mE E qEx E E

qE

(2-2-10)

Figure 2.4: Random telegraph noise power for different values of τupper/ τlower. It can be clearly seen that the noise power reaches its maximum when the ratio is 1.

‐10‐4 10‐2 100 10

2 104

‐

‐

‐

‐

‐90

‐80

‐70

‐60

‐50


where m0 is the tunneling effective mass, m0* the free-electron mass, E the electric

field, Eoxc the oxide conduction band edge, x the depth of the trap into the oxide, Et

* the

empty defect level, Et the occupied defect level, and τ0 a characteristic tunneling time

that has only a weak dependence on x and E. A similar expression for the backward

tunneling constant τlower is obtained with Et* replaced by Et.

It should be noted that the tunneling time depends on both the defect level and the

depth of the trap into the oxide as shown in Figure 2.5.

(b) 1/f noise:

When a device contains a large number of traps, several trapping/de-trapping

fluctuations happen over a wide range of tunneling times as shown in Figure 2.6 (a).

The ΔN model explains the origin of the 1/f spectrum by assuming that it is a

summation of a large number of uncorrelated Lorentzian spectra, each caused by

separate tunneling time constants. A 1/f noise spectrum is usually measured as shown

in Figure 2.6 (b).

Figure 2.5: Both trap depth and energy level determine the tunneling time of trapping/de-trapping mechanism.

Trap depth changes

tunneling time

Trap energy level

changes tunneling time


Figure 2.6: (a) The sum of Lorentzians causes 1/f noise spectrum. (b) Typical measured 1/f noise spectrum.

10-2 10-1 100 101 102 103 104 105

1E-18

1E-16

1E-14

1/f

Sid

(A

2/H

z)

Frequency (Hz)

TCAD simulation results for Lonertzian spctrums

104 105

1E-20

1E-19

n-MOSFETLg=1um 3.15MHz

1/f

Corner frequency

Sid

(A

2 /Hz)

Frequency (Hz)

Measured 1/f noise spectrum

(a)

(b)

TCAD simulations for Lorentzian spectra


A 1/f noise form is shown in Figure 2.6 (b) and it is characterized by a power

spectral density function:

id

CS

f (2-2-11)

where C is a constant. The integrated power in the spectrum between f1 and f2 is given

by

2

1

2

1

lnf

id idf

fCP S df

f f

(2-2-12)

This result shows that for a fixed frequency ratio f2/f1, the integrated noise power

is constant. Thus, the total noise power between any decades of frequency, says 0.1 Hz

to 1 Hz or 1 Hz to 10 Hz or 10 Hz to 100 Hz, is identical. This property of 1/f noise is

known as "scale invariance".

Figure 2.7 defines the coordinate system in real space. Note that the location of

oxide traps is described by four coordinates x, y, z, and E.

Figure 2.7: The coordinate system in real space for a MOS transistor.

Z X

Y

Oxide

Si substrate


Mathematically, the noise spectrum due to a trap center nT at energy E in a unit

volume ΔxΔyΔz is given by Eq. (2-2-13).

2 24 1

1tN T t tS n E E x y zf f

(2-2-13)

where ft = 1+exp[(E-EF)/kBT]-1 is the trapping probability. The probability of an

electron penetrating into the oxide decreases exponentially with the distance from the

interface so the relaxation time constant or the trapping process for a trap located at a

distance z from the silicon-oxide interface is

0 expE z (2-2-14)

It should be noted that the assumption behind Eq. (2-2-14) is that inelastic

tunneling (that is, tunneling between different energy levels) is regarded as unlikely

[14]. This assumption is discussed in [15][16] and several trapping models are

proposed such as the lattice-relaxation multi-phonon emission (LRME) process model

[17] and switching oxide traps model [18]. However the mismatch between the

trapping models and experimental results has repeatedly been demonstrated and

prompted various authors to introduce empirical corrections [17].

For the Si/SiO2 system, trap locations at z = 2.6 nm and at 0.7 nm for frequencies

of 0.01 Hz and 1 MHz, respectively seem appropriate. Thus, oxide traps located too

close to the channel interface are too fast to give 1/f noise, and those located more than

~3 nm from the interface are too slow to contribute.

The carrier number fluctuation model should include the contributions from all

traps in the gate oxide and the following integral should be provided.

2

20 0 04 1

1 2

t t

C ox

V

N N

E W L t

tE

S S dxdydzdE

qN f E f E dxdydzdE

WL f

(2-2-15)


where SNt is noise power spectral density oxide trapping fluctuation. The trap

distribution has four dimensions: three real space dimensions and one energy

dimension. Thus, the integral includes the four dimensions to cover all traps in the

oxide. This integral is the key for number fluctuation model.

In the energy dimension the probability of trap/de-trap is given by the

Fermi-Dirac distribution function f (E).

,

1

1 fn pE E kTf E

e

(2-2-16)

The product f(E)(1-f(E)) is sharply peaked around the quasi-Fermi level Efn,p as

shown in Figure 2.8.

Only when traps are around the quasi-Fermi level Efn,p (within a few kT) can the

traps contribute to the 1/f noise. When the energy of traps is much higher than the

quasi-Fermi level (> a few kT) the traps are permanently empty. On the other hand,

when the energy of traps is much lower than quasi-Fermi level (< a few kT) the traps

0.0 0.2 0.4 0.60.0

0.5

1.0

1-f(E)f(E)

Pro

bab

ility

of

trap

pin

g/d

etr

app

ing

Energy level (eV)

Ef

Figure 2.8: The product f(E)(1-f(E)) is sharply peaked around the quasi-Fermi level.


are permanently filled. The product f(E)(1-f(E)) in Eq. (2-2-15) behaves like a delta

function around the quasi-Fermi level.

2

0 0 0

4 11 2

C ox

t

V

E tW L

N t

E

S N f E f E dxdydzdEf

20 0 0

41 2

oxW L t

t fkTN E dxdydzf

(2-2-17)

A reasonable assumption is that the trap distribution in the width direction is

uniform and given by the following expression.

20 0 04

1 2

ox

t

W L t

N tS kTN dxdydzf

20 0

41 2

oxL t

tkTW N dydzf

(2-2-18)

where Nt is the density of traps in the gate dielectrics at the quasi-Fermi level (in

cm-3eV-1) as these traps are the only ones that contribute to the low frequency noise.

At very low drain voltages and gate bias above threshold voltage (linear regime),

the carrier density is uniform along the channel and Eq. (2-2-19) becomes

2 20 0 0

4 41 2 1 2

ox ox

t

L t t

N t F t FS WLkT N E dydz WLkT N E dzf f

(2-2-19)

To demonstrate a 1/f spectrum the oxide traps are assumed to have a uniform

spatial distribution (in z axis) near the interface. Through Eq. (2-2-19), uniform spatial

distribution near the interface causes exponentially distributed tunneling time as shown

in Figure 2.9.


The noise spectrum can be approximated by

20

41 2

ox

t

tt

N t F

kTN WLS WLkT N E dz

ff

(2-2-20)

for 1 2

1 1

In general, the noise spectrum can be approximated as:

constant for 1

1f

1tNS f for

1 2

1 1

(2-2-21)

21 f for 2

1f

τ= τ0ekz

uniform distribution of traps

Figure 2.9: Uniform spatial distribution near the interface causes exponentially distributed tunneling time.

Z2 Z1

τ1

τ2

exponential

distribution of τ


In Eq. (2-2-21), τ1 and τ2 are the time constants governed by the smallest and

largest distances of tunneling, respectively. At extremely low frequencies, the noise

level is equal to a constant and no longer depends on the frequency as shown in Figure

2.10.

Figure 2.10: Low frequency noise spectrum based on the number fluctuation model.

It should be noted that the frequency exponent "γ" deviates from 1 if the trap

density is not uniform in depth. For a trap distribution that is skewed toward the

interface, there are a greater number of high-frequency traps. In this case γ < 1 is

expected. For the opposite case, for a trap distribution that is skewed away from the

interface, there are a greater number of low-frequency traps leading to γ > 1.

Through capacitances, the carrier number fluctuations translate into a flat band

fluctuation.

fb tV NS S (2-2-22)

10-3 10-2 10-1 100 101 102 103 104 105

1E-18

1E-16

1E-14

flat

shortest relaxation time

longest relaxation time 1/f2

1/f

Sid

(A

2 /Hz)

Frequency (Hz)

TCAD simulations nMOSFETs Lg=1um


The drain current noise can be calculated as follows.

2 2

2 2

0 0

1 1fb t

inv invid v m N m

c c

N NS S g S g

(2-2-23)

Thus

2 22 2

20 0

1 1fb t

inv invid m mv N

d d c d c

N NS g gS S

I I I

(2-2-24)

From Eq. (2-2-24) we can see that Sid/Id2 (gm/Id)

2 which means that in the ΔN

model, low frequency noise power is proportional to the circuit metric (gm/Id). To

improve both (gm/Id) and noise performance it is necessary to reduce carrier number

fluctuations.

2.2.2 Gate Bias Dependence

In the previous section we performed the ΔN model derivation in the triode regime.

In this section, we shall generalize the results presented in Section 2.2.1; they will be

generalized and a simple theory is outlined that covers drain current noise from weak

to strong inversion.

Following G. Reimbold's theory in 1984 [8], the gate bias dependence of drain

current noise is shown in Figure 2.11. The gate bias dependence in Figure 2.11 can be

briefly described as follows. In the strong-inversion regime the screening of the

trapped charge is provided by the inversion-layer electrons. It is therefore expected that

electron capture reduces the total number of free carriers in the inversion layer, Ninv.tot,

and hence

1d

d inv

I

I N

(2-2-25)


As the gate voltage is reduced to threshold and below, the screening of the trapped

charge is principally achieved by the depletion region and the gate bias dependence of

drain current noise becomes constant.

Figure 2.11: Gate bias dependence of low frequency noise based on the G. Reimbold theory.

Mathematically, the ratio of the fluctuations in carrier numbers to fluctuations in

occupied trap numbers is used; R describes the gate bias dependence of drain current

noise.

t

NR

N

(2-2-26)

where ΔN=NWΔx, ΔNt=NtWΔx. N and Nt are the number of channel carriers and the

number of occupied traps per unit area.

Figure 2.12 depicts the location of charge in the MOS structure. QG, Qit, Qo, Qn

and Qt are defined to be the charge density (per unit area) associated with the gate,

interface traps, the depletion region, inversion-layer and the oxide traps, respectively.

0.0 0.5 1.0 1.5

1E-11

1E-10

1E-9

1E-8 Plateau

Sid

/I d2

(1/

Hz)

Gate Voltage (V)

TCAD simulations G. Reimbold theorynMOSFET (W/L=10um/1um)

1/Qn2


When the trapped charge Qt fluctuates at a fixed gate bias, the charge conservation in

the structure is such that

0G it D n tQ Q Q Q Q (2-2-27)

Figure 2.12: The location of charge in an MOS structure.

These charge fluctuations are related to the surface potential fluctuation through

the following equations.

G ox s

it it s

D D s

n n s

Q C

Q C

Q C

Q C

(2-2-28)

Cox, Cit, CD and Cn are the capacitances (per unit area) associated with the oxide,

interface traps, depletion region and channel respectively as shown in Figure 2.13.

+ + + + + + + +

z

y

x x x x xx x

Si

Oxide

Depletion region

Inv. layer

Vg>0

Vsub

QtQit

QG

Qn

QD


Figure 2.13: Capacitances related to charge trapping/de-trapping in an n-type MOSFET.

Eq. (2-2-27) and Eq. (2-2-28) allow us to write

t G it nD

s s s s s

ox it D n

Q Q Q QQ

C C C C

(2-2-29)

Thus we can obtain

/

/n n s

t t t s

n

ox it D n

Q QNR

N Q Q

C

C C C C

(2-2-30)

It should be noted that only the channel charge Qn depends on surface potential.

0 0exp expsn s

nn

s

qQ Q Q

kT

QQ

(2-2-31)

xx ∆φsurface

∆QG ∆Qit

∆Qn

∆QD

Cox

CD

Cn

Cit

n+ n+

p

inversion layer


Therefore

2 2

1 1 1 n nn n

s s s s

Q QkT kTN Q C

q q q q

(2-2-32)

Other charges do not depend on surface potential and we can define

*2 ox it D

kTN C C C

q

(2-2-33)

The value of N depends on thermal equilibrium status and the typical values in the

range 1~5x1010 cm-2. 'R' can be written in a more concise form as

*

NR

N N

(2-2-34)

To generalize the results in Section 2.2.1 a small area WΔx in the MOSFET is

considered. Eq. 2-2-4 can be normalized as

1 1 effd

td t eff t

I NN

I N N N

(2-2-35)

where ΔN=NW Δx, ΔNt=NtW Δx, and N and Nt are the number of channel carriers and

occupied traps per unit area.

The ratio of the fluctuations in carrier number to fluctuations in occupied traps is

R=δΔN/ δΔNt. Through simple calculations we obtain

1 effd t t

t effd eff t

I N NR RN

I N W x N N W x

(2-2-36)

Thus, the power spectral density of local current fluctuation is

2 2

d t

dI eff N

I RS S

W x N

(2-2-37)


where SΔNt is the power spectral density of mean-square fluctuations in the number of

occupied traps over the area WΔx. From Section 2.2.1 we get

tN t

kTS N W x

f (2-2-38)

The total drain current noise power turns out to be

2

2

22

2 20 0

( )

1 1

d t

d d

dI eff N

L Ld

I I t f eff

I RS S

W X N x

kTI RS S xdx N E dx

L L fW N x

(2-2-39)

Eq. (2-2-39) is a general relation for any bias conditions. At low drain bias,

condition Eq. (2-2-39) can be simplified as

22

d

dI t t eff

kTI RS N E

fWL N x

(2-2-40)

To obtain the essential relation we ignore the correlated mobility term here.

22

2d

t fdI t f

ox D it n

N EkTI R KS N E

fWL N x f C C C Q

(2-2-41)

with

2

dkTIK

WL (2-2-42)

As weak inversion is approached, |βQn| << Cox+CD+Cit corresponds to charge

sharing among the gate, inversion and depletion layers.


22

( )t fid

d ox D it

N ES K

I f C C C

(2-2-43)

For a given frequency, since CD slowly varies with the biases, Sid/Id2 appears to be

a constant as long as Cit and Nt variations versus biases remain small.

For strong inversion, |βQn| >> Cox+CD+Cit , Eq. (2-42) becomes

2 2 2

( )t fid

d n

N ES K

I f Q (2-2-44)

Sid/Id2 strongly depends on gate bias through 1/Qn

2.

For the intermediate case of moderate inversion, a numerical calculation is

necessary to obtain a precise formulation.

Based on G. Reimbold's theory, a plateau is observed in the variations of Sid/Id2

versus the gate voltage in weak inversion followed by a steep decrease in strong

inversion, which becomes an important characteristic in ΔN model.

2.2.3 Time Domain Waveform

Based on number fluctuation model 1/f noise is the summation of several component

of random telegraph noise; the evolution of time domain wave form can be visualized

as shown in Figure 2.14.


Figure 2.14: The evolution of time domain wave of low frequency noise based on number fluctuation model.

2.3 Mobility fluctuation model

The second mechanism of low frequency noise is the result of mobility fluctuations.

The model was first proposed by Hooge in 1969 with the following empirical formula for

homogeneous semiconductors or metals [9]

0 5 10 15

2.06E-006

2.07E-006

1/f noise

0 5 10 154.60E-007

4.65E-007

4.70E-007

4.75E-007

4.80E-007 Tw o level RTN

0 5 1 0 1 59 .2 5E -0 0 7

9 .3 0E -0 0 7

9 .3 5E -0 0 7

9 .4 0E -0 0 7

9 .4 5E -0 0 7

9 .5 0E -0 0 7

9 .5 5E -0 0 7 M u lt i- le v e l R T N

Time


2RS

R fN

(2-3-1)

where SR is the spectral power density of the resistance, R is the resistance of the

sample, f is the frequency at which the noise is measured, N is the total number of free

electrons, and α is an empirical dimensionless constant with values ranging between

10−6 and 10−4. It is suggested that for a homogeneous semiconductor the Hooge

mobility fluctuation model is primarily generated by lattice vibration (phonon

scattering) as shown in Figure 2-14 [9].

Figure 2.15: A schematic for Hooge mobility fluctuation for a homogenous material.

Currently there is no well-accepted theory that explains Eq. (2-3-1). From the

viewpoint of mathematics, Eq. (2-3-1) hints that the spectral slope is directly

proportional to 1/f for all frequencies, which is not physically a stationary process since

the noise power will be infinite. The Hooge relation is an approximation of some real

physical mechanism at more limited frequencies, temperatures, materials, etc.

Electron

current

Lattice vibration

causes carrier mobility

fluctuation

1/f

noise

Homogenous Si

material

free carriers

lattice vibration


The only assumption behind Eq. (2-3-1) is that the factor 1/N results from

independent mobility fluctuations by each of the N conducting carriers. Musha and

Tacano suggest that energy partition among weakly coupled harmonic oscillators in an

equilibrium system is subjected to 1/f fluctuations [20]. Jindal and van der Ziel

proposed that the phonon population exhibits generation-recombination noise which is

transferred to mobility fluctuation noise through a fluctuating phonon scattering

mechanism [21]. However the real physical mechanism behind Eq. (2-3-1) is still an

open issue today.

In 1981 Hooge model for homogeneous semiconductors has been extended to

explain 1/f noise in a MOSFET, which suggests that 1/f noise in a MOSFET is mainly

a bulk effect; the carrier mobility fluctuations attributed to drain current fluctuations

has been extended to the 1/f noise in a MOSFET. This model is based on the

following empirical formula.

2id H

d i

S q

I fWLQ

(2-3-2)

The dimensionless parameter αH, referred to as the Hooge parameter, was

suggested to be constant and equal to 3-2×10-3, which depends on the crystal quality; in

perfect materials 2-3 order of magnitude lower values were observed. That is, in

high-quality materials, such as epitaxial layers, α values are in the range 10−6–10−4. In

damaged materials, whether due to mechanical or process induced damage, α values

are much higher.

The carrier mobility in a MOSFET is determined by the scattering of the free

electrons or holes. Several scattering mechanisms are present, which are as follows: 1)

bulk phonon scattering, 2) surface acoustic phonon scattering, impurity scattering by

charged or neutral centers, 3) surface scattering from the crystal boundaries, and 4)

electron scattering by other charged states (impurities) as shown in Figure 2-15.


Figure 2.16: Different mobility mechanisms in a MOSFET.

By assuming that the different scattering mechanisms act independently and have

the same energy dependence, the effective mobility μeff in the MOSFET inversion layer

a can be computed using Matthiessen’s rule. Although the conditions for using

Matthiessen’s rule seldom are fulfilled in practice, the formula still serves as a good

approximation for the effective mobility.

1 1 1 1 1

jeff j latt sr C (2-3-3)

where μb is the bulk phonon mobility, μac the mobility limited by surface acoustic

phonon scattering, μsr the mobility due to surface roughness scattering and μC the

mobility limited by Coulomb scattering mainly from ionized impurities/charges in the

gate oxide or in the poly-Si gate.

The different scattering mechanisms that limit the channel mobility in MOSFETs

vary in different ways with the effective (normal) electric field and density of inversion

charge as shown in Figure 2.15.

xx

n+ n+

p

inversion layer x

Phonon scattering

surface roughness

Coulomb scattering


The fluctuations in the different scattering processes are also assumed

independent.

2 2 2 2 2 2

eff j b ac sr C

jeff j b ac sr C

(2-3-4)

The Hooge model attributes the 1/f noise to mobility fluctuations caused by

phonon scattering [9]. However, some studies suggest that other scattering

mechanisms such as surface roughness and surface acoustic phonon scattering can also

play roles [22]. The exact mobility scattering mechanism for 1/f noise in a MOSFET

is still an open issue; in this thesis Hooge theory is followed and only the phonon

scattering term is considered as the 1/f noise source.

In Hooge model phonon scattering contributes low frequency noise thus the

following form results

Total

mobility

Coulomb

scattering phonon

scattering

surface

roughness

Effective electrical field (log scale)

Figure 2.17: Different scattering mechanisms that limit the channel mobility in MOSFETs.


2

,2 2

effidH H ph

d i ph i

S q q

I fWLQ fWLQ

(2-3-5)

and

2

,2

effH H ph

ph

(2-3-6)

where αΗ varies with gate bias due to the bias dependent factor “μeff2/ μph

2”. Thus αH

depends on both technology and bias conditions. However, compared to Qi, the

change of αΗ under different bias conditions is relatively small. In this thesis αΗ is

assumed as a constant.

Through Eq. (2-3-5) the gate bias dependence of Hooge mobility fluctuation

shows 1/Qi dependence as shown in Figure 2.17.

Figure 2.18: Hooge mobility fluctuation shows 1/Qn trend in gate bias dependence.

The drain current dependence of Sid/Id2 (fixed drain voltage and sweep gate

voltage) is proportional to 1/Id. An improved Hooge model accounting for the effects

-0.5 0.0 0.5 1.0 1.5 2.0

1E-11

1E-10

1E-9

1E-8

1E-7

1/Qn

Sid

/Id

2 (1

/Hz)

Gate Voltage (V)

TCAD simulationsHooge theorynMOSFET(W/L=10um/1um)


of parasitic source/drain resistance was also proposed in [23] and the effect of parasitic

source/drain resistance as shown in Figure 2.18 can change the drain current

dependence so Sid/Id2 1/Id

a. The exponent ‘a’ can be larger than one.

2.4. Diagnosis

In Sections 2.2 and 2.3 we have introduced ΔN model and Δμ model. Over the past

fifty years numerous publications have been outlined supporting one or the other

modeling camps. One can find sufficient support for each group, as well as several

arguments against the alternative. It is required to identify dominant low frequency

noise sources. Two basic diagnostic methods are introduced in this section.

(a) Sid/Id2 versus Vg

The first method is to plot the normalized drain current spectral density (Sid/Id2)

versus gate voltage (Vg). As shown in Section 2.2, based on ΔN model, the gate bias

dependence of Sid/Id2 should show a weak inversion plateau and then decrease (

Parasitic resistance

Parasitic resistance

Source Drain

Figure 2.19: Improved Hooge model includes the impact from parasitic source/drain resistance.


1/Qi2) in medium and strong inversion as shown in Figure 2.19 (a). On the other hand,

in the Hooge model, Sid/Id2 is usually inversely proportional to the inversion carrier

density (1/Qi). This leads to an exponential increase in noise according to the Hooge

model in the sub-threshold regime, with decreasing overdrive voltages as shown in Fig,

2.19 (b). Ref. [23] suggests that in the Hooge model there exists a minimum carrier

density (N0) in the weak inversion, and as such the minimum carrier density can also

cause the observed plateau. However a fundamental reason for the minimum carrier

density (N0) is still not clear in Hooge model. Moreover in some published

measurement data the normalized Sid does not show a plateau in the weak inversion

region [24] [25].

-0.5 0.0 0.5 1.0 1.5 2.0

1E-11

1E-10

1E-9

1E-8

1E-7

1/Qn

S

id/I

d2

(1/H

z)

Gate Voltage (V)

TCAD simulationsHooge theorynMOSFET(W/L=10um/1um)

ΔN model Δμ model

(a) (b)

0.0 0.5 1.0 1.5

1E-11

1E-10

1E-9

1E-8 Plateau

Sid

/Id

2 (1

/Hz)

Gate Voltage (V)

TCAD simulations G. Reimbold theorynMOSFET (W/L=10um/1um)

1/Qn2

Figure 2.20: Gate bias dependence of Sid/Id2 based on (a) number fluctuation model and (b)

gate bias dependence of Sid/Id2 predicted by Hooge mobility fluctuation model.


(b) Sid/Id2 (gm/Id)

2

The second common method is used for checking the dominance of channel

carrier number fluctuations is to see if Sid/Id2 is proportional (gm/Id)

2 as shown in Figure

2.21. If the ΔN model is dominant Sid/Id2 is proportional to (gm/Id)

2 as shown in Figure

2.21 (a). One thing should be remarked that in this case drain voltage is fixed and gate

bias increases from subthreshold to strong inversion. Drain current dependence of

Sid/Id2 at strong inversion can change slightly when correlated mobility fluctuations are

involved. However Sid/Id2 is still highly correlated to (gm/Id)

2.

On the other hand, if the bulk mobility fluctuations are the main cause of low

frequency noise, then Sid/Id2 is proportional to 1/Id as shown in Figure 2.21 (b). The

improved Δμ-based model accounting for the effect of parasitic series resistance can

change the slope in plot Sid/Id2 v.s. Id as shown in Figure 2.21 (b) [22]. However Sid/Id

2

is still not perfectly proportional to (gm/Id)2 [49]. Thus, this method, assuming Sid/Id

2

(gm/Id)2, can still separate ΔN and Δμ model when considering parasitic resistances.

2.5 Summary

Chapter 2 presents a brief review on the development of low-frequency noise study in

electron devices and the recent progress in developing an understanding and modeling,

which provides the background to understand the concepts in this thesis. Several key

issues are addressed: (1) the origin of low frequency noise can be attributed to the

channel carrier number fluctuation, which is more related to surface states and referred

as the ΔN model. The carrier trapping/de-trapping also induces "correlated" mobility

fluctuations through Columbic scattering. If there are only a few traps involved, the

current can switch between two or more states resembling random telegraph noise

(RTN). If there are multiple traps involved this causes a 1/f noise spectrum. (2) Low

frequency noise can be from mobility fluctuation (Δμ model) and with the empirical

formula, Sid/Id2=qα/fWLQi. There is no theory to explain this equation, but it is found


that the mobility fluctuations should be mainly from lattice vibrations (phonon

scattering). (3) Different low frequency noise models show different gate bias and

drain current dependence, which is used to diagnosis the main noise contribution source.

Figure 2.21: Drain current dependence of Sid/Id2 based on (a) number fluctuation model

and (b) Hooge mobility fluctuation model.

(gm/Id)2

Id

Id

(gm/Id)2 Sid/Id

2

α=0

α>0

α<0

Correlated mobility fluc. is considered

ΔN

model

Sid/Id2

Δμ

model

1/Id

1/Ida; a>1

parasitic S/D resistance is added.

(a)

(b)

CHAPTER 3. METHODOLOGY 41

41

Chapter 3

Methodology

In this chapter we will describe the methodology used in this thesis to study low

frequency noise in advanced CMOS technology such as high-κ gate dielectric (Chapter

4), SiGe channel (Chapter 5) and size effect (Chapter 6).

3.1 Introduction

The debate regarding the origin of low frequency noise mechanisms has continued for

fifty years. Although McWhorter's and Hooge theoretical models are useful for

providing qualitative explanations, a device level numerical model is nonetheless

necessary to quantitatively clarify the origin and analyze the impact of the low

frequency noise in MOS transistors.

The methodology used in this thesis includes two parts: 1). Technology

Computer- Aided Design (TCAD) simulations and 2). device characterization. TCAD

refers to the use of computer simulations to understand and develop semiconductor

technologies and devices. On the other hand, device characterization provides the

practical device information.

42 CHAPTER 3. METHODOLOGY

As shown in Figure 3.1, TCAD simulations provide the detailed physical

information and noise measurements can verify the parameters and models used in

TCAD. Through comparisons between TCAD simulations and device characterization

one can study the complicated low frequency noise mechanism in a MOSFET. In

Section 3.1 the low frequency noise measurement system is introduced and in Section

3.2 TCAD simulations are discussed.

Figure 3.1: A schematic of the methodology used in this thesis.

3.2 Noise characterization

Performing accurate, robust and repeatable measurements is critical to calibrating

meaningful TCAD simulations and to achieve an accurate low frequency noise model.

However, noise characterization is a sensitive process and it is necessary to ensure the

measured noise is from the targeted device and not from undesired disturbances. The

noise current is typically a few pico-amperes so it can be easily overwhelmed by

external noise from equipment and the environment. The measurement setup must be

designed carefully with appropriate shielding and preferably using batteries as power

sources to avoid disturbances from bias circuitry.

In this thesis two kinds of low frequency noise characterization are used:

frequency and time domain measurements. In the frequency domain, the power

spectral density is measured by a spectrum analyzer. On the other hand, in the time

TCAD simulations

Explore low freq.

noise mechanism Measurements


domain, the measurements are completed with the help of an oscilloscope. In Section

3.2.1 we will focus on frequency domain noise measurements and in Section 3.2.2

time-domain measurements will be discussed.

3.2.1 Low frequency noise characterization: frequency domain

The noise measurement setup follows that described in [25] and Figure 3.2.

Figure 3.2: A schematic of a low frequency noise measurement bench.

A device under test (DUT) can be on-wafter or in-package. In this work both

on-wafer and in-package measurement systems are implemented as show in Figure 3.3

and 3.4. Compared to on-wafer noise measurements, the noise measurements for

packaged chips are easier to add shields and isolate DUT from environment noise. On

the other hand, the packaging of devices is very time consuming and extra parasitic

elements from packaging are induced.

0

0

0

0

0

HP4156 Filter

<1Hz SR570

Signal analyzer

Cascade probe station (on‐wafer) or

circuit board (in‐package)

Spectrum analyzer (frequency) or

oscilloscope (time)


Figure 3.3: Low frequency noise characterization: an on-wafer noise measurement system.

Figure 3.4: Low frequency noise characterization: an in-package noise measurement system.

In the frequency domain noise measurements, the key elements of the setup are a

low noise amplifier (LNA) SR570, a Cascade probe station with enhanced shielding

(for on-wafer measurements), a circuit board for the packaged chip (for in-package

measurements), semiconductor parameters analyzer, HP4156, and the FFT spectrum

analyzer, SR760. In the following we will discuss these basic elements of a noise

measurement system.


The settings of SR570:

The use of a LNA for low frequency noise measurements is critical. Either current

or voltage amplifiers can be used in the measurement system; the choice of LNA

depends on the DUT characteristics. For high output resistance and high noise devices

such as MOSFETs and poly resistors, the current amplifier is a suitable choice. On the

other hand, for devices with low output resistance such as thin film resistors, a voltage

LNA is more suitable. For our purposes, MOSFETs are the DUT and a commercially

available current LNA, SR570 is used. The SR570 is battery powered for low intrinsic

noise, and provides the biasing of the DUT output. The SR570 is connected to the

drain of MOSFETs; there, it is biased to the desired voltage.

One thing should be noted. To amplify noise effectively the output, DC current of

DUT should be removed by a low noise offset current source. Thus, high gain can be

used and not to drive SR570 into saturation. However, the SR570 only provides for a

few DC offset options. The adjustment of offset current in the SR570 to match the

drain current of DUT can cause extra experimental complexity.

Also, there is a trade-off between gain and bandwidth in a LNA. The SR570 has

severe bandwidth limitations for the better sensitivities (high gain conditions). In the

low frequency noise measurements usually a high gain/low bandwidth setting is used

first to make sure the measured noise is the targeted one, and then one can try to

decrease gain and increase bandwidth to find the corner frequency of low frequency

noise. The corner frequency in MOSFET technology can be several MHz; the

bandwidth for the measurement system should be about several hundred MHz. In this

system the SR570 has ~1MHz bandwidth in the high bandwidth mode.

The SR570 should be connected to a high impedance load to efficiently transmit

the signal. It is necessary to check the impedance load when using the SR570.

Information regarding device input impedance can be found in the manuals. For low

input impedance equipment such as a sprectrum analyzer HP4396A, an active probe

should be used to transfer low impedance to high impedance.


The HP4156 settings:

HP4156 is used to bias gate, source, and substrate. Source and substrate are

connected to the ground of this system. In order to remove 60Hz AC power line noise

from the HP4156, a low pass filter is added in the gate bias path. A small output

resistance of the filter is used to reduce the thermal noise. In this work the resistor of

the low-pass filter is 50Ω and the cut off frequency was chosen as 0.3Hz.

The filter is built using metal film resistors, for lowest possible 1/f noise.

The settings of the probe station:

There are two different cascade stations in the Stanford Center for Integrated

Systems: the Cascade probe station and low-Temperature (low-T) probe station. Use of

the low-T probe station mainly offers three advantages: 1) better shielding and less

background noise. 2) lower likelihood of DUT oscillations. 3) very low temperature

(~k) and vacuity. However the low-T probe station is not convenient to set up and use

because of the extra and laborious experimental work that is required. For noisy

devices such as MOSFETs, the cascade probe station should be a better choice. For

special measurements such as low frequency noise versus temperature, the low-T probe

station can be considered.

In this work, the cascade probe station is mainly used because it is simple and

suitable for MOSFET measurements. However, there are several things to be noted

when using it. It is important to check the contact issues in the cascade probe station.

One must make sure that the tips are well connected. Loose probes usually cause extra

contact resistance, which impacts the noise measurement results. To reduce this error it

is necessary to check Id-Vgs curves before the noise measurements. Loose contacts

usually cause noisy Id-Vgs curves and in that case the probing should be repeated.


The ground loop and power supply issues:

Figure 3.5 shows the impact of power supply in low frequency noise measurements.

Through the comparison between battery power supply and DC power supply from

HP4156, we can see that the noise measurement is very sensitive to the quality of DC

power supply; the clean DC supply is required. In our measurements a battery power

supply is used in SR570 and in HP4156 to reduce the background noise. Figure 3.5 also

indicates the importance of the ground loop in the measurement settings, which causes

unexpected resonance and distort the measurement results. The path from the output

ground (ground of HP4156) to the input ground (ground of SR570) is usually about 2

meters. Unless aggressive shielding boxes are used, this ground loop, which is an

antenna, picks up parasitic noise from the environment, often rendering the DUT noise

unascertainable.

In this measurement bench the ground is from one center and the pattern of the

connection is a “center shape” as shown in Figure 3.6. In our measurement bench the

battery ground of the SR570 low noise amplifier is established for all components,

which is connected to Cascade probe station and all other components' grounds are also

connected to the same hub in Cascade probe station. Moreover all connections should

be as short as possible to minimize antenna effects.

Figure 3.5: Ground loop and DC power supply can significantly impact low frequency noise measurement results.

1 10 100

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

Sid

(u

A2 /H

z)

Frequency (Hz)

Battery power supply / ground loop

HP4156 power supply / ground loop

Battery power supply / no ground loop

1/f


Figure 3.6: Center-shape ground for all equipments in the measurements.

The settings for packaged chips:

Here we introduce the low-frequency noise measurement system for packaged

chips. The schematic is similar to the on-wafer low-frequency noise measurement

bench. The equipment of this system is shown in Figure 3.4.

The shielding box and circuit board which includes a low-pass filter are used in

this system. Since the measurement is for low-frequency application, the material of

the circuit can be a standard FR4. On the other hand, GML1000 material can be used

for a high-frequency application since the dielectric of GML1000 remains constant

through a broad frequency range.

Figure 3.7: A circuit board for in-package noise measurements.

V

to SR570

Circuit board (FR4)

Ground Equipment 1

(SR570)

Equipment 2

(HP4156) Equipment 3

(Cascade probe station)


The settings for spectrum analyzers:

In this noise measurement system, two kinds of spectrum analyzers are used: the

SR760 and HP4396A. The standard option for low frequency noise measurements is

SR760 whose measurement range is from 476 uHz to 100 kHz and has a dynamic

range of 90 dB. Moreover its input impedance is 1MΩ and 15pF so the SR570 can

connect to the SR760 directly.

Although the SR760 is a convenient option for low frequency noise measurements,

the corner frequency of low frequency noise in a MOSFET can be several MHz. To

measure the behavior of corner frequency, MHz bandwidth is required. In this case,

the other spectrum analyzer, the HP4396A can be used. The HP4396A is usually

used for microwave applications and the bandwidth is from 2Hz to 1.8GHz [26]. Thus

it can significantly increase the bandwidth of the measurement systems. However the

input impedance of HP4396A is designed as a 50 Ω load for microwave standards.

To connect HP4396A to SR570 an impedance transformation is required and an active

probe HP41800A is used. The HP41800A can transform the input impedance from

1M Ω to 50 Ω. Thus it is suitable to be the bridge between HP4396A and SR570. The

bandwidth of the HP41800A is from 5Hz to 500 MHz so it will not cause the limitation

of whole measurement system bandwidth. In this case the bandwidth of the

measurement system is from the bandwidth of LNA SR570 whose bandwidth is 1MHz.

Measurement results:

The frequency domain measurement results, Sid versus frequency, are shown in

Figure 3.8, which should be plotted in log-log scale.


Figure 3.8: Low frequency noise measurement results from the built test bench. Device Lg=1μm, width=1μm, Vth=0.6V, Vgs=0.45V and Id=8e-8A.

3.2.2 Low frequency noise characterization: Time domain

In addition to the frequency spectrum we are also interested in the time-domain

waveform of low frequency noise, which is especially important for RTN studies. The

settings of the time-domain measurements are shown in Figure 3.9. Since RTN is a

statistical phenomenon, to fully understand its impact on circuits, it is necessary to

assess the probability distributions of trap numbers, amplitude, and capture/emission

time, as well as their dependence on bias, which means that many samples must be

measured to obtain statistically useful information.

10-1 100 101 102 103 104 1051E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

Measurement results from our test bench

Sid

(u

A2 /H

z)

Frequency (Hz)

Vg=0.45V

1/f

High-k p-MOSFET Lg=0.1umHigh-κ nMOSFET, Lg=1μm, width=1μm, Vth=0.6V, Vgs=0.45V, Vd=0.7V, Id=8*10-8A


Figure 3.9: Time-domain low frequency noise measurement bench.

In the time domain measurement, instead of a spectrum analyzer, an oscilloscope

should be used. HP4156 is used as the oscilloscope in the time domain measurement

system.

Multiple samples and several bias conditions are required in the time domain

measurements. A total run of the measurements may take several days. Controlling the

HP4156 and cascade probe station every few minutes can get very tedious and time

consuming. For the measurements in this thesis, an automatic program was set up to

control cascade probe station and HP4156. To automatically control the measurement

system, the settings of noise measurements were simplified. Cascade probe station

connects to HP4156 directly and a computer controls the measurement flow as shown

in Figure 3.9.

The system has been rigorously verified through several RTN measurements.

Figures 3.10 shows a RTN measurement result and its Fourier transform.


Figure 3.10: Random telegraph noise results performed by the built test benches.

3.3 TCAD noise simulations

In this work, the Impedance Field Method (IFM) together is used, with the local low

frequency noise source modeling, to numerically investigate the low frequency noise

mechanism. In Section 3.3.1, the Impedance Field Method is introduced and in

Section 3.3.2, the low frequency noise simulation process is described.

3.3.1 Impedance field method

The Impedance Field was originally proposed by Shockley [27] in 1910; It is a transfer

function defined as the ratio of voltage perturbation at the terminal of interest (drain

terminal in our case) to the injected noise current at location r of the device.

_ _ _ _

_ _ _ _ _ _

th

kr

Voltage fluctuation at k electrodeZ

Injected current at r in the device

(3-2-1)

20 25 30 354.60E-007

4.65E-007

4.70E-007

4.75E-007

4.80E-007

I d (

A)

Time (s)

Vd=10mV Vg=570mV

0.1 1 101E-19

1E-18

1E-17

1E-16

FFT from time domain

Sid

(A

2/H

z)

Frequency (Hz)

Vd=10mVVg=570mVScaled nMOSFETL=50nmW=70nm

1/f2

Scaled nMOSFET:

Lg=40nm,width=70n

m, Vth=0.35,

Vgs=570mV, Vd=10mV


Assume that there is a current signal injection at the location r in the device as

shown in Figure 3.11, and the voltage fluctuations at the electrodes are then calculated.

The local noise generation can be modeled by injecting a current at a location r.

The contribution to noise at the k-th electrode from location r becomes:

2

kr inZ S (3-2-2)

where Sin is the power spectral density of the local noise source. The impedance field,

Zkr in Eq. (3-2-2) is squared because we are calculating the power spectral density at

the electrodes.

Integrating Eq. 3-2-2 over the whole area of the device gives the total noise at the

k-th electrode. Electrons and holes have their own transfer function respectively, and

the integration must be done for each carrier type:

22

ik nkr in pkr ipS Z S dv Z S dv (3-2-3)

Source Drain

Inject current

voltage fluctuation at drain +

‐ IFM

+‐

+ ‐

Figure 3.11: A schematic of impedance field method.


The first term in the above equation represents the contribution to noise from

electrons, and the second term the contribution from holes.

3.3.2 Low frequency noise simulations

The Impedance Field Method (IFM) approach was introduced in Section 3.3.1 and has

been broadly used for multi-dimensional MOS noise simulations. Simulations in this

work are carried out using a general device simulator, PROPHET [28] [29]. A

schematic plot of a typical n-type FET transistor is shown in Figure 3.12 (a). The oxide

is usually found to be associated with a high density of traps, where the inversion

carriers can be trapped or de-trapped through tunneling and cause low frequency noise.

The band diagram showing this tunneling process is given in Figure 3.12.

Figure 3.12: (a) Schematic plot of an n-type MOSFET and the IFM based physical model. (b) Band diagram along the gate stacks.

(a)

gat oxid Si

(b)


The numerical model in this thesis takes the Langevin approach analysis [30] for

non-local carrier tunneling. It solves the impedance field numerically for a system

including the trap rate equation [31].

The calculation of this low frequency noise model is illustrated in Figure 3.12 (a).

The microscopic noise source is modeled assuming that it originates from traps inside

the oxide layers. The total drain noise is thus obtained as

2( ) ( )id ntS dv A r S r (3-2-4)

where Snt(r) is the power spectral density of the Langevin force associated with the

trapping/de-trapping processes. In addition to the Poisson and carrier continuity

equations, a rate equation for the trapped electron density is solved for

self-consistency:

exp(( ) / )[ ]t T t t T F Bdn N n n E E k T

G Rdt

(3-2-5)

where the tunneling time τ, is again calculated using the Wentzel–Kramers–Brillouin

(WKB) method, and the trap energy level, ET, is set equal to EF for noise evaluations.

This Generation-Recombination (G-R) term is also subtracted from the continuity

equation for the channel carriers to ensure charge conservation. The trapped electrons

also enter into the source term of the Poisson equation. It is noted that this approach is

non-local from the simulation viewpoint. The grid points in the channel are coupled

with those inside the oxides; and this is reflected by the corresponding non-zero

off-diagonal entries in the Jacobian matrix. The Impedance Field Method is then

extended to solve A(r), taking into account this additional device equation.

( ) 2( )ntS r G R (3-2-6)

The microscopic noise source is modeled as white G-R noise Snt(r)=2(G+R)

according to [32]. In this physical model, the frequency dependence of the terminal

noise is produced implicitly by the frequency dependence of the impedance field. In


this model, two types of trap energy distributions are used: the uniform type and the

exponential type. In the latter case, it is assumed that NT (E) decays exponentially away

from the oxide band-edge Ec:

0 0( ) 1 exp[ ( )]( / 2)T e c TN E k E E E N (3-2-7)

where ke, E, and NT0 are parameters to characterize the trap energy distribution profile.

In this work, we adopt the unified model developed in [33], where the mobility

fluctuations are modeled as the consequence of additional Coulomb scattering of

channel carriers by the trapped charges. The local noise source is multiplied by a

correction term as follows

2 2

0

[1 ]fb

invid v m

c

NS S g

(3-2-8)

where n2D is the 2-D inversion carrier density and μc0 is a fitting parameter for

Coulomb scattering.

Beside trapping/de-trapping, the Hooge mobility fluctuations are also included in

the post processing of the TCAD simulations. Hooge empirical equation is used.

2

id

d inv

S q

I WLQ f

(3-2-9)

The parameters in this empirical equation are extracted from TCAD simulations.

The total drain current noise is calculated as the sum of the ΔN fluctuations as well as

the Hooge mobility fluctuations, i.e.,

_ _ _id total id unified id HoogeS S S (3-2-10)


3.4 Summary

Chapter 3 summarizes the methodologies used in this work. Low frequency noise has a

reputation of being difficult to understand. To clarify the physical mechanisms of low

frequency noise, a numerical model based on the Impedance Field Method (IMF) is

developed; it accounts for a trap-induced carrier number fluctuation, correlated

mobility fluctuations, and Hooge mobility fluctuations. Robust low frequency noise

measurement test benches are also constructed, including both frequency and time

domain measurements. In the frequency domain the noise analysis, i.e., SR570, is used

to amplify the current generated by test devices. HP 4156 provides the dc bias for test

devices and provides I–V measurements and the network signal analyzer SR 780 for

the measurement of the spectral density of the noise in the MOSFET. Time domain

measurements are used for the study of random telegraph noise. To measure a large

number of samples, the test bench is simplified and automated.

CHAPTER 4. GATE DIELECTRICS: LOW FREQUENCY NOISE IN HIGH-Κ MOSFETS 59

59

Chapter 4

Gate dielectrics: low frequency noise in high-κ MOSFETs

With ongoing scaling of device dimensions, the gate oxide needs to be thinned in order

to control the short channel effects. However the gate leakage current increases

exponentially with decreasing dielectric thickness. High gate leakage current causes

problems such as increased standby power consumption, reduced reliability, and

lifetime. By replacing the SiO2 with a high-κ material, a physically thicker gate

dielectric achieves the same capacitance and lower gate leakage.

4.1 Introduction

Novel gate-stack materials have major implications on low frequency noise

performance metrics. In particular, based on the number fluctuation model, low

frequency noise is intrinsically related to the oxide properties and expected to be

affected by new choices in technology. This chapter addresses fundamental issues in

low frequency noise of high-κ MOSFETs, with detailed measurements that are

supported by TCAD simulation results.

A schematic plot of a typical high-κ based (hafnium-based) n-type MOS transistor

is shown in Figure 4.1.

60 CHAPTER 4. GATE DIELECTRICS: LOW FREQUENCY NOISE IN HIGH-Κ MOSFETS

Figure 4.1: A schematic of the hafnium-based n-type MOS transistor.

The equivalent oxide thickness (EOT) is defined as

2SiOhigh

high

EOT t

(4.1.1)

which corresponds to the thickness of SiO2 that gives the same capacitance as that of

the high-κ gate dielectric with thickness thigh-κ and dielectric constant khigh-κ.

Figure 4.2 shows the measured and simulated Id-Vgs curves for a high-κ n-type

MOSFET

Figure 4.2: Measured and simulated Id-Vgs curve (Vd=0.7V) for a high-κ nMOSFET with 1μm gate length and 1μm gate width.

0.4 0.6 0.8 1.0

1E-7

1E-6

1E-5

1E-4

1E-3

Lin

ear

scal

e d

rain

cu

rren

t (A

)

Measurements TCAD

High-k nMOSFETLg=1um

Gate voltage (V)

Lo

g s

cale

dra

in c

urr

ent

(A)

0.0000

0.0002

0.0004

0.0006

0.0008

n+ n+

p

HfO2

SiON


4.2 Low frequency noise in high-κ MOSFETs

The high-κ material is usually found to be associated with high density of traps, where

the inversion carriers can be trapped or de-trapped through tunneling. The band

diagram of a multi-stack (Si/SiO2/HfO2/poly-Si) n-type MOSFET under inversion

conditions is illustrated in Figure 4.3.

Figure 4.3: Band diagram along high-κ gate stack in an n-type MOSFET.

As discussed in Chapter 2, because the trapped electrons obey binomial statistics,

only those traps with an energy level near the channel quasi-Fermi level, EF, have

significant number fluctuations. The simulation method introduced in Chapter 3 is used

in this chapter; different trap densities and tunneling parameters are applied in the

interfacial layer and the high-κ material.

Low frequency noise characterstics in a p-type MOSFET with HfO2 gate

dielectric and varying gate voltages from 0.45V to 0.65V are measured and simulated

as shown in Figure 4.4. The TCAD simulation results have been carefully calibrated

with experimental data.

SiON

Ef

gate

HfO2

channel

xx xx

Trap:Nt

τ(z)


Figure 4.4: Measured and simulated noise power spectrum density for high-κ n-type MOSFET with 1μm gate length.

Compared to SiON, typically high-κ materials show more traps; most reports

indicate that one to three orders of magnitude higher low frequency noise

characteristics are observed compared to standard CMOS devices, which is consistent

with the measurements shown in Figure 4.5.

Figure 4.5: Low frequency noise comparison between high-κ and SiON gate stack: in general a high-κ MOSFET shows higher low frequency noise.

0.1 1 10 100 1000 100001E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

0.01

Vg=0.65V

M easurem ents

Vg=0.55V

1/f

Sid

(u

A2 /H

z)

F requency (Hz)

High-k nM OSFETL=1umM easurem ents & TCAD

Vg=0.45V

TCAD

High-κ nMOSFET, Lg=1μm, width=1μm, Vth=0.6V, Vd=0.7V

1 10 1001E -10

1E -9

1E -8

1E -7

1E -6

1E -5

1E -4

1E -3

M easu rem en tsO verd rive vo ltag e= 0 .3Vn M O S F E T L g = 1u m

Sid

(u

A2 /H

z)

F req u en cy (H z)

1 /f

S iO N

H ig h -k


The impact of device scaling on the low frequency noise behavior in high-κ

MOSFETs is examined by developed TCAD simulations. Figure 4.6 (a) shows

simulated drain noise as a function of frequency for devices with varying channel

length. It can be seen that 1/f type noise is reproduced for frequencies up to 100 kHz. A

1/f2 behavior is observed for higher frequencies, which can be explained by the fact

that SiO2 trap density is much smaller than that of HfO2. The low frequency noise and

thermal noise meet at a corner frequency fc, which increases with reducing channel

length [31]. To further illustrate this trend, the low frequency noise at 1Hz and thermal

noise are plotted as functions of channel length in Figure 4.6 (b). It can be seen that, as

the channel length decreases, the magnitude of the low frequency noise increases much

faster than that of the thermal noise.


Figure 4.6: (a) Simulated drain current noise spectrum based on the built TCAD noise model. Devices with varying gate length of 30, 130, 230, 630, and 1230nm with width 1μm are simulated, respectively. Bias condition is Vd = 0.1V and Vg-Vth = 0.2V. (b) Low frequency noise at 1Hz and thermal noise as a function of gate length.

0.01 0.1 1

1E-19

1E-18

1E-17

1E-16

1E-15

1E-14

1E-13

1E-12

~1/L

TCAD simulations

Sid

(A

2 /H

z)

Channel length (um)

Low frequency noise Thermal noise

~1/L2.5

100 101 102 103 104 105 106 107 108 109 10101E-24

1E-22

1E-20

1E-18

1E-16

1E-14

1E-12TCAD simulations for high-k nMOSFETs

Thermal

1/f2

Sid

(A

2/H

z)

Frequency (Hz)

1/f

Scale down channel length

(a)

(b)


However, it should be mentioned that in high-κ MOSFETs with μm-level width,

the carrier number fluctuation tends to be more important,1 so the improvement of the

high-κ process can reduce the trap number; efficiently reducing low frequency noise as


Figure 4.7: Reduction of trap density in high-κ material can suppress low frequency noise in high-κ n-type MOSFETs.

Figure 4.8 shows the simulated profiles of low frequency noise contributions

inside the oxide at different frequencies. For this and the following simulations, the

device EOT is set to 2.3 nm (physical thickness 5.5 nm) with a 1 nm interfacial layer to

match with the actual device parameters given in [34]. A moderate dielectric constant

of 13.5ε0 is assumed for the HfO2 layer, and an affinity difference of 1.2eV is used

between the SiO2 and HfO2 layers. It is shown in Figure 4.8 that, for a given frequency,

the major noise contribution comes from traps at a certain depth into the oxide. As the

frequency decreases, the peak of the distributed noise moves deeper into the dielectric,

because those traps correspond to longer tunneling times.

0.1 1 10 1001E-7

1E-6

1E-5

1E-4

1E-3

0.01

Decrease Nt and reduce 1/f noise

High-k nMOSFETLg=1um

1/f

Sid

(u

A2/H

z)

Frequency (Hz)

Measurements

TCAD: Nt=3e19 /(cm3eV)



1 Here the high-κ MOSFETs have μm-level W/L. If W/L is nm-level, mobility fluctuation becomes diminant. Chapter 6 will discuss the details.


The height of the noise peak increases by about four orders of magnitudes as the

frequency decreases from 10k Hz to 1Hz, leading to the 1/f type noise behavior. Such

an observation agrees with that first reported in the work of [35].

Figure 4.8: Simulated profiles of distributed drain current noise contributions at inside the gate oxide using the built TCAD noise model. Two frequencies are simulated: (a) 1Hz and (b) 10k Hz. The device gate length is 0.18μm. Vd=50mV and Vg-Vth=0.3V.


The normalized drain noise Sid/Id2 is simulated at 1Hz, as shown in Figure 4.9. In

this simulation the device channel length is 1μm and the overdrive voltage varies from

sub-threshold to the strong inversion condition. As pointed out by G. Reimbold, the

fluctuation of carrier numbers is not equal to the fluctuation of occupied trap numbers

under the sub-threshold condition.

Instead, the correction due to the capacitances related to the charges at the gate

and depletion regions need to be considered. Therefore, Sid/Id2 approaches to a

saturated value in sub-threshold regime. The TCAD model we used is based on the

direct evaluation of the impedance field of the complete system, with the electrostatics

taken into account self-consistently. Hence, the saturation of the normalized drain

noise is correctly reproduced in agreement with G. Reimbold’s theory.

Figure 4.9: Normalized drain current noise as a function of overdrive gate voltage from simulations using the built TCAD noise model. The device gate length is 1μm and Vd is 50mV.

-0.2 -0.1 0.0 0.1 0.2 0.3 0.41E-10

1E-9

1E-8

Sid

/Id

2

Overdrive voltage (V)

High-k nMOSFET (Lg=1um)TCAD simulationsbased on Reimbold's theory


Simulated Sid/Id2 based on our TCAD model is compared with measured data [34]

at varying overdrive voltages. Simulation results are shown for both the uniform and

exponential trap energy distribution models (Figure 4.10).

Figure 4.10: Measured and simulated normalized drain current noise as a function of overdrive gate voltage. The simulations are based on the built numerical TCAD noise model with both the uniform and exponential trap energy distributions. In this simulation the device gate length is 0.18μm and Vd is 50mV.

For the uniform model, a uniform trap density of 3x1018/cm3eV in the HfO2 is

assumed. For the exponential model, the trap distribution follows Eq. (4-2-1).

0 0( ) 1 exp[ ( )]( / 2)T e c TN E k E E E N (4-2-1)

where ke, E, and NT0 are parameters to characterize the trap energy distribution profile.

-0.1 0.0 0.1 0.2 0.3

1E-8

1E-7

Sid

/Id

2 (1/

Hz)


Experiments Exponential distribution Uniform distribution


The values of NT0, ke and E0 are assigned to 4x1017/cm3eV, 6eV and 3eV are used

in simulations respectively. The uniform model produces uses a much stronger

overdrive voltage dependence of the normalized drain current noise than the

exponential model does. This is because when the gate bias increases, the channel

quasi-Fermi level can access trap levels closer to the conduction band-edge, which

possess higher apparent trap densities according to the exponential model. The

measured data shows a relatively weak bias dependence and matches the exponential

trap energy distribution model. To model low frequency noise in high-κ MOSFETs

accurately, the exponential trap energy distribution model in the high-κ gate stack is

required.

4.3 Halo doping

In highly scaled MOS transistors, halo doping profiles are used to suppress the short

channel effect as shown in Figure 4.11.

n+ n+

p

HfO2 SiON

p+ halo

Figure 4.11: Halo doping profiles are used in highly scaled MOS transistors.


It has been observed experimentally that the presence of Halo doping significantly

degrades the low frequency noise of short channel devices, mainly due to the

non-uniform threshold voltage distribution along the channel. In that work, an

analytical model considering channel segments with different Vth have also been

developed [36].

In this work a device with source/drain Halo doping profiles (1.8x1018/cm3) is

also simulated with the physical model. As shown in Figure 4.12 (a), the distributed

noise contribution profile exhibits two peaks in the oxide, corresponding to the

source/drain Halo doping positions in the lateral direction. This indicates that the same

amount of electron fluctuations cause greater current fluctuations in the Halo regions

than in the rest of the channel. This can be explained by the reduced inversion carrier

density in the Halo regions. In Figure 4.12 (b), the normalized low frequency noise as a

function of the overdrive voltage is simulated for devices with and without Halo

doping, respectively. The devices with Halo doping consistently exhibit higher noise

levels over the entire range of overdrive voltage.

4.4 Summary

TCAD simulations and noise measurements are used to investigate the low frequency

noise performance in FETs with high-κ gate stacks. Comparison between

experimental data and simulations suggest that the number fluctuation model is

dominant in high-κ MOSFETs and it is important to consider the non-uniform trap

energy distributions, which also indicates that the improvement of high-κ quality can

suppress low frequency noise. The negative impact of Halo doping on the low

frequency noise is evaluated with the aid of TCAD simulations.


Figure 4.12: (a) Simulated profile of noise contribution at 1Hz for a high-κ n-type MOSFET with halo doping. (b) Normalized drain current noise as a function of over drive gate voltage for two devices with and without halo doping, respectively. The device gate length is 0.18μm and Vd is 50mV.

-0.1 0.0 0.1 0.2 0.3 0.41E-8

1E-7

Sid

/Id

2


without halo with halo

TCAD simulationshigh-k nMOSFET Lg=0.18um

(a)

(b)

CHAPTER 5. CHANNEL MATERIAL: LOW FREQUENCY NOISE IN SI/SIGE/SI HETERO-MOSFETS 73

73

Chapter 5

Channel material: low frequency noise in Si/SiGe/Si hetero-MOSFETs

In this chapter we will discuss low frequency noise in p-type Si/Si0.7Ge0.3/Si

heterostructure MOS (SiGe p-HMOS) transistors. A layer-dependent low frequency

noise model has been developed to investigate low-frequency noise mechanisms in

SiGe p-HMOS and the simulation results have been carefully correlated with

experimental data. Quantitative agreement reveals the important role of the dual

channels in the low-frequency noise behavior of SiGe p-HMOS devices. A

physics-based compact low frequency noise model for SiGe p-HMOS is constructed to

estimate the circuit performance.

5.1 Introduction

Carrier velocity in the MOSFET channel at the top of the barrier near the source

(virtual source velocity) is the main driving force for improved transistor performance

with scaling as shown in Figure 5.1.

74 CHAPTER 5. CHANNEL MATERIAL: LOW FREQUENCY NOISE IN SI/SIGE/SI HETERO-MOSFETS

Figure 5.1: Virtual-source velocity vx0 as a function of the gate length; data is extracted from [37, 38]. Red symbols represent strain-engineered devices.

To continue the historical trend of MOSFET scaling, higher mobility channel

materials such as SiGe should be considered to achieve sufficient virtual source

velocity.

Compared to bipolar transistors, CMOS technology is superior in terms of low

cost and scalability. However MOS transistors generally show much higher low

frequency noise than bipolar transistors. Moreover the impact of CMOS scaling on low

frequency performance should also be evaluated carefully. Thus CMOS technology is

usually at a disadvantage in low noise applications. To make CMOS technology useful

in various analog/RF circuit applications, the evolution of new device structures and

materials should be considered.

While considering both transistor scaling and noise performance, heterostructure

MOS (HMOS) transistors with buried SiGe channels become an attractive candidate.

Research on the Si/SiGe/Si system has demonstrated that significant mobility

enhancements (e.g. 2× for electrons and 10× for holes) relative to Si MOSFETs, can be

achieved [39]. Recently high Ion/Ioff and well controlled short channel effects are

1002

4

6

8

10

12

Vir

tual

so

urc

e ve

loci

ty (

106 c

m/s

)

Gate length (nm)

w/o strain with strain

pMOSFET

1005

10

15

20

V

irtu

al s

ou

rce

velo

cit

y (1

06 c

m/s

)

Gate length (nm)

w/o strain with strain

nMOSFET


demonstrated in p-type Si/Si0.25Ge0.75/Si MOSFETs with a buried SiGe channel and

55nm gate length [40].

SiGe p-HMOS devices, particularly those operated using the dynamic threshold

(DT) scheme, have exhibited attractive low-frequency noise performance [41], [42]

owing to additional control of the body bias. In this chapter, device-level noise

simulation capabilities and careful noise characterization are provided and employed to

investigate the low-frequency noise behavior in the SiGe p-HMOS devices.

5.2 Device schematic

Figure 5.2 shows the cross section and band diagram along the vertical direction of a

SiGe p-HMOS.

Figure 5.2: Schematic plots of a SiGe p-HMOS device structure and a band diagram along the vertical direction.

As shown in Figure 5.2, a SiGe p-HMOS has a buried SiGe channel with a Si cap

layer; there are two channels inside the device: a parasitic surface channel and a SiGe

buried channel.

Two different SiGe p-HMOS devices and two control Si p-MOS devices are used

for this study on bulk and partially depleted (PD) SOI substrates, respectively. Table

5.1 gives a summary of simulated device structure parameters.


Table 5.1: Summary of simulated device parameters.

Devices EOT Si

cap

SiGe

channel

Gate

length

Gate

width

Vth Bulk

thickness

Set I Bulk p-MOS 8nm -- -- 1μm 10μm -0.44V 500nm

SiGe p-HMOS 8nm 6nm 14nm 1μm 10μm 0.01V 500nm

Set II PD p-MOS 6nm -- -- 1μm 10μm -0.27V 160nm

PD SiGe p-HMOS 6nm 9nm 15nm 1μm 10μm -0.14V 160nm

In this work, the oxide trap density NT is set to 4×1017 /cm3eV and 4.7×1017

/cm3eV for Si and SiGe devices, respectively. The Darwish mobility model [43] is

used with the parameters calibrated for both Si and SiGe materials. Simulated and

measured Id-Vgs curves of the studied devices are shown in Figure 5.3 (a)-(d).


Figure 5.3: Measured and simulated Id-Vg characteristics for (a) bulk Si0.7Ge0.3 p-HMOS, (b) control Si bulk pMOS, (c) PD Si0.7Ge0.3 p-HMOS, (d) PD control Si pMOS.

Figure 5.3 shows simulated SiGe p-HMOS carrier density for both surface and

buried channels as functions of gate voltage. The simulation parameters are based on

the SiGe p-HMOS in parameter Set I shown in Table 5.1.

-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.51E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Sim.: Vd=-0.1V Mea.: Vd=-0.1V Sim.: Vd=-0.5V Mea.: Vd=-0.5V Sim.: Vd=-3V Mea.: Vd=-3V

Dra

in C

urr

en

t (A

/um

)

Gate Voltage (V)

Si pMOS

-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.51E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Dra

in C

urr

en

t (A

/um

)

Gate Voltage (V)

Sim.: Vd=-0.1V Mea.: Vd=-0.1V Sim.: Vd=-0.5V Mea.: Vd=-0.5V Sim.: Vd=-3V Mea.: Vd=-3V

SiGe p-HMOS

-1.5 -1.0 -0.5 0.0 0.50

5

10

15

20

25

30

Vd=-0.5V

PD Si pMOS Simulation Measurement

Gate voltage (V)

Lin

ear

dra

in c

urr

ent

I ds

(u

A/u

m)

10-6

10-5

10-4

10-3

10-2

10-1

100

101

Lo

g d

rain

cu

rren

t I d

s (

uA

/um

)

-1.5 -1.0 -0.5 0.0 0.50

5

10

15

20

25

30

Simulation Measurement

Gate voltage (V)

Lin

ear

dra

in c

urr

ent

I ds

(uA

/um

) PD SiGe p-HMOS

Vd=-0.5V

10-6

10-5

10-4

10-3

10-2

10-1

100

101

Lo

g d

rain

cu

rren

t I d

s (

uA

/um

)

(a) (b)

(c) (d)


Figure 5.4: Simulated SiGe p-HMOS carrier density for both surface and buried channel as a function of gate voltage.

From Figure 5.4, it can be seen that in the weak inversion the carrier density in the

parasitic Si channel is negligible compared to that of the buried channel. So the weak

inversion region is characterized by the typical exponential dependence of current on

gate voltage

gV

kTdI e (5-2-1)

The extracted η is 1.55 and sub-threshold slope is 92.3 mV/decade. On the other

hand, the carrier density in the parasitic Si channel increases significantly when the

gate bias increases.

It should be noted that in a well-designed SiGe p-HMOS, the buried channel

usually turns on before the parasitic surface channel. If the parasitic surface channel

turns on before the SiGe buried channel, the screening effect from surface channel

charge shields the buried channel. In this case the surface channel becomes dominant

across the range of gate bias conditions.

-4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5

1E10

1E11

1E12

1E13

Ho

le D

ensi

ty (

1/cm

2 )

Gate Voltage (V)

Si cap layer SiGe buried channel

SiGe p-HMOS


5.3 Numerical low frequency noise model in a p-type

Si/SiGe/Si Hetero-MOSFET

As described in Chapter 3, combined with proper modeling of the local noise sources,

the impedance field method for low frequency noise simulations is based on the

modeling of tunneling-based nonlocal charge trapping/de-trapping, whereby the

number fluctuations are quantitatively modeled and an additional post processing step

is used to take into account the correction term of correlated mobility fluctuations,

according to the unified model as well as the contribution from the Hooge model.

A SiGe p-HMOS has two channels: a parasitic surface channel and the SiGe

buried channel. These two channels show different noise behavior. To understand low

frequency noise behavior for a SiGe p-HMOS, the carrier distribution in the surface

and in the buried channel should be considered separately. Here, a layer dependent low

frequency noise model is proposed to model both unified model and Hooge model.

(a) Layer-dependent unified model

Compared to the buried channel, the surface channel generally incurs higher

Coulomb mobility fluctuations, due to the fact that it is closer to the oxide interface as



To account for the correlated Coulomb mobility fluctuations, in the standard

unified model the noise contribution is multiplied by a correction term, i.e.,

2

2 0(1 / )D cn (5-3-1)

where n2D is the 2-D inversion carrier density and uc0 is a mobility fitting scattering

parameter, which depends on the interface properties and the material of gate oxide. In

a SiGe p-HMOS, the surface and buried channels possess quite different interface

properties. Thus the surface channel has higher correlated mobility fluctuations

compared to the buried channel. Therefore, a layer dependent correlated mobility

fluctuation is constructed. The correction term is applied to the 3-D carrier density n3D,

and the fitting mobility scattering parameter μc0_3D is a function of the vertical position,

which is used to model the different noise properties of the two channels.

2

3 0 _ 3(1 / )D c Dn (5-3-2)

Using simulation capabilities based on the improved numerical model, the low

frequency noise in p-type Si0.7Ge0.3/Si HMOS is simulated and carefully correlated

with experimental data in terms of its dependence on gate biases, drain currents, and

body biases, which will be discussed in Section 5.3.

traps

p+ p+

p

SiGe channel surface channel

more noisy more quiet xx xx

xx

Figure 5.5: Parasitic surface channel and SiGe buried channel show different low frequency noise performance.


(b) Layer-dependent Hooge model

Hooge mobility fluctuation model was suggested to be the low frequency noise

source and for SiGe p-HMOS, two uncorrelated Hooge parameters, αcap and αSiGe for

the cap and SiGe channels, respectively, are used to model the respective noise

components:

2 2

2 2 2( )cap dcapid SiGe dSiGe

d cap d SiGe d

q IS q I

I WLQ f I WLQ f I

(5-3-3)

where Qcap and QSiGe are the inversion charge densities at the surface and SiGe

channels; W and L are channel width and channel length respectively. The total drain

current noise is calculated as the sum of the layer-dependent ΔN-Δu fluctuations and

Hooge mobility fluctuations as shown in Eq. (3-2-10).

5.4 Results and discussions

The noise model in Section 5.3 has been correlated to measurement results and used to

investigate the low frequency noise behavior at various gate biases, drain currents, and

body biases in SiGe p-HMOS devices. In the noise simulations, the oxide trap density

NT is set to 4 × 1017/(cm3 eV) and 4.7 × 1017/(cm3 eV) for Si and SiGe devices,

respectively, and the fixed interface charge density is 1.75 × 1011/cm2.

(a) Gate bias and drain current dependence

Bulk SiGe p-HMOS and bulk Si control devices are used for this study. Different

gate biases are applied, ranging from subthreshold to strong inversion for each device.

In the layer-dependent correlated mobility fluctuation model, the 3-D mobility fitting

parameter μc0_3-D is set to 1.4 × 1011 and 1 × 1012 (cm)1/2/(Vs) for the surface (Si) and

buried (SiGe) channels, respectively. These values of μc0_3-D correspond to 2-D

parameter μc0_2-D values of 5 × 107 and 3.57 × 108 cm/(Vs) for the surface (Si) and

buried (SiGe) channels, respectively. The value in the surface layer is consistent with


the number reported in [44]. The larger value in the buried SiGe channel reduces the

correlated mobility fluctuation term in the SiGe channel compared to that in the Si

channel [63]; the reduction factor between the two channels agrees well with that used

in [45]. The Hooge parameters used in this thesis are 6 × 10−6 and 1 × 10−5 for the

SiGe buried channel and the surface channel, respectively, which are within the

expected reasonable range of 10−4−10−6 [46].

The normalized drain current noise Sid/Id2 at 10 Hz is plotted as a function of the

gate voltage in Figure 5.6. From Reimbold’s theory [8], the gate bias dependence of

Sid/Id2 should show a weak inversion plateau and then decrease in strong inversion. On

the other hand, in the Hooge model, Sid/Id2 is usually inversely proportional to the

inversion carrier density [22]. This leads to an exponential increase in noise in the

Hooge model in the subthreshold regime with decreasing overdrive voltages. As shown

in Figure 5.5, the measured Sid/Id2 at sub-threshold rapidly increases with decreasing

overdrive biases, indicating the applicability of the Hooge model in this regime. As

suggested from the simulated noise components in Figure 5.5, the Hooge model is

dominant in subthreshold, and the ΔN−Δμ unified model plays a major role under

strong inversion. The measured data for the p-HMOS in [21] show similar noise

behavior in subthreshold that is consistent with the proposed model. Moreover, low

frequency noise data for SiGe p-HMOS in strong inversion have been reported in [47]

and [48], which show trends in agreement with the measured and simulated results

presented here. An improved Δμ-based model accounting for the effect of parasitic

series resistance was proposed in [49]. It is found that this model is not directly

applicable in explaining the measured data in our devices when using realistic

source/drain series resistance values.


Figure 5.6: Measured and simulated normalized drain current noise Sid/Id2 at 10 Hz as a

function of the gate voltage for (a) Si pMOS and (b) SiGe p-HMOS.

In Figure 5.7, the measured and simulated Sid are plotted against the gate bias for

SiGe p-HMOS. Two sets of simulations have been reformed with and without

considering the layer dependence of the correlated mobility fluctuation model,

respectively. It is evident that in the nonlayer-dependent case, Sid decreases as the

(a)

-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.51E-12

1E-11

1E-10

1E-9

1E-8

1E-7

Vd=-0.1V

Unified model Hooge's model This work Measurements

Sid

/I d2

(1/H

z)

Gate Voltage (V)

SiGe p-HMOS

(b)

-2.5 -2.0 -1.5 -1.0 -0.5 0.01E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

Sid

/I d2 (

1/H

z)

Gate Voltage (V)

Unified model Hooge's model This work Measurements

Si pMOS

Vd=-0.1V


overdrive gate voltage rises above threshold. This is because, as the overdrive voltage

increases, more holes spill over into the surface channel. Without considering the

difference in the mobility fluctuations, the surface channel has much lower mobility,

and, therefore, the simulations lead to a reduction of Sid. Conversely, only when the

significant correlated mobility fluctuations in the surface channel are accounted for can

simulations predict the increase in Sid with increasing overdrive voltage, which is in

agreement with experimental data.

Other measurement results [50] have shown an increase in Sid with rising

overdrive biases, which further confirms the validity of our model.

Figure 5.7: Measured and simulated drain current noise Sid at 10 Hz as a function of the gate bias for SiGe p-HMOS. The gray dotted line neglects the layer dependent contribution of the correlated mobility fluctuation, whereas, in this work, different fitting mobility scattering parameters are used in the Si cap layer and in the SiGe channel, and Hooge mobility fluctuations are also accounted.

-2.0 -1.5 -1.0 -0.5 0.0

1E-23

1E-22

1E-21

1E-20

Sid

(A

2 /Hz)

Gate Voltage (V)

w/o layer dependence This work Measurements

Vd= -0.1V

SiGe p-HMOS


In Figure 5.8, the normalized drain current noise Sid/Id2 is plotted versus the drain

current for the two devices—Si and SiGe p-MOSFETs.

Figure 5.8: Measured and simulated normalized drain noise, Sid/Id2 at 10Hz (right

y-axis), together with (gm/Id)2 (left y-axis), as functions of the drain current. Data for

both (a) Si pMOS and (b) SiGe p-HMOS are shown.

(a)

(b)

1E-9 1E-8 1E-7 1E-6 1E-5 1E-410-2

10-1

100

101

102

103

104

105

106

107

Sim. Sid/Id2

Mea. Sid/Id2

Sim. (gm/Id)2

Mea. (gm/Id)2

Drain Currrent (A)

(g

m/I d

)2 (V

-2)

SiGe p-HMOS

Vd=-0.1V

10-15

10-14

10-13

10-12

10-11

10-10

10-9

10-8

10-7

Sid

/Id

2 (H

z-1)

1E-10 1E-9 1E-8 1E-7 1E-6 1E-5 1E-410-2

10-1

100

101

102

103

104

105

106

107

Sim. Sid/Id2

Mea. Sid/Id2

Sim. (gm/Id)2

Mea. (gm/Id)2

Drain Current (A)

(g

m/I d

)2 (V

-2)

Si pMOS

Vd=-0.1V

10-15

10-14

10-13

10-12

10-11

10-10

10-9

10-8

10-7

Sid

/I d2

(H

z-1)


As can be seen from the figure, Sid/Id2 and (gm/Id)

2 exhibit good correlation for

both devices; this can be regarded as additional evidence to support the unified model

under inversion conditions. On the other hand, the noise level increases with lower

drain current in subthreshold, which deviates from the saturation behavior of gm/Id.

This also indicates that the Hooge model is playing a dominant role in

subthreshold. This observation agrees with that reported in [24].

(b) Body Bias Dependence

The PD SiGe p-HMOS and PD Si pMOS devices are used for the study of body

bias dependence, the mobility fitting parameter μc0_3-D is the same as that for the bulk

devices. A contact to the body region has been fabricated in the PD devices to provide

direct body biasing. Such a body contact was originally designed for dynamic

threshold voltage (DT) mode operation, where the major device performance benefits

have come from efficient channel carrier modulation through body biasing [41], [42].

In Figure 5.9, the simulated and measured drain current noise spectra are given,

and four different body biases are applied, ranging from a reverse bias (0.2 V) to a

forward bias (−0.4 V); the overdrive voltage is kept at −0.3 V for each device.

It should be noted from Figure 5.8, that the low frequency noise in SiGe p-HMOS

is about one to two orders-of-magnitude less than low frequency noise in Si p-MOS.

The comparison is based on the same process technology, bias conditions and device

size.

In Figure 5.9 the simulation results agree well with the noise measurements, and

the strong body bias dependence of the drain current noise is observed in the SiGe

p-HMOS. The low frequency noise level decreases by about an order-of-magnitude as

the body bias is varied from a reverse bias to a forward bias in SiGe p-HMOS.

However, under the same conditions, the Si control device shows no observable body

bias dependence. It should be noted that in [51] the low frequency noise body bias


dependence was observed in Si pMOS, and the difference can be explained by the

quality of surface roughness.

Figure 5.9: Measured and simulated drain current noise spectra for (a) Si pMOS and (b) SiGe p-HMOS. The frequency range is 10 Hz to 1 kHz. Four body biases are used ranging from 0.2 to −0.4 V.

10 100 1000

1E-23

1E-22

1E-21

1E-20

SiGe p-HMOS

Vd=-0.5VVov=-0.3V

Sid

(A2

/Hz)

Frequency (Hz)

Vb=-0.4V

Vb=-0.2V

Vb=0V

Vb=0.2V

(a)

(b)

10 100 1000

1E-21

1E-20

1E-19 Vd=-0.5VVov=-0.3V

Vb=-0.4V

Vb=-0.2V

Vb=0V

Vb=0.2V

Sid

(A

2/H

z)

Frequency (Hz)

Si pMOS


Using the Darwish model, the parameter δ of carrier mobility limited by surface

roughness scattering μsr is set as 4.1 × 1015 V/s, which agrees with [43] and is about

two orders-of-magnitude larger than [51]. In the Hooge model, Sid is inversely

proportional to μsr2 [52]; therefore, compared with [51], the effect of an effective

vertical electrical field Eeff is about four orders-of-magnitude smaller. In Figure 5.10,

the hole density in the Si cap layer and the carrier density in the SiGe channel, as

functions of the body bias, are shown.

Figure 5.10: Hole density in the Si cap layer and carrier density in the SiGe channel as functions of the body bias. The small plot is from TCAD simulations of the band diagrams along the vertical direction for two body bias conditions (Vb = 0.2 V and Vb = −0.4 V).

The decrease in the body bias leads to an increased hole density in the buried

channel and reduces the hole density in the Si cap layer. The strong body bias

dependence of PD SiGe p-HMOS devices can be attributed to the redistribution of

carriers between the two channels with body bias changes; the surface channel incurs

higher mobility fluctuations than the buried channel. To clarify this point, in the inset

of Figure 5.10, simulated valence band diagrams are shown for two different body bias

conditions, while the overdrive voltage is kept constant. It can be seen that as the body

0.00 0.03 0.06

-4

-2

0

Vov: -0.3V

Ele

ctr

on

en

erg

y (e

V)

Vertical position (um)

Vb=0.2V: valence band, Ev Vb=0.2V: quasi-Fermi level, Fp Vb=-0.4V: valence band, Ev Vb=-0.4V: quasi-Fermi level, Fp

-0.4 -0.3 -0.2 -0.1 0.0 0.1 0.21E13

1E14

1E15

Vd=-0.5V

Si cap layer SiGe channel

Vov=-0.3V

Ho

le d

ensi

ty (

cm-2

)

Body bias (V)


bias varies from a reverse bias condition to a forward bias, the buried channel is pulled

closer to the quasi-Fermi level, so the carrier density in the SiGe buried channel

increases.

Figure 5.11 shows the drain current noise and the carrier density in the Si cap

layer at different body bias conditions ranging from a reverse bias to a forward bias.

Figure 5.11: Drain current noise, Sid (left y-axis) at 100 Hz, together with hole density in Si cap layer (right y-axis), as functions of body bias.

The correlation between the low frequency noise level and the hole density in the

Si cap layer indicates that the low frequency noise is mostly determined by the Si cap

layer carrier density due to higher Coulomb scattering near the Si cap layer. In PD

SiGe p-HMOS, the Si cap layer carrier density is efficiently modulated by the body

bias, leading to a strong body bias dependence of the low frequency noise level.

In Figure 5.12, the body bias dependence is also studied for different overdrive

bias levels.

-0.4 -0.3 -0.2 -0.1 0.0 0.1 0.21E-22

1E-21

1E-20

Sid

[A

2 /H

z]

Vov=-0.3V

Si cap layer hole density Simulated Sid Measured Sid

Body bias (V)

Vd=-0.5V

1E14

1E15

1E16

Ho

le d

ensi

ty (

cm

-2)


Figure 5.12: Simulation data for the drain current noise Sid as a function of the overdrive voltage at a frequency of 100 Hz.

When the overdrive voltage is small (−0.05 V), Sid is decreased by 16.4 times

from the reverse bias to the forward bias. However, when the overdrive voltage

increases (−0.6 V), the decrease in Sid from the reverse bias to the forward bias

conditions is just 3.8 times. In general, for a more negative overdrive voltage, a smaller

body bias dependence of the drain current noise level is observed. This can be

attributed to the fact that for more negative overdrive voltages, the carrier

concentrations in both channels are controlled by the gate electrode to a larger extent

and, therefore, less sensitive to body bias variations.

Figure 5.13 shows the simulated two-channel carrier density as a function of the

overdrive voltage for the reverse and forward body biases, respectively. It can be seen

that when the forward body bias is applied, in a region of smaller overdrive, both

buried and surface channels contribute to the total low frequency noise. However, with

larger overdrive, the hole density in the Si cap layer starts to dominate. Conversely,

when the reverse body bias is applied, the hole density in the Si cap layer is dominant

-0.6 -0.5 -0.4 -0.3 -0.2 -0.1

1E-23

1E-22

1E-21

1E-20

Vd=-0.5V

Sid

(A

2/H

z)


Vb=0.2V

Vb=0V

Vb=-0.2V

Vb=-0.4V

increase body bias


across the entire overdrive voltage range. For a larger negative gate bias, the hole

density in the Si cap layer is dominant for both reverse and forward body biases,

resulting in a smaller difference in the Sid values observed. However, with a smaller

negative gate bias, hole densities in the Si cap layer and in the SiGe channel are

dominant in the reverse and forward body biases, respectively; a larger difference in

the body bias dependence is observed for this condition. The results are consistent with

the gate bias dependence of Sid shown in Figure 5.13.

Figure 5.13: Carrier density for both surface and buried channels as a function of the overdrive voltage in two different body biases, −0.4 and 0.2 V.

(c) TCAD parameter sensitivity

It should be noted that to use TCAD simulations to investigate low frequency

noise mechanisms, it is important to check parameter sensitivities. Different TCAD

parameters can reverse the conclusions; larger Hooge parameters can result in the

conclusions that Hooge mobility fluctuation is dominant across the whole gate bias

range. To validate the conclusions made here, different TCAD parameters are

evaluated and compared to measurement results.

-0.6 -0.5 -0.4 -0.3 -0.2 -0.1

1E12

1E13

1E14

1E15

1E16

Vd=-0.5V

Si cap layer; Vb=0.2V SiGe channel; Vb=0.2V Si cap layer; Vb=-0.4V SiGe channel; Vb=-0.4V

Car

rier

den

sity

(1/

cm2

)



Larger Hooge parameters are used; αH are 5.3×10-5 for Si p-MOS and 2.7×10-5 for

SiGe p-HMOS respectively. An improved Hooge model based on [22, 49], which

includes the effects of parasitic source/drain resistance is used. In Figure 5.14, the

measured and simulated normalized Sid based on the improved Hooge model are

plotted against the drain current for SiGe p-HMOS.

Figure 5.14: (a) Improved Hooge model without the contribution of number fluctuation (b) Improved Hooge model with the contribution of number fluctuation.

1E-6 1E-5 1E-4

1E-11

1E-10

1E-9

SiGe p-HMOS

Sid

/Id

2 (

1/H

z)

Drain current (A)

Rsd 100 ohm 1000 ohm 3000 ohm 5000 ohm measurements

Improved Hooge modelw/ number fluctuations

(a)

(b)

1E-6 1E-5 1E-4

1E-11

1E-10

1E-9 Improved Hooge modelw/o number fluctuations

Sid

/Id

2 (1

/Hz)

Drain current (A)

Rsd 100 ohm 1000 ohm 3000 ohm 5000 ohm measurements

SiGe p-HMOS


The parasitic source/drain resistance of SiGe p-HMOS is extracted from TCAD

tool and the value is less than 2000 Ω/um. Two simulations are conducted with and

without considering the number fluctuations, respectively. It is evident that in the

non-number fluctuation case, the slope of the SId/Id2(Id) plot in log-log scale cannot fit

the experimental data. When the number fluctuations are considered and the trap

density is in the range of 1017 1/cm2 the slope of the SId/Id2(Id) plot in log-log scale can

increase and the quality of fitting is improved. However the slope still does not agree

the measurement data. When the parasitic source/drain resistance increases, the slope

can get a better fit; however, larger thermal noise from the parasitic resistance cannot

explain the measurement results in the strong inversion region. Only when the values

of αH and μc0 are around the values we proposed in the model (in Table I) can

measurement results be reproduced well. This indicates that the proposed low

frequency noise mechanism is a suitable one.

5.5 Compact model

While basic device characteristics and detailed low frequency noise properties for SiGe

p-HMOS have been reported in Section 5.1-5.4, a discussion of the connection

between the SiGe p-HMOS and analog/RF circuit performance is still lacking. In this

section a physics-based compact low frequency noise model for the SiGe p-HMOS is

demonstrated, based on capacitance division and respective charge distributions in the

dual channels. Using the proposed model, low frequency noise of an active load

amplifier based on the SiGe p-HMOS technology is studied.

5.5.1 Equivalent device model

To model low frequency noise for this device, the carrier distributions in the surface

and the buried channels should be considered separately and the screening effect

should be modeled under different bias conditions. In a well-designed SiGe p-HMOS,


the buried channel usually turns on before the parasitic surface channel. The compact

model presented here will mainly focus on this case.

As shown in Figure 5.15 three equivalent models are proposed to simulate

screening effects of the dual channel under different gate voltages: low, medium, and

high bias conditions; in the following we will describe the details in each case are

discussed as well as the modeling process.

Figure 5.15: The proposed model for screening behavior: under low Vg the dual-channel behavior is like two uncorrelated MOS. When Vg is larger than Vth_buried surface channel behavior can be modeled as a thin body device. If Vg is larger than Vth_surface, buried channel charges are saturated.

Low Vg:

High Vg:

Medium Vg:


(a) Low gate bias case

In the low gate bias case, the device is in the depletion mode and screening is

weak. In this case the behavior of two channels can be modeled as two uncorrelated

bulk MOS devices in parallel. The surface channel is modeled as a Si bulk MOS and

the device behavior can be calculated using conventional MOS equations.

_ _

_ _ _ _

2 (2 )2

Si a Si B Si bs

th surface bulk FB Si B Siox

qN VV V

C

(5-5-1)

log (1 )dm

surfaceox

CkTS

q C

(5-5-2)

where VFB_Si is the flab-band voltage, φB_Si is the difference between Fermi-level and

intrinsic level, Na_Si is the acceptor impurity density, and εSi is dielectric constant.

Ssurface is the subthreshold slope for this equivalent device, Cox is oxide capacitance per

unit area, Cdm is maximum depletion-layer capacitance per unit area, q is electron

charge, and Vbs is the body bias.

On the other hand, the buried channel can be modeled as a SiGe surface channel

MOS and the Si cap is part of its equivalent oxide thickness (EOT) i.e.,

oxox cap

si

EOT T T

(5-5-3)

Based on the 1-D Poisson equation solution, the buried channel threshold voltage

can be calculated as

_ _ _ _ _ max2 [ ( )][ ]cap ox

th buried FB Ge B Ge a Si cap a Ge d capSi ox

x xV V q N x N x x

(5-5-4)

and the maximum depletion region width is


_ _ _ 2max

_ _

2 (2 )Si B Ge bs Si a Ged cap cap

a Si Ge a Si

V Nx T T

qN N

(5-5-5)

In this expression Tcap is the Si cap thickness and xdmax is the maximum depletion

length. Using a modified depletion width and threshold voltage, conventional BSIM

equations [53] can be used to model this equivalent device structure.

Figure 5.16: Equivalent capacitance model (a) before and (b) after buried channel turns on.

(b) Medium gate bias case

When the bias gate increases and is between buried channel threshold voltage,

Vth_buried and surface channel threshold voltage, Vth_surface, this is the medium Vg case as

shown in Figure 5.15. Under this bias condition, the screening from the buried channel

charge, Qburied should be modeled. With regard to the screening effect from buried

channel charge, when the buried channel turns on, an inversion layer is formed at the

Si/SiGe interface and shields the bulk capacitance (Cbulk); the surface channel behavior

is like an equivalent fully depleted thin body MOS. The threshold voltage of this

equivalent thin body MOS, Vth_surface can be obtained through a capacitive division as

shown in Figure 5.16. Before the buried channel turns on, the vertical potentials can be

modeled as three capacitances in series (Cox, Ccap, and Cdep) and surface channel

potential, φsurface can be calculated as follows:


( )

( )ox cap dep

surface gcap dep ox cap dep

C C CV

C C C C C

(5-5-6)

When the gate bias exceeds Vth_buried the vertical potential reduces to two

capacitances in series (Cox and Ccap). The relation between the overdrive gate voltage,

Vov (Vg-Vth_buried) and its effect on surface channel potential can be calculated through

Ccap and Cox capacitance dividing i.e.,

_ _

_ _

( )

( )ov B Surface surface VthB cap

B Surface surface VthB ox

V C

C

(5-5-7)

where φB_Surface is the surface channel potential and φsurface_VthB is surface channel

potential when Vg is equal to Vth_buried, which is calculated through Eq. (5-5-4). If

surface channel potential becomes 2φB_Si the surface channel turns on and Vov at this

condition is defined as VovS; Vth_surface can be calculated as

_ _ _th surf thin th buried ovSV V V (5-5-8)

(c) High gate bias case

When the gate bias exceeds Vth_surface, the model gets into the case of high Vg

condition. In this case the screening effect results from surface channel charge where

as the surface channel turns on, the surface inversion layer shields the buried channel

and Qburied transitions into the saturation regine; buried channel behavior is like a MOS

with a fixed Vg, which is equal to Vth_surface.

The behavior of the surface channel combines a bulk MOS and a thin body MOS

model under low and high gate bias conditions respectively; a suitable smoothing

function is applied in the transition region. On the other hand, for the buried channel,

the behavior is like a bulk MOS, but the drain current is clipped when the gate bias

exceeds Vth_surface.


(d) Complete modeling process

It should be noted that if the surface channel turns on first, the buried channel will

be screened by the surface charge (Qsurface) before it transitions to strong inversion. In

this case the device behavior is just like a conventional MOS and the usual BSIM3

equations2 are used [53].

The whole modeling procedure for dual-channel behavior of a SiGe p-HMOS can

be summarized in Figure 5.17 Firstly Vth(surface_bulk) and Vth(buried) are calculated using

Eqs. (5-5-1) and (5-5-3). If Vth(surface_bulk) is smaller than Vth(buried), the surface channel

will turn on first and the device behavior is like a conventional MOS with threshold

voltage equal to Vth(surface_bulk). On the other hand if Vth(surface_bulk) is larger than Vth(buried)

the buried channel will turn on first and the proposed model (in Figure 5.14) can

calculate the dual channel behavior

Figure 5.17: Schematic plot of a SiGe HMOS and a band diagram along vertical direction.

2 BSIM4 includes several empirical parameters to address the MOSFET physical effects into sub-100nm regime. This compact model is mainly for a dual-channel effect in a long channel (Lg=1μm) MOSFET. To simplify the compact model, a BSIM3 is used in this work.


When the carrier distribution in both channels is obtained, the low frequency

noise behavior at various bias conditions in the SiGe p-HMOS can be simulated.

2 2

2 2 2

cap dcapid SiGe dSiGe

d cap d SiGe d

q IS q I

I WLQ f I WLQ f I

(5-5-9)

2 2cap

2 2 2Id

2 2 2 22 2SiGe

2

( )

cap dcap eff

cap cap dcap dcapid SiGe dSiGet fn

d cap d d SiGe dSiGe d

SiGe effSiGe SiGe d

R IkT

fWL N I IS S IN E

I WLN f I I WLN f IR IkT

fWL N I

(5-5-10)

_ _ _id total id unified id HoogeS S S (5-5-11)

5.5.2 Results and Discussions

In this section we apply the proposed compact model to study the gate bias and body

bias dependence for low frequency noise and circuit simulations based on the proposed

compact model is demonstrated.

In Figure 5.18 hole density in the dual channels is plotted as a function of gate

bias. The different subthreshold slopes indicate a different EOT for the two channels.

A plateau in strong inversion for Qburied explains the screening effect from Qsurface.


Figure 5.18: Hole density in dual channels versus Vg: different subthreshold slopes indicates different EOT for two channels and the flat part in strong inversion for Qburied explains the screening effect from Qsurface (Parameters are from set I in Table 5.1).

Based on the dual-channel charge distributions for different gate bias the low

frequency noise behavior at various gate biases can be obtained as shown in Figure

5.19.

Figure 5.19: Low frequency noise behavior at various gate biases in a SiGe p-HMOS.

-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5

0.000

0.002

0.004

0.006

0.008

Qburied saturates due to

shielding effect of surface channel

TCAD: surf. charge TCAD: buried charge Model

VG (V)

Lin

ea

r c

ha

rge

de

ns

ity

(C

/m2 ) Vd=-0.1V

10-14

10-13

10-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

10-2

Lo

g c

har

ge

den

sity

(C

/m2

)

-2.0 -1.5 -1.0 -0.5 0.0 0.51E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

Sid

/Id

2 (

1/H

z)

Gate Voltage (V)

TCAD this work measurements

SiGe p-HMOS

Vd=-0.1V


5.6. Summary

Low frequency noise mechanisms in the SiGe p-HMOS have been numerically

investigated and correlated with experimental data. The analysis is based on the IFM

with physical modeling of the local noise sources, including nonlocal trap/de-trap

processes from the gate dielectric. In particular, layer-dependent ΔN−Δμ fluctuations

with the Hooge mobility fluctuations are applied to separate treatments of the buried

and parasitic surface channels. Agreement with the observed variations of gate biases,

drain currents, and body biases suggests the applicability of the proposed low

frequency noise model for SiGe p-HMOS. Based on device capacitance and charge

distributions in these dual channels, a physics-based compact low frequency noise

model for SiGe p-HMOS is proposed. Excellent agreement between the compact

model calculations, TCAD simulations and measurements has been observed for a

variety of gate bias conditions.

CHAPTER 6. SIZE EFFECT: LOW FREQUENCY NOISE IN SMALL-AREA MOSFETS 103

103

Chapter 6

Size Effect: Low Frequency Noise in Small-area MOSFETs

In Chapter 5 hetero-MOSFETs have been discussed; these devices are very useful for

analog/RF applications. In addition to analog/RF applications low frequency noise

becomes a growing concern in digital applications such as for SRAM noise margin,

yield, device reliability and variations. In this chapter the focus will be on low

frequency noise mechanisms in small-area MOSFETs which are critical for future

digital IC designs.

6.1 Introduction

Constant downscaling makes the speed of the MOSFETs higher, lowers the power

consumption and enables a higher level of integration. However, downscaling does

not reduce low frequency noise; detailed understanding of low frequency noise

mechanisms involved in small area MOSFETs remains elusive, including consideration

of devices using high-κ dielectrics. There are several issues that compound the

problem as we will now discuss.

104 CHAPTER 6. SIZE EFFECT: LOW FREQUENCY NOISE IN SMALL-AREA MOSFETS

(a) Small gate area:

Due to the ever decreasing gate area, the number of charge carriers in the MOSFET

channel is continually decreasing, and single-electron, low-frequency noise phenomena

(random telegraph noise) becomes visible, which is quite different from the 1/f noise in

standard MOSFETs. Random Telegraph Noise (RTN) show a two-level amplitude

distribution and a Lorentzian power spectrum (Figure 6.1).

Figure 6.1: Random telegraph noise results performed by the built test benches.

(b) Variability:

RTN in small devices shows extreme variability; measured low frequency noise

can show variations in the amplitude, ΔI, mean ‘high’ time τupper and mean ‘low’ time

τlower. Thus many samples must be measured to obtain meaningful statistical data.

Recently it has been reported that threshold voltage variation (ΔVth) due to RTN

increases with scaling, just as variations due to random dopant fluctuations (RDF) [54].

Moreover recent studies also predict that the impact of RTN can exceed RDF for 3σ

devices at the 22nm technology node [55].

Cu

rren

t (A

)

Time (s)

τc

τe

ΔI

Corner freq.

1/f2

Freq. spectrum of RTN:a Lorentzian shape

Po

wer

sp

ectr

um

den

sity

(A2 /

Hz)

Frequency (Hz)


(c) High-κ material

Short channel MOSFETs require high-κ gate dielectrics to reduce gate leakage

current. Figure 6.2 shows the energy band diagram of a high-κ dielectric gate stack

along vertical direction. As discussed in Chapter 4, compared to SiON, high-κ

materials show different tunneling characteristics and trapping/de-trapping properties,

which complicate the understanding of the random telegraph noise mechanism.

All these issues affect future IC designs, especially in SRAM cells. In this

chapter the low frequency noise mechanisms in small area MOSFETs will be studied.

Figure 6.2: Compared to SiON, high-κ material shows different band structure and tunneling characteristics, which complicates the random telegraph noise mechanism.

6.2 Device schematic

Metal gate devices with Hafnium-based dielectrics fabricated on SOI substrates in a

conventional CMOS process flow [56] are used in this study. To continue Moore’s

SiON

gate channel

x xx x

HfO2

Tunneling behavior is different.


law, the device gate area has been aggressively scaled down. The devices studied

have W/L=70nm/40nm as shown in Figure 6.3.

Figure 6.3: Device area is aggressively scaled down to save cost and improve performance.

6.3 Experimental results

This section focuses on the mechanisms of RTN in high-κ devices and correlates

them to the PBTI behavior, as both phenomena share the same physical origin:

charge-trapping in the gate dielectric. The correlation of PBTI, Ig-RTN, and Id-RTN in

high-κ nMOSFETs is investigated. In this section, measurements are performed in the

linear drain current regime at room temperature, using a commercial semiconductor

parameter analyzer.

(a) PBTI measurements:

For high-κ devices, positive bias temperature instability (PBTI) can be attributed

to negative charge trapping in the high-κ dielectric and causes positive threshold

voltage shifts and simultaneously increased gate current (Ig), due to the phenomenon

known as SILC (Stress-Induced Leakage Current) [57] [58].

L

W S DL

WS D

Aggressively scale down device area.


Figure 6.4 shows Id/Ig-Vg characteristics measured under three conditions: before

stress, after positive stress, and after the negative recovery cycle [59].

Figure 6.4: Current-Voltage characteristics of a high-κ nMOSFET (W/L=450nm/30nm) before (solid line) and after stress. Stresses are conducted with positive stress (1.8V, dashed line) and followed by negative stress (-1.8V, triangle). Notice that large Vth shift and increased Ig occur after positive stress. Both Vth shift and high gate current recover during negative stress.

Three phenomena are revealed. First, the Stress-Induced Leakage Current (SILC)

is clearly observed in the stressed devices. Second, the threshold voltage is shifted in a

positive direction. Third, both additional gate current and threshold voltage shifts are

recovered after negative stress. During the stress condition, electrons are trapped in the

dielectric, triggering trap-assisted tunneling (TAT) and resulting in a higher gate

current. The trapped charge influences the gate potential and shifts the threshold

voltage. When charges are de-trapped (or recovered), both SILC and the threshold

voltage shift disappear. The trap location is in the high-κ dielectric stack; therefore

mobility degradation due to remote Coulomb scattering is directly related to interfacial

layer thickness shown in Figure 6.5 [60].

-0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.01E-13

1E-11

1E-9

1E-7

1E-5

IgI d (

A)

or

Ig

(A

)

Vg (V)

Before stress Positive stress Negative stress

Id


Figure 6.5: Measured electron mobility values at Ninv=3x1012cm-2 as a function of interfacial oxide thickness. The mobility values are corrected for ionized impurity Coulomb scattering. Thicker interfacial layer can reduce the Coulomb scattering between traps inside high-κ stack and channel carriers.

(b) Ig-RTN:

References [61] and [62] have already reported the phenomenon, Ig-RTN, which

can be a diagnostic tool for transistor oxide reliability; such data is also very useful for

understanding SRAM reliability. Figure 6.6 shows the measured two-level stochastic

behavior of gate current, which is a signature of RTN.

0.4 0.8 1.2 1.6 2.0 2.4

120

160

200

240

280

320E

lect

ron

mo

bil

ity

(cm

2 /Vs

)

Interfacial layer thickness (nm)

High-k metal gate nMOSFET(HfO2/TiN)


Figure 6.6: Gate current noise with respect to gate bias. Clean random telegraph noise signature is observed from Vg=0.8V to Vg=1.0V (W/L = 70nm/40nm).

Notice that many devices have the same gate bias dependence: for Ig-RTN, the

ratio of average time spent in the upper Ig state (τ+) to average time spent in the lower

Ig state (τ-) increases with increasing gate bias as shown in Figure 6.7.

5 .2 x 1 0- 1 1

5 .6 x 1 0- 1 1

6 .0 x 1 0- 1 1

6 .4 x 1 0- 1 1

3 .2 x 1 0 - 1 1

3 .6 x 1 0- 1 1

0 5 1 0 1 5 2 0 2 51 .6 x 1 0

- 1 1

1 .8 x 1 0 - 1 1

2 .0 x 1 0 - 1 1

Vg = 1.0V

Vg = 0.9V

Vg = 0.8V

Ig (

A)

Time (s)


Figure 6.7: The ratio of average time spent in the upper gate current state to average time spent in the lower Ig state ratio with respect to gate bias for high-κ nMOSFETs (W/L = 70nm/40nm).

The high gate current steps correspond to a trapped state and the low Ig current

steps reflect a de-trapped state, as shown in Figure 6.8 (a). This is consistent with

previous PBTI results, as the trapped charge increases Ig through TAT. We attribute the

gate bias dependence to a narrowing of the energy gap between quasi-Fermi level (Ef)

in the channel and trap level (Et) in the oxide as shown in Figure 6.8 (b), which is also

consistent with the PBTI and Id-RTN results.

0.6 0.7 0.8 0.9 1.0 1.1 1.20.01

0.1

1

10

Vg (V)

Device 1 Device 2 Device 3 Device 4


Figure 6.8: Definition of trapped time and de-trapped time (a): t+ means the system is in the upper state and a charge is trapped in the trap (trapped state). On the other hand t- means that the system is in the lower state and a charge is de-trapped (de-trapped state). This definition is consistent with our PBTI and Id-RTN results in HK nMOSFETs. The schematic illustration of electron trap during the RTN (b): demonstrates that a higher gate bias narrows the energy gap between quasi-Fermi level (Ef) and trap level (Et), resulting in higher probability of capturing electron into the existing traps.

(c) Id and Ig-RTN results:

In addition to Ig–RTN, Id and Ig noise are measured simultaneously and show

RTN behavior with similar temporal characteristics. Higher Ig corresponds to lower Id

and vice versa, as shown in Figure 6.9.

Time

t+

Ig

charge de‐trap (emission)

charge trap (capture)

Et

Ef

(a) (b)


Figure 6.9: Drain and gate current noise signal. Notice that the drain and gate currents track each other. Electron trapping (capture) increases Ig and decreases Id. Electron de-trapping (emission) recovers both Ig and Id (W/L = 70nm/40nm).

This result confirms that negatively trapped charge increases the threshold voltage,

resulting in a decrease of Id, and at the same time increases gate current through trap

assisted tunneling, which is consistent with the PBTI results.

RTN behavior with respect to gate bias was analyzed further as shown in Figure

6.10. From Figure 6.10, it appears that Ig-RTN is manifest at most gate bias conditions

whereas Id-RTN disappears at either low or high gate bias conditions as shown in

Figure 6.10 (a) and (d). This can be explained by the maximum sensitivity of the

device to trapped charges at peak gm, which is around half Vdd.

Ig-RTN comes directly from the physical event of charge trap/de-trap phenomena

and can be observed at most Vg conditions. On the contrary, Id-RTN comes from the

output characteristics of the single stage transistor amplifier, with Ig-RTN providing the

input noise source. For the low gm bias conditions, other noise components can become

dominant and distort Id-RTN.

Figure 6-11 shows the gate bias dependence of Id-RTN as well as the noise spectra

extracted from the Fourier transform of the time domain signal. A clear Id-RTN and

7 .0 0 E -0 1 2

7 .2 0 E -0 1 2

7 .4 0 E -0 1 2

0 1 0 2 0 3 0

1 .5 6 E -0 0 6

1 .5 8 E -0 0 6

1 .6 0 E -0 0 6

t r a p p e d s ta te

d e - t r a p p e d s t a t e

c h a r g e d e - t r a p(e m is s io n )

c h a r g e t r a p(c a p tu r e )

I g

(A

)I d

(A

)

T im e (s )


corresponding Lorentzian curve (1/f2) appear at Vg=0.57V; both disappear for

operation in the low gm require.

Figure 6.10: Id-RTN and Ig-RTN measured in different gate bias conditions (W/L = 70nm/40nm). A high correlation between Id- and Ig-RTN is observed in (b) and in (c); no correlation in (a) and in (d).

(b)

(c) (d)

(a)

5.80E-012

6.00E-012

6.20E-012

0 10 20 30

5.90E-007

6.00E-007

Vg=630mV

Ig (

A)

Id (

A)

Time (s)

8.00E-013

9.00E-013

1.00E-012

1.10E-012

1.20E-012

0 50 100 150 2003.60E-007

3.80E-007

4.00E-007

4.20E-007

Vg=400mV

Ig (

A)

Id (

A)

Time (s)

3.90E-012

4.00E-012

4.10E-012

4.20E-012

0 10 20 304.60E-007

4.70E-007

4.80E-007

Vg=570mV

Ig (

A)

Id (

A)

Time (s)

1.16E-011

1.18E-011

1.20E-011

1.22E-011

0 10 20 30

8.30E-007

8.40E-007

Vg=750mV

Ig (

A)

Id (

A)

Time (s)


Figure 6.11: Gate bias dependence of Id-RTN and corresponding noise spectra extracted from Fourier transform of time domain signals (W/L = 70nm/40nm).

To verify the 1/f noise mechanism in small area devices, 1/f noise is measured at

different drain current conditions. From the plot Figure 6.12 one can see Sid/Id2 is not

proportional to (gm/Id)2 and suggests that the main mechanism for 1/f noise in small

area devices is from Hooge mobility fluctuations. The slope in Figure 6.12 is about 1.7;

0.1 1 101E-19

1E-18

1E-17

1E-16


Sid

(A

2/H

z)

Frequency (Hz)

Vd=10mVVg=570mVScaled nMOSFETL=50nmW=70nm

1/f2

0.01 0.1 1 101E-23

1E-22

1E-21

1E-20

1E-19


Frequency (Hz)

Sid

(A

2 /H

z)

Vg=0.2VVd=20mVHK nMOSFETL=40nmW=70nm

1/f

0.1 1 101E-19

1E-18

1E-17

1E-16FFT from time domain

Frequency (Hz)

Sid

(A

2 /Hz)

Vd=10mVVg=750mVHK nMOSFETL=40nmW=70nm

1/f

150 155 160 165 170

2.05E-009

2.10E-009

2.15E-009

2.20E-009

2.25E-009

2.30E-009

Id (

A)

Time (s)

Vd=10mV Vg=0.2V

0 10 20 30 40

8.28E-007

8.32E-007

8.36E-007

8.40E-007Vd=10mV Vg=750mV

Id(A

)

Time (s)

20 25 30 354.60E-007

4.65E-007

4.70E-007

4.75E-007

4.80E-007

I d (

A)

Time (s)

Vd=10mV Vg=570mV


the large slope results from the effect of parasitic drain/source resistance as mentioned

in Chapter 2.

Figure 6.12: Sid/Id2 is not proportional to (gm/Id)

2, which suggests that the main mechanism for 1/f noise in small area devices is Hooge mobility fluctuation.

6.4 Simulation work

To understand the Vg dependence of Id-RTN TCAD simulations are developed based

on the McWhorter theory [8]. The simulation schematic is explained in Chapter 4; the

noise source is modeled as traps inside the high-κ layer. Through the Impedance Field

Method [27] the trap/de-trap fluctuation is correlated to the drain current noise.

Gaussian functions with a narrow characteristic length are used to define a single

trap location in space and at a specific energy as shown in Figure 6.13 (a) and (b). In

addition to the trapping/de-trapping fluctuations from the gate oxide, the Hooge

mobility fluctuations [22] from bulk phonon scattering are incorporated (Figure 6.14).

Through TCAD simulations the device parameters were extracted and the Hooge

mobility fluctuation was calculated [63].

1E-7 1E-6 1E-5

1E-10

1E-9

1E-8

1E-7

(gm

/Id

)2

Sid/Id2

(gm/Id)2

Drain current (A)

Sid

/Id

2 (1/

Hz)

Measurement resultsHigh-k nMOSFETW/L=70nm/40nm

0.1

1

10

100

1000


Figure 6.13: The single trap location in the simulation in real space (a) and in energy (b).

Figure 6.14: Schematic of the Hooge mobility fluctuation originating from bulk phonon scattering.

Figure 6.15 shows the noise simulation results for different gate bias conditions.

When the device is biased in the high gm regime (0.4V), the Id noise is sensitive to

oxide trapping/de-trapping fluctuations and RTN becomes dominant in the drain

terminal. When the gate bias shifts to the low gm regime (0.1V and 1.1V respectively),

Hooge mobility fluctuations overcome the RTN effect at the drain. In this condition,

instead of RTN, a 1/f noise spectrum is established at the drain, which is consistent

with the measurement results.

2.75nm

Et Ef

Vg=0V

1.75nm

0.24eV

(b)(a)


Figure 6.15: Noise simulation results in different gate bias conditions. The low frequency noise mechanism changes between the Hooge mobility fluctuation (1/f) and RTN (Lorentzian spectrum) depending on the gm value (W/L=70nm/40nm).

6.5 Statistical property

To study the statistical properties of the random telegraph noise, measurements have

been made with over 1000 small area devices (W/L=70nm/40nm). Figure 6.16 shows

four representative cases: 1) no RTN, 2) Ig-RTN only, 3) Id-RTN only and 4) both

Id-/Ig- RTN, as shown in Figure 6.16. From results in Section 6.1 to 6.4 the model can

explain cases 1, 2, and 4. However the physical mechanisms involved in case 3 are still

an open issue. One possible explanation is that the trap occupancy fluctuations happen

inside the space charge region of the MOSFETs [64] as shown in Figure 6.17. This

1E-4 1E-3 0.01 0.1 1 10

1E-23

1E-22

1E-21

1E-20

1E-19

1E-18

1E-17

Sid

(A

2 /Hz)

Frequency (Hz)

RTN from single trap/detrap 1/f noise from Hooge mobility fluc.

TCAD simulationVg=0.1VnMOSFETW/L=70nm/40nm

-0.4 0.0 0.4 0.8 1.20.0

2.0x10-5

4.0x10-5

6.0x10-5

8.0x10-5

gm

(1

/oh

m)

Vg (V)

L=40nmHK nMOSFETs

1E-4 1E-3 0.01 0.1 1 10 100 1000

1E-21

1E-20

1E-19

1E-18

1E-17

1E-16 RTN from single trap/detrap 1/f noise from Hooge mobility fluc.


Sid

(A

2/H

z)

Frequency (Hz)

0.1 1 10 100 1000 100001E-26

1E-25

1E-24

1E-23

1E-22

1E-21

1E-20

1E-19

1E-18

RTN from single trap/detrap 1/f noise from Hooge mobility fluc.


Frequency (Hz)

Sid

(A

2 /Hz)


kind of trapping fluctuation is not related to gate current directly, but can impact drain

current significantly.

Figure 6.16: Drain and gate current noise signal. Notice that the drain and gate currents track each other. Electron trapping (capture) increases Ig and decreases Id. Electron de-trapping (emission) recovers both Ig and Id (W/L = 70nm/40nm).

Ig Id

no RTN

Ig RTN

Id‐/Ig RTN

Id RTN


Figure 6.17: The trap occupancy fluctuation happens inside the space charge region of the MOSFETs can possibly cause Id-RTN without Ig-RTN.

Figure 6.18 shows the statistical properties of the RTN distribution. In the

measurements Vd is 10mV and Vg is 570 mV (the maximum gm condition). For

advanced fabrication processes technology (W/L=70nm/40nm), about 12% of the

devices show random telegraph noise with 9% in Ig-RTN, 2% Id-RTN and 1% both in

Id-/Ig- RTN. Through the statistical data we can observe that RTN already induces

device variability in gate and drain current which will become important when

considering SRAM yield and other device reliability issues.

HfO2

SiON

n+ n+

p

oxide

xx x

Trapping/detrapping happens in space charge region


6.6 Summary

In this chapter mechanisms for random telegraph noise in small area high-κ MOSFETs

are proposed and discussed in the context of evaluating experimental data. First, RTN

in high-κ n-MOSFETs is directly linked to PBTI. PBTI and RTN originate from the

same physical process: charge trapping in the high-κ dielectric. The correlation

between Id- and Ig-RTN is clearly observed. Ig-RTN is directly related to physical

trapping or de-trapping and the Id-RTN reflects the sensitivity of charge trapping as

determined by gm. To minimize the impact of random telegraph noise in small gate

area MOSFETs future development will require optimized high-κ technology and error

correction circuit solutions.

Figure 6.18: About twelve percent (12%) of MOSFETs (W/L=70nm/40nm) show RTN: 9% Ig-RTN, 2% Id-RTN, and 1% Ig-/Id-RTN. The statistical results are from one thousand devices with the same technology and structures.

CHAPTER 7. CONCLUSIONS 121

Chapter 7

Conclusions

As technology scales and supply voltages are dropping, low frequency noise has

become a major concern for both digital and analog systems constituting phase noise in

oscillators and variations in SRAM arrays. A deeper understanding of low frequency

noise is essential in order to optimize future systems that are more immune to noise,

able to allocate power efficiently and exploit current and developing understandings of

noise circuit optimalization for portable electronics, system on chip (SOC) applications,

electrical bio-implants, and electrical sensors. This chapter summarizes the

contributions of this dissertation and proposes future avenues of investigation in this

area of research.

7.1 Summary

CMOS-technology is very attractive since it combines low-cost, high performance, low

standby power, superior integration of functional capability, and scalability. However,

as the MOS device sizes scale down, low frequency noise does not automatically

decrease and its impact on low-frequency system noise performance needs to be

carefully evaluated. Such effects depend on size (channel length/width) scaling, gate

oxide (high-κ dielectrics) and channel materials (SiGe).

121

122 CHAPTER 7. CONCLUSIONS

This work provides the methodologies to analyze complicated low frequency

noise behavior which includes advanced numerical noise simulations and robust noise

characterizations. The numerical analysis is based on a TCAD implementation of the

Impedance Field Method with physical modeling of the local noise sources including

nonlocal trap/de-trap processes from the gate dielectric. State-of-the-art low frequency

noise measurements have been replicated using a Stanford Research LNA (SR570),

Cascade probe station, low pass filters, and a spectrum analyzer (or an oscilloscope).

An extensive study of CMOS scaling of low frequency noise has been provided,

which includes consideration of high-κ oxides, substrate doping (Chapter 4), SiGe

channels (Chapter 5), and sizing effects (Chapter 6). Herein, it has been shown that

high-κ MOSFETs usually suffer worse effects from low frequency noise because of

higher trap densities in the oxide. However, as high-κ technology becomes more and

more mature, low frequency noise performance will gradually improve. Low frequency

noise behavior of Si/SiGe/Si heterostructure MOS (HMOS) transistors were

investigated revealing attractive noise performance due to the separation between oxide

and channel carriers. Sizing effects in low frequency noise have been discussed as well

concluding that in small area MOSFETs, random telegraph noise becomes important

and its dynamic mechanism arises from charge trapping/de-trapping. It is suggested

that process optimization can minimize the effect of sizing.

The major findings derived in this work show that with ongoing scaling of device

dimensions, low frequency noise can be significantly suppressed through an optimized

device structure and careful material consideration.

7.2 Future Work

This thesis has presented frequency mechanisms in devices with high-κ, SiGe channel,

and small area MOS transistors; each case has shown that an improved noise behavior

can be achieved by utilizing smart device engineering that reduces the impact of critical

scattering and tunneling processes. There are still many possibilities to suppress low

CHAPTER 7. CONCLUSIONS 123

frequency noise in the future CMOS technology revealing fruitful avenues of study

which will surely advance the field.

As parasitic components become more and more dominant in anticipation of the

expected future direction of the scaling of transistors, a justifiably growing concern with

regard to the impact of parasitic influence in low frequency noise has been noted. An

obvious course of research, for example, would be an examination of low frequency

noise models and their careful modification would more fully address the effects of

source/drain resistance.

To achieve further enhancements of device speed, the use of high-κ gate dielectrics

and a high mobility channels are necessary. Research on low frequency noise in high

mobility channel concepts together with high-κ gate oxide is urgently needed. Moreover,

as the channel length is now being reduced to the ballistic transport limit, low frequency

noise shows a different behavior and becomes an interesting subject for future study.

When scaling down the gate area, random telegraph noise causes serious device

variability, which significantly impacts in SRAM yield. To suppress the SRAM system

variation, an error correction circuit design should be considered with Ig-RTN and

Id-RTN effects. A combination of process and circuit solution will be needed to enable

continued SRAM cell scaling.

More theoretically, just 1% of the applicable devices reveal Id-RTN, but not

Ig-RTN. Currently there is no theory to explain this result. A suitable model for this

phenomenon can help us understand and produce a more complete picture of RTN

mechanisms in scaled MOSFETs.

124 CHAPTER 7. CONCLUSIONS

APPENDIX A 125

125

Appendix A

Low Frequency Noise Simulation Code

This appendix provides the information to run noise TCAD simulations in PROPHET. To

download PROPHET please refer to Stanford TCAD group website

(http://www-tcad.stanford.edu/~prophet/).

This example is a high-κ nMOSFET with 45 nm gate length and Halo doping. The code is as

follows.

# This part of code is to define a high‐k nMOSFET

dbase createlist name=/library/physics/HfSiON

dbase create name=library/physics/HfSiON/SeeAlso sval="/library/physics/oxide"

dbase createlist name=/library/physics/HfSiON/electrons

dbase create name=library/physics/silicon/electrons/background rval=1e‐20

dbase create name=library/physics/HfSiON/electrons/SeeAlso

sval="/library/physics/silicon/electrons"

dbase modify name=library/physics/oxide/epsilon rval=13.5

dbase modify name=library/physics/oxide/psi/Dix sval="13.5*$library/physics/epsilon0"

126 APPENDIX A. LOW FREQUENCY NOISE SIMULATION CODE

dbase modify name=library/math/systems/default_numerical_parameters/NewtonMaxUpd

rval=1e20

dbase create name=library/math/systems/default_numerical_parameters/InfinityCheck ival=1

dbase modify name=library/math/systems/default_numerical_parameters/maxNewton ival=50

dbase create name=options/Etail rval=3.0 #3.0

dbase create name=options/ke rval=6 # 4.5/eV

dbase create name=/options/build_boxV ival=1

dbase create name=/options/ignoreFPE ival=1

dbase create name=options/tunnel ival=0

include(silicon_poisson_tunnel)

include(silicon_dd_tunnel_mob0)

grid xloc=0.0000,0.0010,0.0100,0.0500,0.1100,0.3000

+ xdel=0.0003,0.0008,0.0020,0.0050,0.0050,0.0500

+ yloc=‐0.05,‐0.03,‐0.0225,‐0.0175,0.000,0.0175,0.0225,0.03,0.05

+ ydel=0.0050,0.00250,0.00125,0.00125,0.0025,0.00125,0.00125,0.00250,0.0050

+ dim=2

deposit mat=HfSiON start=‐0.0225 end=0.0225

+ thick=0,0.0005,0.00275 xdel=0.0001,0.00005,0.0001

APPENDIX A. LOW FREQUENCY NOISE SIMULATION CODE 127

deposit mat=poly start=‐0.0225 end=0.0225

+ thick=0,0.0025,0.02225 xdel=0.00025,0.0015,0.005 zipper

boundary xmin=0 xmax=0 ymin=‐0.05 ymax=‐0.03 name=source

boundary xmin=0 xmax=0 ymin=0.03 ymax=0.05 name=drain

boundary xmin=‐0.025 xmax=‐0.025 ymin=‐0.0225 ymax=0.0225 name=gate

boundary xmin=0.3 xmax=0.3 ymin=‐0.2 ymax=0.2 name=substrate

field set=psub val=‐6e17 mat=silicon

field set=pch val=‐2.4e18*0.5*(1+erf((X‐1+0.5)/0.01)) mat=silicon

field set=sdiff mat=silicon

+ val="1e20*gbox(X,0,0,0.0035)*gbox(Y,‐0.05,‐0.02,0.001125)"

field set=ddiff mat=silicon

+ val="1e20*gbox(X,0,0.0,0.0035)*gbox(Y,0.02,0.05,0.001125)"

field set=ns mat=silicon

+ val="1e20*gbox(X,0,0,0.0184)*gbox(Y,‐0.05,‐0.04,0.00735)"

field set=nd mat=silicon

+ val="1e20*gbox(X,0,0.0,0.0184)*gbox(Y,0.04,0.05,0.00735)"

field set=npoly mat=poly

+ val=1e20


field set=sHalo mat=silicon

val=‐3.5e18*gbox(X,0.0105,0.0105,0.02385)*gbox(Y,‐0.05,‐0.025,0.0096)

field set=dHalo mat=silicon

val=‐3.5e18*gbox(X,0.0105,0.0105,0.02385)*gbox(Y,0.025,0.05,0.0096)

field set=netdope val=psub+pch+ns+nd+sdiff+ddiff+npoly+sHalo+dHalo

field set=Qfix val=1.2e19*gbox(X,‐0.002,0.0,0.0001) mat=HfSiON #fixed negative charge

field set=eps_SiO2 val=3.9*8.854187817e‐6 mat=HfSiON

field set=eps_HfO2 val=(13.5‐3.9)*8.854187817e‐6*gbox(X,‐0.00275,‐0.0005,0.000025)

mat=HfSiON

#Til_SiO2=1.0nm

field set=eps_ins val=eps_SiO2+eps_HfO2

graph gridline quantity=netdope contour color

bias initial system=silicon_poisson_tunnel

dbase create name=options/tunnel ival=1

#note that the distributed material should be named as tunnelmat1

dbase create name=options/tunnelmat1 sval=HfSiON

dbase create name=options/tunnelmat2 sval=silicon

dbase create name=options/tunneldist rval=2.7e‐3


dbase create name=library/physics/HfSiON/electrons/Dix rval=1e‐79

dbase create name=options/Til_SiO2 rval=0.0010 #define the SiO2 interfacial layer thickness to be

1.0nm

dbase create name=options/epsilon_highk rval=13.5

dbase create name=options/epsilon_SiO2 rval=3.9

dbase create name=options/CB_offset rval=1.2

#1.8, C.B. offset between HfO2 and SiO2. value from Robertson EJAP

dbase create name=options/Nc0_srh rval=1e19

field set=nc1 val=2.86e19 mat=silicon

field set=nc2 val=0 mat=HfSiON

field set=nc3 val=1e1 mat=HfSiON

field set=nc0 val=nc1+nc2+nc3

field set=affinity1 val=2.0 mat=silicon #1.4

field set=affinity2 val=0 mat=HfSiON

field set=affinity0 val=affinity1+affinity2

field set=chi val=0 #needed in phyterm band

field set=et val=0.4 mat=HfSiON #1.45

field set=et_s val=0.4 mat=HfSiON #0.6

field set=nt0 val=1e14 mat=HfSiON #trap density in HfO2


field set=nt1 val=0 mat=HfSiON

field set=nt val=nt0+nt1

field set=tau0 val=1e‐10 mat=HfSiON #1e‐11

field set=electrons val=1e0 mat=HfSiON

field set=mnt1 val=0.3

field set=mnt2 val=(0.4‐0.3)*gbox(X,‐0.0010,0,0.0001)

field set=mnt val=mnt1+mnt2

field set=mn val=0.35 #"0.4172*4"

field set=channel val=1 xrange=[0:0.1] yrange=[‐0.09:0.09] mat=silicon

dbase modify name=library/physics/silicon/electrons/darwish_alpha rval=3.5e‐21 #original

6.85e‐21

Before running noise simulations DC simulations (Id-Vgs) should be done first.

bias system=silicon_dd_tunnel_mob0 elec=drain voltage=0.0

bias system=silicon_dd_tunnel_mob0 elec=drain,gate voltage=1.0,0.35

graph iv outfile=nmos.iv

dbase dump=nmos.db

save pas=nmos.pas


Then we start to run low frequency noise simulation. The code is as follows.

load pas=../nmos.pas

dbase create name=options/printtunnel ival=1

bias system=silicon_dd_tunnel_mob0 elec=gate,drain voltage=1,0.35

graph quantity=psi ypos=0 reg=HfSiON print outfile=psi_v.txt

graph quantity=psi xpos=‐0.0010 reg=HfSiON print outfile=psi_h.txt

noise noutfile=gradA.out houtfile=acrh_dd_d.out electrode=drain

+ electrode2=gate f=1e0 method=1

APPENDIX B 133

133

Appendix B

Compact Model Code for Dual-Channel Behavior

This appendix provides a Verilog-A code to model dual-channel behavior in a p-type

Si/SiGe/Si hetero-channel MOSFET.

`include "constants.vams"

`include "disciplines.vams"

module sigefet(d, g, s, b);

inout d, g, s, b;

electrical d, g, s, b;

//****** Parameters ******//

parameter real w = 10e‐6; //# Width

parameter real l = 1e‐6; //# Length

parameter real tox = 5.5e‐9; //#oxide thickness

parameter real dox = 0.33e‐9; //#Quantum effect

134 APPENDIX B. COMPACT MODEL CODE FOR DUAL-CHANNEL BEHAVIOR

parameter real nsd = 2e26; //# SD doping

parameter real ng = 2e26; //#poly gate doping

parameter real nch = 1e20; //# channel doping

parameter real tcap = 11e‐9; //# cap layer thickness

//****** Fitting Parameters ******//

parameter real fitting =0.0075; //# smooth function for the buried charge

parameter real fitting1 =0.3;

//# smooth function for surface charge (thin‐body approx & bulk)

parameter real fitting2 =‐0.27;

//# minor tuning for the gate voltage when Surface channel turns on and Qb saturates

parameter real delta_Vfb =0.7; //# fitting for the equivalent Qot for buried channel

parameter real delta_Vth =0.15; //# Vth difference bet. thin‐body and bulk in surface channel

parameter real delvto = 0;

parameter real eta0 = 0.0058;

parameter real dsub = 0.1;

parameter real dvt0 = 1;

parameter real dvt1 = 2;

parameter real cdsc = 0;

parameter real cdscd = 0;

APPENDIX B. COMPACT MODEL CODE FOR DUAL-CHANNEL BEHAVIOR 135

parameter real ua = ‐6e‐010; //# surface mobility

parameter real ub = 9e‐018; //# surface mobility

parameter real k1 = 0.4; //# body effect

parameter real xl = ‐100e‐9; //# mask litho

parameter real lint = 5.25e‐9; //#lateral diff

parameter real lpe0 = 0e‐9; //# Halo effect

parameter real a0 = 1;

parameter real Xj = 2.4e‐8; // Junction depth

//****** Physical constants ******//

parameter real q = 1.60217653e‐19;

parameter real k = 1.3806505e‐23;

parameter real T = 300;

parameter real e0 = 8.854187817e‐12;

parameter real eox = 3.9;

//##### Si parameters #####//

parameter real VAS = 10; //# surface Si

parameter real voffS = ‐0.35; //#buried SiGe subthreshold

parameter real u0S = 0.065; //# surface Si


parameter real deltaS= 0.01 ; //# surface Si

parameter real vsatS = 22000; //# surface Si

parameter real Egsi = 1.12; //# surface Si

parameter real esi = 11.7; //# surface Si

parameter real ni = 1.45e16;

//##### SiGe parameters #####//

parameter real nfactor = 1.0; //#buried SiGe subthreshold

parameter real voff = ‐0.45; //#buried SiGe subthreshold

parameter real VA = 100; //#buried

parameter real u0 = 0.09; //# buried SiGe

parameter real delta = 0.01; //#buried

parameter real vsat = 30000; //#buried

parameter real Egsige = 1.0; //#

parameter real esige =13; //#

parameter real nisige =7e16; //#

//****** Y Defined Parameter ******//

parameter real kc = 0.65;


//##### Electrical Definition for Terminals #####//

real Vds, Vgs, Vbs;

// ##### Buried Channel Parameters #####//

real leff, Vt, cox, coxp, phins, Vfb, Vbi, qbm, Vbc, Vbseff1, Vbseff, Xdep, lt, Xdep0,lt0, Vth,

n;

real Abulk, Vgse, Vgst, ueff, Esat, Vdsat, Vdseff, Xdc, cen, coxeff;

real phinB_si, phinB_sige, tcapeff, coxB, coxpB, phinsB, Wdb, Cbb1, Cbb2;

real VthB, VthS_thinbody, VthS_bulk, Vth0;

real Vfb_sige, Qb0, Qbsat, Qb_final, beta_final, beta ;

real Vgssat, Vgsesat, Vgstsat;

real Idso_buried, Ids_buried;

real ccap;

// ###### Surface channel parameters ##### //

real VfbS, VbiS, qbmS, VbcS, Vbseff1S, VbseffS, XdepS, ltS, Xdep0S, lt0S;

real Vth0S, VthS, nS, AbulkS, VgseS, VgstS, ueffS, VgstS_bulk;

real EsatS, VdsatS, VdseffS, XdcS, cenS, coxeffS, betaS, Vth0_bulk, XdcS_bulk;

real Qs_thinbody, Qs_bulk, Qs_sum, Qs_final;

real cenS_bulk, coxeffS_bulk,betaS_bulk, betaS_final;

real IdsoS, IdsS;


real VthS_thinbodyS, VthBB;

// ##### Body bias coefficient ##### //

real k1buried=1.15;

real k1surf=0.6;

real abc =2 ;

analog

begin

Vds = V(d, s);

Vgs = V(g, s);

Vbs = V(b, s);

//###### Leff #####//

leff = l + xl ‐ 2 * lint;

Vt = k * T / q;

//###### bulk potential #####//

phinB_si = Vt *ln(nch/ni); //#

phinB_sige = Vt *ln(nch/nisige); //# dominated by "nisige"

//###### Capacitance for Surf & Buried Channels #####//


cox = eox * e0 / (tox + dox);

coxp = eox * e0 / tox;

tcapeff = tcap * (eox/esi) ; //#

coxB = eox * e0 / (tox + dox + tcapeff); //#

coxpB = eox * e0 / (tox + tcapeff); //#

ccap = esi *e0 /tcap ;

//###### Surface potential (2* phinB) for Surf & Buried channels #####//

phins = 2 * Vt * ln(nch / ni);

phinsB = 2 *phinB_sige; //#

//###### Depletion Width for buried #####//

Wdb =sqrt(2 * e0 * esige * phinsB / q / nch); //#

Cbb2 =esige*e0/Wdb; //#

Cbb1 =1/(1/ccap +1/Cbb2); //#

//##### Vth for surf & buried channel #####//

Vfb_sige= ‐0.5 *Egsi ‐ phinB_si +delta_Vfb ; //#

VthBB = Vfb_sige + 2*phinB_sige +sqrt(2 * e0 * esige *q*nch* phinsB )/coxpB ;

VthB = VthBB‐ k1buried * Vbs; //#

VthS_thinbodyS = (esi*e0*(phins‐2*phinB_sige)/tcap +phins*cox)/cox ; //#


VthS_thinbody = VthS_thinbodyS ‐ k1surf *Vbs;

VthS_bulk = VthS_thinbody ‐ delta_Vth; //#

Vgssat = VthS_thinbody + fitting2 ; //#

//############## Effective Vgse, Vgst for buried channel ###############//

Vfb = Vfb_sige;

Vbi = Vt * ln(nch * nsd / nisige / nisige);

qbm = ‐1 * sqrt(2 * q * e0 * esige * nch * phinsB);

Vbc = 0.9 * (phinsB ‐ k1 * k1 / 4 / 0.0025);

Vbseff1 = Vbc + 0.5 * (Vbs ‐ Vbc ‐ 0.001 + sqrt(pow((Vbs ‐ Vbc ‐ 0.001), 2) ‐ 0.004 * Vbc));

Vbseff = 0.95 * phinsB ‐ 0.5 * (0.95 * phinsB ‐ Vbseff1 ‐ 0.001 + sqrt(pow((0.95 *

phinsB ‐ Vbseff1 ‐ 0.001), 2)+4*0.001*0.95*phinsB));

Xdep = sqrt(2 * e0 * esige * (phinsB ‐ Vbseff) / q / nch);

lt = sqrt(esige * e0 * Xdep / coxB);

Xdep0 = sqrt(2 * e0 * esige * phinsB / q / nch);

lt0 = sqrt(esige * e0 * Xdep0 / coxB);

Vth0=VthB; //#

Vth=Vth0; //#

n = 1 + nfactor * e0 * esige / Xdep / coxB + (0.5 / (cosh(dvt1 * leff / lt) ‐ 1)) * (cdsc +

cdscd * Vds) / coxB;


Abulk = 1 + k1 / 2 * a0 * (leff / (leff + 2 * sqrt(Xj * Xdep)));

//***** calculate ueff *****//

Vgse = Vfb + phinsB + (q * esige * e0 * ng * pow((tox + dox+ tcapeff), 2)) / (eox * eox

* e0 * e0) * (sqrt(1 + (2 * eox * eox * e0 * e0 * (Vgs ‐ Vfb ‐ phinsB)) / (q * esige * e0 * ng * (tox + dox

+tcapeff) * (tox + dox + tcapeff)))‐1);

Vgst = n * Vt * ln(1 + exp((Vgse ‐ Vth)/(2 * n * Vt))) / (0.5 + n * coxB * sqrt(2 * phinsB

/ (q * nch * esige * e0)) * exp((Vgse ‐ Vth ‐ 2 * voff) / (‐2 * n * Vt)));

ueff = u0 / (1 + ua * ((Vgst + 2 * Vth) / (tox + dox + tcapeff)) + ub * pow(((Vgst + 2 *

Vth) / (tox + dox + tcapeff)), 2));

//##### calculate Vgstsat in terms of Vgssat #####//

Vgsesat = Vfb + phinsB + (q * esige * e0 * ng * pow((tox + dox+ tcapeff), 2)) / (eox *

eox * e0 * e0) * (sqrt(1 + (2 * eox * eox * e0 * e0 * (Vgssat ‐ Vfb ‐ phinsB)) / (q * esige * e0 * ng * (tox +

dox +tcapeff) * (tox + dox + tcapeff)))‐1);

Vgstsat = n * Vt * ln(1 + exp((Vgsesat ‐ Vth)/(2 * n * Vt))) / (0.5 + n * coxB * sqrt(2 *

phinsB / (q * nch * esige * e0)) * exp((Vgsesat ‐ Vth ‐ 2 * voff) / (‐2 * n * Vt)));

//*****calculate vdsat *****//

Esat = 2 * vsat / ueff;

Vdsat = Esat * l * (Vgst + 2 * Vt) / (Abulk * Esat * l + Vgst + 2 * Vt );

//*****calculate vdseff *****//


Vdseff = Vdsat ‐ (Vdsat ‐ Vds ‐ delta + sqrt(pow((Vdsat ‐ Vds ‐ delta), 2) + 4 * delta * Vdsat))

/ 2;

//##### calculate charge #####//

//Xdc = 1.9e‐9 /(1 + pow(((Vgst + 4 * (Vth0 ‐ Vfb ‐ phinsB)) / 2 / (tox + tcapeff)/1e8),

0.7));

//cen = esige * e0/ Xdc;

//coxeff = coxpB * cen / (coxpB + cen);

beta = ueff * coxpB * w / leff;

Qb0= Vgst *beta*leff/(w*ueff);

Qbsat= Vgstsat*(1+abc*Vbs) * beta *leff/(w*ueff);

// Qbsat= Vgstsat * 4E‐3;

Qb_final = Qbsat ‐ 0.5* ( Qbsat ‐ Qb0 ‐fitting +sqrt(pow((Qbsat ‐ Qb0 ‐fitting),2)

+4*fitting* Qbsat) ) ;

beta_final = ueff * Qb_final * w / leff/Vgst ;

//*****calculate Ids_buried *****//

Idso_buried = beta_final * Vgst * (1 ‐ Vdseff / (2 * ((Vgst + 2 * Vt) / Abulk))) * Vdseff / (1 + Vdseff /

(Esat * leff));

Ids_buried = kc * Idso_buried * (1 + (Vds ‐ Vdsat) / VA);


//############### Effective Vgse, Vgst for Surface Channel ################//

VfbS = ‐0.555 ‐ phins / 2;

VbiS = Vt * ln(nch * nsd / ni / ni);

qbmS = ‐1 * sqrt(2 * q * e0 * esi * nch * phins);

VbcS = 0.9 * (phins ‐ k1 * k1 / 4 / 0.0025);

Vbseff1S = VbcS + 0.5 * (Vbs ‐ VbcS ‐ 0.001 + sqrt(pow((Vbs ‐ VbcS ‐ 0.001), 2) ‐ 0.004 *

VbcS));

VbseffS = 0.95 * phins ‐ 0.5 * (0.95 * phins ‐ Vbseff1S ‐ 0.001 +

sqrt(pow((0.95 * phins ‐ Vbseff1S ‐ 0.001), 2)+4*0.001*0.95*phins));

XdepS = sqrt(2 * e0 * esi * (phins ‐ VbseffS) / q / nch);

ltS = sqrt(esi * e0 * XdepS / cox);

Xdep0S = sqrt(2 * e0 * esi * phins / q / nch);

lt0S = sqrt(esi * e0 * Xdep0S / cox);

Vth0S=VthS_thinbody; //#

VthS=Vth0S; //#

nS = n*(1+Cbb1/cox)/(1+Cbb2/coxB) ; //#

AbulkS = 1 + k1 / 2 * a0 * (leff / (leff + 2 * sqrt(Xj * XdepS)));

//# subthreshold behavior


//***** calculate ueff *****//

VgseS = VfbS + phins + (q * esi * e0 * ng * pow((tox + dox), 2)) / (eox * eox *

e0 * e0) * (sqrt(1 + (2 * eox * eox * e0 * e0 * (Vgs ‐ VfbS ‐ phins)) / (q * esi * e0 * ng * (tox + dox) * (tox

+ dox)))‐1);

VgstS = nS * Vt * ln(1 + exp((VgseS ‐ VthS)/(2 * nS * Vt))) / (0.5 + nS * cox *

sqrt(2 * phins / (q * nch * esi * e0)) * exp((VgseS ‐ VthS ‐ 2 * voffS) / (‐2 * nS * Vt)));

ueffS = u0S / (1 + ua * ((VgstS + 2 * VthS) / (tox + dox)) + ub * pow(((VgstS +

2 * VthS) / (tox + dox)), 2));

//##### calculate Vgst_bulk #####//

VgstS_bulk = nS * Vt * ln(1 + exp((VgseS ‐ VthS_bulk)/(2 * nS * Vt))) / (0.5 +

nS * cox * sqrt(2 * phins / (q * nch * esi * e0)) * exp((VgseS ‐ VthS_bulk ‐ 2 * voffS) / (‐2 * nS * Vt)));

//*****calculate vdsat *****//

EsatS = 2 * vsatS / ueffS;

VdsatS = EsatS * l * (VgstS + 2 * Vt) / (AbulkS * EsatS * l + VgstS + 2 * Vt );

//*****calculate vdseff *****//

VdseffS = VdsatS ‐ (VdsatS ‐ Vds ‐ deltaS + sqrt(pow((VdsatS ‐ Vds ‐ deltaS), 2)

+ 4 * deltaS * VdsatS)) / 2;


//##### calculate charge #####//

XdcS = 1.9e‐9 /(1 + pow(((VgstS + 4 * (Vth0S ‐ VfbS ‐ phins)) / 2 / tox/1e8),

0.7));

cenS = esi * e0 / XdcS;

coxeffS = coxp * cenS / (coxp + cenS);

betaS = ueffS * coxeffS * w / leff;

Qs_thinbody= VgstS *betaS*leff/(w*ueffS); //#

Vth0_bulk =VthS_bulk ; //#

XdcS_bulk = 1.9e‐9 /(1 + pow(((VgstS_bulk + 4 * (Vth0_bulk ‐ VfbS ‐ phins)) / 2 / tox/1e8), 0.7));

//#

cenS_bulk = esi * e0 / XdcS_bulk; //#

coxeffS_bulk = coxp * cenS_bulk / (coxp + cenS_bulk);

betaS_bulk = ueffS * coxeffS_bulk * w / leff;

Qs_bulk= VgstS_bulk *betaS_bulk*leff/(w*ueffS) ; //#

Qs_sum = fitting1 *(Qs_thinbody + Qs_bulk);

Qs_final = 0.5*(Qs_sum + Qs_thinbody + sqrt(pow((Qs_thinbody ‐

Qs_sum),2)) ) ;

betaS_final = ueffS * Qs_final * w / leff/Vgst ;

//*****calculate Ids *****//


IdsoS = betaS_final * VgstS * (1 ‐ VdseffS / (2 * ((VgstS + 2 * Vt) / AbulkS))) * VdseffS /

(1 + VdseffS / (EsatS * leff));

IdsS = kc * IdsoS * (1 + (Vds ‐ VdsatS) / VAS);

//###### final current #####//

I(d, s) <+ Ids_buried +IdsS;

end

endmodule

Figure B.1 shows the simulation results for charge distribution in dual channel.

Figure B.1: Charge distribution in dual-channel as a function of gate bias

-2.0 -1.5 -1.0 -0.5 0.0 0.51E-16

1E-14

1E-12

1E-10

1E-8

1E-6

1E-4

0.01

Car

rier

ch

arg

e d

ensi

ty (

cm-2

)

Gate voltage (V)

Buried channel Surface channel

Compact model for dual-channel behavior in a p-type Si/SiGe/Si MOSFET

BIBLIOGRAPHY 147

147

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