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1196 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 4, APRIL 2009

Low-Cost Gate Drive Circuit for Three-LevelNeutral-Point-Clamped Voltage-Source Inverter

Felipe J. C. Padilha, Student Member, IEEE, Walter Issamu Suemitsu, Senior Member, IEEE,Maria Dias Bellar, Member, IEEE, and Plutarcho Maravilha Lourenco

Abstract—This paper presents a new hardware implementationof gate drive circuits applied to low-power neutral-point-clamped(NPC) multilevel three-phase inverters. The proposed circuit isbased on commercially available MOS-gate driver ICs (MGDs)for large-scale applications, which may reduce the total cost ofimplementation of NPC inverters. Only one dc power supply isrequired to feed all the gate drivers for the three-phase system.Detailed design procedures are presented, which include the pro-tection circuits for avoiding hazardous switching states of thepower switches. Experimental results of a laboratory prototypedemonstrate the validity of the proposed circuit. These results alsosuggest that for achieving safe operation of snubberless powerswitches during transients, a hybrid implementation of each NPCphase leg, consisting of MOSFETs with voltage ratings at half thedc bus voltage and of insulated gate bipolar transistors rated atthe total dc bus voltage, is recommended.

Index Terms—Charge pump technique, gate drive circuit,switch-voltage balancing, three-level neutral-point-clamped(NPC) inverter.

I. INTRODUCTION

MULTILEVEL inverters have been considered a high-potential technology for high-power high-voltage ap-

plications, since they can offer some advantages over theirtwo-level pulsewidth modulated counterparts, such as reducedswitch-voltage ratings, reduced switch dv/dt stresses, and out-put voltage waveforms with improved spectra at lower switch-ing frequencies [1]–[3]. In particular, neutral-point-clamped(NPC) inverters have been receiving increased attention re-cently for the integration of renewable energy sources to the

Manuscript received June 16, 2008; revised September 15, 2008. Firstpublished October 31, 2008; current version published April 1, 2009. This workwas supported in part by CNPq and in part by the Electric Power ResearchCenter (CEPEL), Rio de Janeiro, Brazil.

F. J. C. Padilha was with the Electric Power Research Center, Rio de Janeiro21941-911, Brazil. He is now with the Electrical Engineering Department,Escola Politécnica, and the Instituto Alberto Luiz Coimbra de Pós Graduação ePesquisa de Engenharia, Universidade Federal do Rio de Janeiro, Rio de Janeiro21941-901, Brazil (e-mail: [email protected]).

W. I. Suemitsu is with the Electrical Engineering Department, EscolaPolitécnica and the Instituto Alberto Luiz Coimbra de Pós Graduação ePesquisa de Engenharia, Universidade Federal do Rio de Janeiro, Rio de Janeiro21941-901, Brazil (e-mail: [email protected]).

M. D. Bellar is with the Department of Electronics and TelecommunicationsEngineering, State University of Rio de Janeiro, Rio de Janeiro 20550-900,Brazil (e-mail: [email protected]).

P. M. Lourenco is with the Electric Power Research Center, Rio de Janeiro21941-911, Brazil (e-mail: [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TIE.2008.2007554

utility grid [4]–[6] and for low-voltage drives, traction, andutility applications [7], [8]. Thus far, special concerns onthe controls of these inverters have been extensively reported[9]–[14].

Nevertheless, low-voltage applications of three-level NPCinverters are still very restricted, and few works on this topichave been done [7], [8], [15]. Although the use of integratedgate drive circuits [MOS-gate driver ICs (MGDs)] for control-ling two-level inverters are very common, this has not yet beenthe case for multilevel inverters. The development of low-costand reliable gate drive circuits may considerably reduce thetotal cost of implementation of multilevel inverters, and thenmake them a competitive solution in industries. In [7] and [16],gate drive circuit was proposed based on the bootstrap chargepump scheme, which was applied to a three-level NPC three-phase inverter and to one phase leg of an eight-level floatingsource multilevel inverter, respectively. In those works, powerMOSFETs were used, and the gate drivers were composed ofdiscrete components.

This paper is focused on the implementation of thecharge pump technique with commercially available MGDs,generally applied to two-level inverters, for the power switchesof three-level NPC inverters. The proposed gate drive circuitis intended for applications up to a 500-dc-link voltage,making it suitable for a great number of low-voltage industrialapplications where power MOSFETs could be applied. Theimplemented circuit requires only one dc power supply to feedthe whole gate driver for the three-phase system. Moreover, itallows for independent triggering and long conduction time ofthe power switches. These attributes are usually more restrictedin conventional gate drive circuits, based on the chargepump technique, and it may impose some limitations to theinverter performance [17], [18]. In [17], some design consider-ations and preliminary experimental tests for one phase legof the NPC, connected to a dc-link voltage rated at 64 V andwith a resistive load, were presented. In the work developed inthis paper, experimental tests were carried out on a three-phaseNPC inverter at a dc bus voltage equal to 320 V, while feedinga three-phase resistive load and also when it was drivingan unloaded 1-hp/3450-r/min induction motor. During thesetests, the voltage balancing on the power switches was ofa special concern. Special care was taken on implementingprotection circuits in order to avoid switching states whichcould cause damage to the power switches. Moreover, thetotal harmonic distortion (THD%) in the output voltages isshown for verifying the proper operation of the inverter. For

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PADILHA et al.: LOW-COST GATE DRIVE CIRCUIT FOR VOLTAGE-SOURCE INVERTER 1197

Fig. 1. Basic inverter diagram.

completion, the results of the previous work [17] are alsopresented here.

This paper is organized as follows. In Section II, importantdesign issues on gate drive circuits are described, with emphasison the use of integrated circuit devices of type MGD. InSection III, the use of MGDs, applied to NPC inverters, and theproposed gate drive circuits are explained. In Section IV, theexperimental results are shown, and the conclusion is presentedin Section V.

II. CHARGE PUMP TECHNIQUE

A block diagram of an inverter switch, with control andpower stages, is shown in Fig. 1.

Control circuits, protection scheme, the gate drive circuit,and its associated auxiliary power supply are in the con-trol stage, together with the main power supply. The dc bus(VDC+) and power switch are in the power stage. In this work,the auxiliary power supply consists of the bootstrap capacitorvoltages, as it will be shown later in this paper.

The ground connection of power switches depends on theconverter topology and can generally be arranged in two differ-ent ways. One is by connecting the emitter (or source) terminalto the control ground reference. It is of simple triggering, and nospecial procedure is needed. In the other way, when S1 (Fig. 1)is floating, as referenced to the control ground point, an isolated(auxiliary) power supply is required to turn it on. This makes thedesign of the control stage more complex, particularly whenthe power stage has several power switches floating from theground reference. Hence, in this paper, only the second case isconsidered.

The basic function of the gate drive circuit is to properlytrigger the power switches with the use of isolated powersupplies that provide safe operation of the inverters [18]. Thecharge pump is a simple technique of implementing low-costgate drivers and is very popular in industries [19]. In the nextsection, this technique is explained.

A. Typical Charge Pump Circuit

The charge pump technique is based on a charged capacitorthat works as an auxiliary voltage source for switching voltage-controlled power switches, such as MOSFETs and insulated-gate bipolar transistors (IGBTs). The charge pump circuithas a voltage supply V1, a diode D1, and a capacitor C1,as shown in Fig. 2. In this case, the auxiliary voltage sup-

Fig. 2. Simple gate drive circuit using the charge pump technique.

Fig. 3. Typical circuit using MGDs for one phase inverter leg.

ply, which corresponds to the isolated supply, is made upby the capacitor C1. Its working cycle is described as fol-lows [19].

1) The capacitor C1 is charged up to the voltage V1 by thecurrent flowing in the loop containing D1 and the load,while the power switch S1 is opened.

2) A signal is sent to activate the optocoupler OP thatconnects C1 to the switch control terminals, and then, thecapacitor voltage turns S1 on. In this situation, the diodeD1 prevents C1 from discharging through the main powersupply and protects the circuitry that is connected to V1.

The circuit shown in Fig. 2 is very simple but it does notallow long conduction times of the switch, considering that C1will discharge due to leakage currents and S1 bias current. Iflonger turn-on times are desirable, some capacitor rechargingprocedures should be provided [19], [20]. The proposed circuitprovides a way to recharge this capacitor.

A gate drive circuit based on the charge pump operation isintegrated in a simple and low-cost device named MGD, and ithas been used as a good choice to implement power invertersfor industrial applications.

B. MGD Characteristics and Practical Considerations

A typical application using the commercial IR21xx familyis shown in Fig. 3. It shows an easy way to implement ahigh-speed one-phase inverter leg using high- and low-side



drives [19]. The high-side output (HO) is the only one that usesthe charge pump technique. The low-side output (LO) is a high-current ground-connected buffer.

The point connections HO, LO, VB, and VS in Fig. 3correspond to those shown in Fig. 2.

The inverter and gate drive circuit (MGD), as well as thecharge pump components, are usually specified based on thedc bus voltage, maximum output switch current, and switchingfrequency.

Therefore, the following items must be taken into accountduring the components’ selection [19]–[21].

1) MGD: The MGD output sink current greatly influencesthe choice of switching frequency. This characteristic and thedc bus voltage are critical for selecting this component. Com-mercial devices can be found with output current ranging from100 to 2000 mA and voltages from 100 to 1200 V.

2) Diode D1: As mentioned before, when the high-sideswitch is turned on (S1 in Fig. 2 and Q1 in Fig. 3), the diodewill be reverse-biased with a voltage close to the dc bus value.Aside from this, it should have a fast response time to allowfor quick charge changes on C1. Therefore, the diode D1 mustbe carefully chosen. It must be pointed out that in the proposedcircuit, there is no need to use any bootstrap diode.

3) Capacitor C1: A minimum capacitive value must bespecified for the sake of a proper and safe switching proce-dure. On the other hand, large capacitance values may causeproblems to the recharging process. Capacitors of tantalum orpolyester types are commonly preferred.

The minimum capacitance value is given as [19]

C1 = 2

[2Qg + Iqbs(max)

fsw+ Qls

]V1 − VD1

(1)

where fsw is the switching frequency, Qg is the total gate chargeof the high-side switch (typically 20 nC < Qg < 150 nC), Qlsis the shift charge level required per cycle (typically equal to5 nC for 500 V/600 V ICs or 20 nC for 1200 V ICs), VD1is the forward voltage drop across the bootstrap diode, andIqbs is the quiescent current for the high-side driver circuitry(approximately equal to 0.8 mA).

In practical situations, the actual value of C1 must be muchhigher than the one obtained from (1).

III. MGD-BASED GATE DRIVE CIRCUIT

FOR NPC INVERTERS

Fig. 4 shows one phase leg of an NPC, where the neutralpoint N and the MGDs associated with the switches (Q1–Q4)are shown. The NPC operation, as described next, is based on asequence of switching pairs of power switches (Fig. 4). Dead-time intervals are inserted between each changing of switchstate, in order to avoid short circuit in the dc links (CUP,CLOW).

1) Initially, all switches are off.2) Q3–Q4 are then turned on, while the others remain off.3) Q3–Q4 are turned off, dead-time interval is inserted,

Q2–Q3 are turned on, and Q1 remains off.

Fig. 4. NPC inverter leg with the MGDs associated to the power switches.

Fig. 5. Switch Q3 voltage waveform (20 V/div, 20 μs/div).

4) Q2–Q3 are turned off, dead-time interval is inserted,Q1–Q2 are turned on, and Q4 remains off.

5) Q1–Q2 are turned off, dead-time interval is inserted, andQ3–Q4 are turned on.

6) Repeat sequence from step 3).

This sequence repeats continuously throughout the operationof the inverter.

The charging process of the bootstrap capacitors (C1–C3)is accomplished by means of this switching sequence. Thecapacitors C2 and C3 are continuously recharged through V1,and diodes D2 and D3, respectively, when the switches Q3–Q4are on.

In step 3), C1 is being charged by C2 through D1, and instep 4), C1 remains connected to C2.

This circuit has some usage restrictions, namely, the lim-itation of the switches’ conduction time, as mentioned inSection II-A, and unbalanced capacitor (C1–C3) voltageswhich are mostly caused by the voltage drops in the switchesand diodes. These drops may set the switches in their linearoperation region and damage them. Aside from, it is importantto define a switching sequence, as described in steps 1), 2), 3),4), 5), and 6).

The proposed gate drive circuit eliminates the switchingsequence, as previously described, and the bootstrap diodesD1–D3.



Fig. 6. Conventional recharging process of the bootstrap capacitor C3.

A. Verification of the Switch-Voltage Balance

In this section, some preliminary tests are presented with theuse of FLUKE 99 scopemeter series II—50 MHz. Fig. 5 showsthe switch Q3 voltage waveform when the circuit of Fig. 4 wasinitially tested with one phase and a resistive load connectedbetween the dc bus (±64 V) and the output of the inverter. Thiscondition is bound to occur in three-phase applications if thecontrol signals of the other phases are not synchronized.

As it is shown in Fig. 5, an overvoltage occurs on theswitch Q3, which, in this case, is equal to the total dc busvoltage. This should not happen in an NPC inverter.

This problem can be caused by two main factors.

1) When a pair of switches (in this case, Q3 and Q4) is notswitched on at the same time. In this case, an overvoltageproblem can occur, depending on the load configuration.A proper design of the control logic can prevent thisoccurrence.

2) When a bootstrap capacitor is recharged through an inad-equate current path.

Fig. 6 shows case 2), where C3 is recharged through cur-rent icp.

When the switches Q3 and Q4 are turned on, the bootstrapcapacitor C3 is charged by the voltage source V1. When theseswitches are turned off, the voltage drop of the diode D3remains low (as if it is conducting) for a long time, due tothe fact that Q3 and Q4 are in the high-impedance state and,consequently, there is no reverse current in D3. In this situation,according to the voltage Kirchoff law, the voltage across Q4 iszero, and then, the voltage across the switch Q3 will be equalto the dc-link voltage (VDC+).

The proposed circuit (Fig. 9) will be described in the nextsections. It does not use bootstrap diodes, eliminating the pre-viously mentioned second factor of failure, as shown in Fig. 7.It shows that there is no overvoltage in the switches and theirvoltages are equal to half of the VDC+.

B. Protection Circuits

In order to avoid hazardous switching states, some protec-tion procedures were included in the proposed circuit. Specialswitching states are required for preventing the total (VDC+)or partial dc-link voltage from short-circuiting. Moreover, theswitching sequences of switch pairs must be synchronized, and

Fig. 7. Switch-voltage waveforms with the proposed gate drive (20 V/div and20 μs/div). (a) Switch Q1. (b) Switch Q2. (c) Switch Q3. (d) Switch Q4.

TABLE ISWITCHING SEQUENCE FOR THREE-LEVEL NPC INVERTER

dead-time condition must be inserted as well. In Table I, thepermissible switching conditions are shown, where it can beseen that three states cause short circuit.

Fig. 8 shows the schematic diagram of the protection circuits.There is a logic circuit that prevents invalid switching states atQ1–Q4, based on Table I. In case that it happens in the controlinputs g1–g4, the inverter is disabled. Adjustable dead-timecircuit, start-up reset, and shut down by external command arealso included.

C. Proposed Gate Drive Circuit for Three-LevelNPC Inverters

The purpose of this section is to present a way of keepingthe bootstrap capacitors charged in the NPC topology and ofeliminating the limitations of the circuit in Fig. 4. Fig. 9 showsthe schematic diagram of the proposed gate drive circuit for onephase leg.



Fig. 8. Protection circuits.

Fig. 9. Proposed gate drive for the NPC inverter.

A single dc power supply set to 15 V (main power supply inFig. 1) is used to feed the MGDs and the protection circuits. Thebootstrap capacitors C1–C3 (auxiliary power supply in Fig. 1)are charged by the dc bus VDC+, via an external refresh circuitnamed charge control, associated with three current sources I1,I2, and I3. With this method, it is possible to keep each switch

turned on for long time intervals and to keep the bootstrapcapacitor voltages controlled and stable.

Moreover, each pair of power switches can be enabled in-dependently, which avoids the need of predefined switchingsteps 1), 2), 3), 4), 5), and 6) [7].

The charge control circuit is shown in more detail in Fig. 10.It can be implemented basically with an oscillator and a low-power voltage doubler rectifier. The current source and theZener diode help to produce a low ripple in the power-supplycircuit. The current sources can be implemented with the useof simple components, such as resistors, Zener diodes, and/ortransistors.

Fig. 11 shows a scheme presenting the energy balance of agate drive circuit using MGDs with a charge pump technique.The total power loss that occurs during the switch turn-on isdirectly affected by the switching frequency, and it is namedGP in Fig. 11.

The power lost in the MGD, caused by internal bias current,was named Bp. The external refresh circuit that keeps thebootstrap capacitor charged, as shown in Fig. 10, must be ableto transfer the total power (Paux), as follows:

Paux ≥ (Bp + Gp) (2)



Fig. 10. Charge control circuit.

Fig. 11. Energy balance of the gate drive.

where (2) can be written as

Paux ≥ (VC1 ∗ Iqbs + fsw ∗ VC1 ∗ Qg) (3)

where VC1 is the voltage in capacitor C1 and Iqbs and Qg areas described in (1).

By using (2) and (3), the minimum value of the currentsources (I1, I2, and I3) can be calculated so that the automaticrecharge process works properly, and that means keeping all thebootstrap capacitors charged continuously. The current sourcescan be calculated with

I ≥(

VC1∗Iqbs + f ∗swVC1∗Qg

Vz − VD4 − VD5

)+ Iqos (4)

whereIqos quiescent current for the oscillator;Vz Zener voltage used to supply the oscillator;VD4 and VD5 forward voltage drops in the diodes D4 and

D5, respectively.The specification of the oscillator capacitance CP1 (Fig. 11)

is defined as

(VCP1∗f ∗oscQCP1) ≥ Paux (5)

Fig. 12. Three-phase prototype.

where fosc is the oscillator switching frequency and QCP1 isthe charge level in CP1. The left-hand side in (5) means themaximum (theoretical) power transfer of the charge controlcircuit (Fig. 11).

By considering the approximations

VCP1 ≈VC1 (6)

(Vz − VD4 − VD5) ≈VC1 (7)

a final result can be written as

CP1 ≥(

Iqbs + f ∗swQg

VC1∗fosc

). (8)

Since there is no refresh circuit associated with the currentsource I1, this current source can be set to a value lower thanthe one defined by (4).

The current sources play an important role for balancing theswitch voltages.

D. Switch-Voltage Balancing

It is desirable that each power switch handles as low voltageas possible during OFF-state. In the proposed circuit, the speci-fication of the current sources I1, I2, and I3 (Fig. 9) influencesthe switch blocking voltage and their balancing. These currentsources force the diodes DA and DB to conduct in the propertime, which helps the balancing process of the switch voltages.In addition to this, the voltages of capacitors CUP and CLOWmust be controlled so that the neutral point is maintained aroundhalf of the dc bus voltage.

If the switches Q3 and Q4 are turned on (Fig. 9), the currentsource I3 will prompt the diode DA to conduct, and then, thetotal dc bus will be equally divided among Q1 and Q2. A similarsituation happens when the switches Q1 and Q2 are turned on.In this case, the current source I1 will force the diode DB toconduct, and the other switches will have their share of the totaldc bus.



Fig. 13. Switching sequence of square-wave control applied to the NPC inverter.

Fig. 14. (a) Line-to-line voltage at 220 V · r/min (100 V/div, 4 ms/div). (b) THD% in the NPC output line-to-line voltages.

The diodes DA and DB will assure that when Q2 andQ3 are turned on, the output voltage of the inverter will beequal to half of the dc-link voltage, which implies that theswitches Q1 and Q4 will also be at half of the dc voltagevalue.

When all switches are turned off, as it is the case duringdead-time intervals, both current sources I1 and I3 will workas described before.

It must be pointed out that at any switch state, the currentsources operate independently, which implies that the refresh



circuits also operate continuously. Then, all the bootstrap ca-pacitors are always kept charged.

IV. EXPERIMENTAL RESULTS

A. Experimental Setup

With the purpose of verifying the performance of the pro-posed circuit, a prototype was implemented based Fig. 9 andtested under several conditions. The NPC inverter was imple-mented, with IGBTs of type IRG4BC20KD, and connected toa dc-link voltage rated initially at ±160 V, with a split powersupply (VDC + = 320 V).

In the gate drive circuit, MGDs of type IC IR2110 were usedto trigger switches Q3 an Q4 and two IR2117 to trigger Q1and Q2. The capacitors’ calculation was based on (1) and (8),resulting in C1 = C2 = C3 = 1 μF and CP1 = 220 nF. TheZener diode (VZ1) ratings are 18 V/1 W; the diodes DA andDB are of type BYT79-500, while D4, D5, and D6 are of typeBA159 and the voltage supply V1 is set to 15 Vdc.

The oscillator frequency of the charge control circuit was setto 4.3 kHz, and its Zener diode rates are 18 V/1 W. The currentsource values are obtained from (4) and are equal to 3 mA.

Fig. 12 shows the complete prototype of the NPC inverterfeeding a three-phase resistive load.

All of the experimental results presented here were obtainedwith a switching control of a square-wave type. It consists ofa 12-pulse sequence based on the switching sequence as pre-sented in Table I. Fig. 13 shows one switching sequence appliedto each phase leg that produces output voltages at 60 Hz.

These switching sequences must follow this pattern, no mat-ter what the choice of the modulation technique is [14]. Fig. 13also shows the dead-time interval between each switchingchange.

Experimental results of the three-phase system are presentedin the next figures, with the inverter connected to a three-phaseresistive load, with the use of Tektronix TDS 3034B.

The line voltage is a 12-step waveform with a maximumamplitude equal to (2/3)VDC+, while the line-to-line voltageis a six-step waveform, with its maximum at VDC+(total dcbus voltage), as shown in Fig. 14.

The THD% of the line-to-line voltages are similar to the linevoltages. Fig. 14(b) shows the experimental Fourier spectrumof the line-to-line voltage of Fig. 14(a).

B. Operation While Driving an Induction Motor

In this section, the experimental results are shown, when thedc bus voltage VDC+ is set to 320 V and the inverter is drivingan unloaded induction motor rated at 1 hp/3450 r/min.

Fig. 15 shows the line voltages and the switch-voltage wave-forms of one phase leg. In Fig. 15(a) and (b), voltage spikesoccur, which did not appear during the tests with the resistiveload [Figs. 7 and 14(a)].

Fig. 15(b) shows that very short duration overvoltages hap-pen only on the intermediate switches (Q2 and Q3). This resultsuggests that these switches must be rated at VDC+ and top andbottom switches (Q1 and Q4) can be rated at half of VDC+.Consequently, Q1 and Q4 can be built of power MOSFETs,while IGBTs are recommended for Q2 and Q3. The use of

Fig. 15. (a) Line voltages (200 V/div, 4 ms/div). (b) Switch-voltage wave-forms of one phase leg, with VDC + = 320 V (Ch1 = VQ1, Ch2 = VQ2,Ch3 = VQ3, Ch4 = VQ4).

power MOSFETs can significantly reduce power loss and costsfor low-power applications.

V. CONCLUSION

This paper presented a new hardware implementation of abootstrap charge-pump-technique-based gate drive circuit ap-plied to a three-level NPC inverter for low-power applications.The design equations and the considerations on the choice ofcomponents were experimentally verified. The main advantagesare as follows: the use of commercially available MGDs, withthe benefit of low power consumption; the use of a single lowpower supply for the whole three-phase system gate driver andthe protection circuits; and safe operation of power switcheswith long turn-on time intervals. However, the results suggestthat a hybrid implementation of each phase leg, consisting ofMOSFETs with voltage ratings at half of the dc bus voltageand of IGBTs rated at the total dc bus voltage, is recommendedfor achieving safe operation during transients and for reducedpower losses and costs.



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[19] “Application Note AN978,” HV Floating MOS-Gate Driver ICs. [Online].Available: http://www.irf.com/technical-info/appnotes/an-978.pdf

[20] “Design Tips DT 94-1A,” Keeping the Bootstrap Capacitor Chargedin Buck Converters. [Online]. Available: http://www.irf.com/technical-info/designtp/dt94-1.pdf

[21] “Design Tips DT 98-2A,” Bootstrap Component Selection forControl. [Online]. Available: http://www.irf.com/technical-info/designtp/dt98-2.pdf

Felipe J. C. Padilha (S’06) received the B.Sc. de-gree in electrical engineering from the State Univer-sity of Rio de Janeiro (UERJ), Rio de Janeiro, Brazil,in 2003, and the M.Sc. degree from the InstitutoAlberto Luiz Coimbra de Pós Graduação e Pesquisade Engenharia (COPPE), Universidade Federal doRio de Janeiro (UFRJ), Rio de Janeiro, in 2006,where he is currently working toward the Ph.D.degree.

In 2005, he was an Assistant Professor with theDepartment of Mathematics, UERJ/Resende. He is

currently a Teaching Assistant with the Electrical Engineering Department,Escola Politécnica, UFRJ. His research interests include gate drive circuits,power inverters, dc–dc converters, and renewable energy systems, principallyphotovoltaic applications.

Walter Issamu Suemitsu (S’72–M’75–SM’81) re-ceived the B.Sc. degree in electrical engineeringfrom the Escola Politécnica da Universidade deSão Paulo, São Paulo, Brazil, in 1975, the M.Sc.degree in electrical engineering from InstitutoAlberto Luiz Coimbra de Pós Graduação e Pesquisade Engenharia (COPPE), Universidade Federal doRio de Janeiro (UFRJ), Rio de Janeiro, Brazil, in1979, and the Dr.Ing. degree in electrical engi-neering from the Institut National Polytechnique deGrenoble, Grenoble, France, in 1986. He did his

Postdoctoral Research at Laval University, Québec City, QC, Canada, from1991 to 1993.

Since 1977, he has been teaching and developing researches with the Elec-trical Engineering Department, Escola Politécnica, UFRJ, where, since 1986,he has also been an Associate Professor with COPPE, the engineering graduateschool; currently, he is the Dean of the UFRJ Technology Center. His researchinterests include electrical machine drives and applications of power electronicconverters on electrical drives and in renewable energy systems.

Maria Dias Bellar (S’90–M’01) was born in Riode Janeiro, Brazil. She received the B.Sc. degreein electronics engineering and the M.Sc. degree inelectrical engineering from Universidade Federal doRio de Janeiro, Rio de Janeiro, in 1986 and 1989,respectively, and the Ph.D. degree from Texas A&MUniversity, College Station, in 2000.

Since 1990, she has been with the Departmentof Electronics and Telecommunications Engineering,State University of Rio de Janeiro, Rio de Janeiro,where, since 2001, she has been an Associate Pro-

fessor. Her current research interests include converters with high power factor,converters for photovoltaic power systems, and motor drives.

Dr. Bellar was the Chair of the IEEE Rio de Janeiro Power ElectronicsSociety/Industry Applications Society/Industrial Electronics Society jointchapter, from 2004 to 2005.

Plutarcho Maravilha Lourenco received the B.Sc.degree in electronic engineering from the Escola deEngenharia, Universidade Federal do Rio de Janeiro,Rio de Janeiro, Brazil, in 1975, the M.Sc. degreein electrical engineering from the Instituto AlbertoLuiz Coimbra de Pós Graduação e Pesquisa deEngenharia, Universidade Federal do Rio de Janeiro,in 1978, and the D.Sc. degree in electrical engineer-ing from the Pontificia Universidade Catolica do Riode Janeiro, Rio de Janeiro, in 1998.

Since 1978, he has been with the Electric PowerResearch Center, Rio de Janeiro, as a Researcher, where he develops andimplements electronic instrumentation applied to electric power systems andelectric load forecast models. His research interests include signal process-ing; electronic instrumentation; digital control; analysis and forecast of timeseries; robotics; and applications of statistical and computational intelligencetechniques to forecast, processing, control, and instrumentation systems.


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