logic gates ic details

8/3/2019 Logic Gates IC Details

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Examples of SSI chip pin layouts

7400 7404

7408 7411

7422 7430

7432 7486


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A circuit for the majority function of three variables

A chip representation of the majority function

A

B

C

A A'

B C'B' C

ABC

A'BC

..

. .

.

..

AB'C

A'BC+AB'C

.

.ABC'

ABC+ABC'

Output

AB'C


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Design levels for digital computers:

- systems level

- interfacing the components

- CPU chips

- memory chips

- I/O chips

- digital logic level

- designing the chips

- using logic gates

- device level

- designing the logic gates

- using transistors

Digital Logic Level:

- combinational circuits

- the input determines the output

- if the input changes, the output changes

- the system does not have to remember the current state

- sequential circuits

- the output depends on:

- the input

- the current state

- the sequence is synchronized by a clock

- timing determines when a change in input will produce a change in output


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Combinational circuits:

- have multiple inputs

- have multiple outputs

- implemented in MSI chips

- typical combinational circuits include:

- binary adders

- comparators

- decoders

- encoders

- multiplexers

- demultiplexers

- shifters

Multiplexer (MUX)

- selects 1 of its (multiple) input lines and sends it to its one output line- has more than 1 input, but only 1 output

- the control line determines which input line is selected

- as a block diagram:

data line 0

data line 1output line X

control line A


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2-to-1 multiplexer:

As a logic diagram:

Corresponds to:

If A = 0Output D0

Else

Output D1

A 4-input (or 4-to-1) multiplexer (block diagram):

Each AND gate has 3 inputs:

1 data line

2 control lines

The control lines determine which

AND gate can output a 1


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A 4-input (or 4-to-1) multiplexer:

An eight-input multiplexer circuit


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Demultiplexer:

- the reverse of a multiplexer

- has 1 input signal- has n control lines and 2n output lines

- e.g. a 2-bit demultiplexer

- value of its 1 input line is sent to 1 of the 4 output lines

- depending on the value of its 2 control lines

D0

D1

D2

D3

input

C1 C0

Decoder:

- takes an n-bit number as input

- has 2n output lines (1 for each combination of the n bits)

- one of the 2n output lines is set to 1

- the other output lines are 0

A 2-to-4 decoder

Truth table:

Input Output

A B D0 D1 D2 D30 0 1 0 0 0

0 1 0 1 0 0

1 0 0 0 1 0

1 1 0 0 0 1


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A 3-to-8 decoder circuit

A 1-bit left/right shifter

Shifter:

- shifts the n-bit input one bit to the right or left

- has n input lines and n output lines

- has 1 control line to determine direction of shift

- 0 = left, 1 = right


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Code converters:

- translate input word into a corresponding new code word

- number of input lines may differ from number of output lines

Problem:

- design a BCD-to-some-other-code converter

- using dont care conditions, given the following truth table

Inputs (BCD) Outputs (some other code)

A B C D W X Y Z

0 0 0 0 0 0 0 0 0

1 0 0 0 1 0 0 0 1

2 0 0 1 0 0 0 1 0

3 0 0 1 1 0 0 1 1

4 0 1 0 0 0 1 0 0

5 0 1 0 1 1 0 1 1

6 0 1 1 0 1 1 0 0

7 0 1 1 1 1 1 0 1

8 1 0 0 0 1 1 1 0

9 1 0 0 1 1 1 1 1

- must build a k-map for each of the output lines

- using the values of ABCD when the output line is 1

- can use the dont care conditions to group


A B C D W X Y Z

0 0 0 0 0 0 0 0 0

1 0 0 0 1 0 0 0 1

2 0 0 1 0 0 0 1 0

3 0 0 1 1 0 0 1 1

4 0 1 0 0 0 1 0 0

5 0 1 0 1 1 0 1 16 0 1 1 0 1 1 0 0

7 0 1 1 1 1 1 0 1

8 1 0 0 0 1 1 1 0

9 1 0 0 1 1 1 1 1

AB

CD

X

AB

CD

Code converter - continued

X =

W =

X

X

X

X

X

X

X

X

X

X

X

1

11

1

1

1

1

1

1

1

A + BD + BC

A + BC + BD'

00

00

01 11 10

01

11

10

00

00

01 11 10

01

11

10


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AB

CD

AB

CD


A B C D W X Y Z

0 0 0 0 0 0 0 0 0

1 0 0 0 1 0 0 0 1

2 0 0 1 0 0 0 1 0

3 0 0 1 1 0 0 1 1

4 0 1 0 0 0 1 0 0

5 0 1 0 1 1 0 1 1

6 0 1 1 0 1 1 0 0

7 0 1 1 1 1 1 0 1

8 1 0 0 0 1 1 1 0

9 1 0 0 1 1 1 1 1

Code converter - continued

Z =

Y =

X

X

X

X

X

X

X

X

X

X

X

X

1

11

1

1

11

1

1

1

A + B'C + BCD

D

00

00

01 11 10

01

11

10

00

00

01 11 10

01

11

10

Code converter - continued W = A + BC + BD

X = A + BC + BD'

- the logic diagram: Y = A + B'C + BC'DZ = D


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A simple 2-bit comparator

Comparator:

- compares 2 n-bit data words

- output will be 1 if the words are equal, 0 if they are not

- compares matching bits from 2 words

- first: xor the matching bits

- returns 0 if they are equal, 1 if not

- then: results from n bits are output to a nor gate

- if each pair was 0 (matching), final result is 1

A simple 4-bit comparator


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-Comparator can also check for > and B:

A = 11 and B = 10 or 01 or 00

A = 10 and B = 01 or 00

A = 01 and B = 00

or

1110

1101

1100

1001

1000

0100

A1A0

B1B000

00

01 11 10

01

11

10

1 1 1

1 1

1

A1B'1

A1A0B'0

A0B'1B'0

2-bit comparator for A = B and A > B


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Addition:

- the most common arithmetic operation performed by a digital computer

- if the hardware can add two binary numbers

- the other three primitive arithmetic operations

- subtraction, multiplication and division

- can be performed with the addition hardware

- subtraction is performed using two's complement arithmetic

- multiplication can be done using repeated addition (or shifting and

adding)

- division can be done using repeated subtraction

- addition is implemented by using two different types of adder circuits

- a half-adder

- to add 2 bits

-a full adder

- to add 3 bits

- 2 bits and a carry

Half-adder:

- adds 2 1-bit numbers

- the sum and carry are generated

A0+ B0

C0 S0

block diagram:

bits to

be added

sum

carry


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The half-adder:

Sum Carrya b s c

0 0 0 0

0 1 1 0 Sum : s = a'b + ab' = a xor b

1 0 1 0

1 1 0 1 Carry: c = ab

Alternate diagram for Half-Adder


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Full adder:

- to add 2 2-bit numbers A1

A0

- the sum and carry are generated for the least significant digit + B1 B0

- but

- all subsequent bits need to have the carry bit added in

- needs to add 3 bits

- so full adder adds 3 bits and generates a sum and a carry

- made up of 2 half-adders

block diagram:

bits to

be added

sum

carry

Full adder - continued:

- usually the full adder circuit uses 2 half-adders and an OR gate

- first half adder adds A and B (a bit from each number)

- second half adder adds the sum from the first half-adder and the carry in

- if either half adder has a carry, it is sent to carry out

First: A plus B:


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Then the second half-adder:

- (The sum of A plus B) plus (the carry in)

The full adder:

Carry Sum Carry

In Out

a b c s cout0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1 Sum: s = a'b'c + a'bc' + ab'c' + abc1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1 Carry: cout = a'bc + ab'c + abc' + abc

How the formula is derived:


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The full adder:

Carry Sum Carry

In Out

a b c s cout0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1 Sum: s = a'b'c + a'bc' + ab'c' + abc

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1 Carry: cout = a'bc + ab'c + abc' + abc

Carry = a'bc + ab'c + abc' + abc

= a'bc + ab'c + ab(c' + c)

= (a'b + ab')c + ab(1)

= (a xor b)c + ab

or ab + bc + ac

ab

cin1

1

1

abcin

1

11 1

1

11

00

0

01 11 10

1

00

0

01 11 10

1

S um = a'b'c + a 'bc' + a b' c' + abc ( can reorder)

= a'b'c + abc + a'bc' + ab'c (can factor out c and c)

= (a'b' + ab)c + (a'b + ab')c (this is a xor b)

(and this is a xnor b)

= (a'b' + ab)''c + (a'b + ab')c

= [(a'b')'(ab)']'c + (a'b + ab')c

= [(a'' + b'')(a' + b')]'c + (a'b + ab')c

= [(a + b)(a' + b')]'c + (a'b + ab')c

= (aa' + ab' + ba' + bb')'c + (a'b + ab')c

= (0 + ab' + ba' + 0)'c + (a'b + ab')c

= (ab' + ba')'c + (a'b +ab')c

= (a'b + ab')'c + (a'b + ab')c

= (a xor b)'c + (a xor b)c

= (a xor b) xor c


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XOR: AB + AB

XNOR: AB + AB (the 2 cases that are not the XOR)

So . . . C (AB + AB) + C (AB + AB)

is the same as

C (A xnor B) + C (A xor B)

which is the same as

C (A xor B) + C (A xor B)

which is the equivalent of XY + XY or X xor Y

and . . . C (A xor B) + C (A xor B)

becomes C xor (A xor B)

Alternate diagram for Full Adder


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Circuit design for a 4-bit adder - parallel binary adder (or ripple-carry adder)

b2b3 b1 b0

c3

a0a1a2a3

s0s1s2s3

c0c1c2

A 1-bit ALU

Data bus:

Decoder:(to choose

function)

F0 F1 function

0 0 ab

0 1 a+b

1 0 b

1 1 a plus b

ab

a+b

b

enable lines

enable line for adder -anded with the result from the xor gates (sum)

and with the gates computing the carry out

output may be from

any of the functions


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Sequential circuits:

- combinational circuits combined with memory

- output depends on both input and the current state of the circuit

- timing determines when a change in input will produce a change in output

- controlled by the clock

- use gates and memory elements called flip-flops

- this circuit will hold and store its value

The latch:

- adds a feedback loop

- the output of each gate feeds into the input of another gate

- is the basis for computer memory

A latch:

- a circuit that will hold and store its values

- adds a feedback loop to a circuit

- output of each gate feeds back to the input of a previous gate

- a D-latch: (data latch)

- has 2 outputs

- the complement of the

true output

- the true output


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- if D = 1

- output of gate #1 will be 0 (Q')

- inputs to gate #2 will both be 0- Q will be 1 and stay 1

- so the latch is set to 1

gate #1

gate #2

- if D = 0

- the reverse process occurs

- Q will be 0- and the latch is reset to 0

Positive Clock Pulses

logical 0

logical 1

Clock cycle


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a clocked D-latch

- to prevent the latch from changing its state until we want it to change

- adds a clock and 2 and gates

- the clock enables the and gates

- the inputs are now D and the clock

- the outputs are still Q and Q'

gate #1

gate #2

- the clock is normally 0

- keeps input to the NOR gates 0 (no matter what the value of D)

- so the latch does not change state

- when the clock is 1:

- the latch is enabled

- it responds to the value of D

- input to gate 2 is always the complement of D

gate #1

gate #2


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- if the clock = 0 the latch is stable

- it remembers its previous state

- to load the current value of D into the circuit (into memory)

- a positive pulse is put on the clock line

Clocked D-latch

Truth table:

Clk D Q Q

1 0 0 1

1 1 1 0

0 X Q Q

Positive Clock Pulses

logical 0

logical 1

Rising edgeof pulse

(Leading edge)

Falling edgeof pulse

(Trailing edge)

Clock cycle


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D-latch:

D flip-flop:

d

ck

q d

d d

ck

ck ck

q

q q

State changes on high voltage

(level is 1)State changes on low voltage

(level is 0)

Flip-flop on the leading edge Flip-flop on the falling edge

Logic diagram for

a 4 x 3 memory

Each row is one

3-bit word.

A read or write

operation reads or

writes a complete

word.

Data bus

Data bus

Decoder

Control

lines


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Logic diagram for

a 4 x 3 memory

Each row is one

3-bit word.

A read or write

operation reads or

writes a complete

word.

Data bus

Data bus

Decoder

Control

lines

3-bit memory

(3 flip-flops)

selects word

(address bus)

Chooses read or

write operation

(control bus)

only used for a

write operation

only used for a

read operation

the non-inverting buffer:

- has a data input and a control input

- has 1 data output

- can act like an open circuit

- if control signal is high

- buffer acts like a conducting wire

- if control signal is low- buffer acts like an open circuit

data in

control in

data out

detail from memory diagram:


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- the memory circuit

- the CS line must be asserted

- it is anded with the inverted RD line into the write gate

- it is anded with the RD line and the OE line to become a control line for the outputs

- the address lines input to a decoder

- selects one line that enables one of the memory words

- for a READ operation:

- the control lines are set to 111

- CS, RD and OE are asserted

- the input lines are not used

- the address lines are set to the word to be read

- the word is placed on the data output lines

- Q is anded with the word select line

- the result is the input to an OR gate

- the output becomes the input to a non-inverting buffer

If:

CS = 1

RD = 1

OE = 1

If:

A1 = 0

A0 = 1

If:

Word 1 = 101

logic gates ic details

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