Microsoft PowerPoint - Chapter02.ppt3
–using truth tables
–using electronic circuits.
(binary). • Boolean operatorsinclude
AND, OR, and NOT.
Truth Table Representation
• Defines the output of a function for every possible combination of inputs.
• A system with n inputs has 2n possible combinations.
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• Gates can be represented by schematic symbols.
• Symbols can be either distinctive-shape or rectangular-outline.
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• Uses different graphic representations for different logic functionsAND, OR, NOT.
• Uses a bubble (a small circle) to indicate a logical inversion.
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Rectangular-Outline Schematic Symbols
• All functions are shown in rectangular form with the logic function indicated by standard notation inside the rectangle.
• The notation specifying the logic function is called the qualifying symbol.
• Inversion is indicated by a 1/2 arrowhead.
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NOT Function
• One input and one output. • The output is the opposite logic level of
the input or we can say that the output is the complement of the input.
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NOT Function Boolean Representation
• Inversion is indicated by a bar over the signal to be inverted.
A Y =
• Distinctive-shape symbol is a triangle with inversion bubble.
• Rectangular-shape symbol uses “1” and the inversion 1/2 arrowhead.
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AND Function
• Two or more inputs, one output. • Output is HIGH only when all of the
inputs are HIGH. • Output is LOW whenever any input is
LOW.
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AND Function
ABY B AY
• Called an AND gate for short. • Distinctive-shape symbol uses AND
designation. • Rectangular-shape symbol use “&” as
designator.
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OR Function
• Two or more inputs, one output. • Output is HIGH whenever one or more
input is HIGH. • Output is LOW only when all of the
inputs are LOW.
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• Called an OR gate for short. • Distinctive-shape symbol uses OR
designation. • Rectangular-shape symbol uses “≥” as
designator.
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• When a logic HIGH is “ON”, the signal is active-HIGH.
• When a logic LOW is “ON”, the signal is active-LOW.
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• Output is HIGH whenever any input is LOW.
• Output is LOW only when all inputs are HIGH.
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BAY •=
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NAND Function Electronic Circuit
• Called a NAND gate. • Uses the AND symbol with inversion on
the output.
• Outputs is LOW whenever any input is HIGH.
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011
001
010
B A Y +=
NOR Function Electronic Circuit
• Called a NOR gate. • Uses OR symbol with inversion on the
output.
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• 3 Input NAND:
• 3 Input NOR:
0110 0001 0101 0011
3 Input NOR and NAND Function Truth Tables
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Exclusive OR Gate
• Two inputs, one output. • Output is HIGH when one, and only one,
input is HIGH. • Output is LOW when both inputs are
equal – both HIGH or both LOW.
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Exclusive NOR Gate
• Two inputs, one output. • Output is HIGH when both inputs are
equal – both HIGH or both LOW. • Output is LOW when one, and only one,
input is HIGH, i.e., the two inputs are different.
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Gate Equivalence – NAND
• A NAND gate can be represented by an AND gate with inverted output.
• A NAND gate can be represented by an OR gate with inverted inputs.
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Gate Equivalence – NOR
• A NOR gate can be represented by an OR gate with inverted output.
• A NOR gate can be represented by an AND gate with inverted inputs.
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C
D
A
Gate Equivalence – DeMorgan Forms
• Change an AND function to an OR function and an OR function to an AND function.
• Invert the inputs. • Invert the outputs.
B
A
/B
/A
B
/A
A
/B
U14A
14011
1
–
–
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DeMorgan’s Theorem - 2
• The following are two common errors associated with DeMorgan’s Theorem:
•
Active Logic Levels
• Any INPUT or OUTPUT that has a BUBBLE is considered as active LOW.
• Any INPUT or OUTPUT that has no BUBBLE is considered as active HIGH.
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output LOW. • • All inputs LOW make the output HIGH.
BA Y +=
• Provides a logic HIGH or LOW depending on switch position.
• Commonly used types include normally- open pushbutton, normally-closed pushbutton, single-pole single-throw, and single-pole double-throw.
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Two-Pole Push Button
• Two-pole push button allows for normally HIGH and normally LOW levels from the same switch.
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• Used to indicate the status of a digital output.
• Has two terminals, i.e., the anode and the cathode.
• If the anode is approximately 1.5 V greater than the cathode, current flows and the LED illuminates.
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A C/K
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• Used to provide a visual indication of a logic state.
• Can be wired to display active-HIGH or active-LOW.
• What’s the common rated current flow through the diode? – About 10mA
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Logic Gate Enable
• The input to a gate that allows the output to respond to other inputs.
• A logic LOW for an OR or NOR gate, a logic HIGH for an AND or NAND gate.
• Somewhat like a controlled switch.
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VCC
R26 10K
R21 2K
R23 1M
Control Input
DIP14 DIP14 May be replaced by 3904. E B C 1 2 3
Logic Gate Enable
Logic Gate Inhibit
• The input to a gate that forces the output to ignore any other input.
• A logic HIGH for an OR or NOR gate, a logic LOW for an AND or NAND gate.
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BY=
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Logic Gate Inhibit Note: P.51 Textbook Error (Typo); Forgot to add a inverter in the output terminal
BY=
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• Three output states, HIGH, LOW and high-impedance.
• Requires a separate input to control which output state is selected.
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Tristate Buffer Utilization
• Used to connect multiple outputs together –A design that requires highly attention! .
• Used in controlling the operation of buses. –
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• Contains two groups of four non- inverting tri-state buffers.
• Each group is controlled by a separate enable input, i.e., .G
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• Integrated Circuits (ICs) contain many components in a single package.
• Several packaging options are available. • One common package is called Dual-In-
line Package (DIP).
• The other common form is Complementary Metal-Oxide Semiconductor, called CMOS.
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Advanced BiCMOS (TTL/CMOS hybrid)74ABT00
Integrated Circuit Technology
Integrated Circuit Designation
• Standard form is 74XXFF, where 74 is the logic family identifier, XX is the logic family member and FF identifies the specific logic function.
• SN74ALS00N
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IC Package Options
• PLCC - plastic lead chip carrier • SOIC - small outline integrated circuit • TSSOP – thin shrink small outline
package • QFP – quad flat pack • DIP – dual inline package • BGA – ball grid array
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PLCC 84 Pin Packages • Can be mounted on the surface of a
circuit board or mounted in a socket. • Pins are equally distributed on four sides. • Pin 1 placed on the center of one of the
rows, as indicated by a dot. • Pins number counterclockwise from this
point. 90