logic design - kthlogic design review slides david broman associate professor, kth royal institute...
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Logic Design
Review Slides
David Broman Associate Professor, KTH Royal Institute of Technology
Assistant Research Engineer, University of California, Berkeley
IS1200, spring 2015
Slides version 1.0
Part I Numbers, Gates, and Combinational Logic Design
Part II Sequential Logic Design
David Broman [email protected]
2
Agenda
Part II
Sequential Logic Design Part I
Numbers, Gates, and Combinational Logic Design
Part I Numbers, Gates, and Combinational Logic Design
Part II Sequential Logic Design
David Broman [email protected]
3
Part I
Numbers, Gates, and Combinational Logic Design
Part I Numbers, Gates, and Combinational Logic Design
Part II Sequential Logic Design
David Broman [email protected]
4
Number Systems (1/3) Decimal and Binary Numbers
How can we represent numbers?
Decimal Numbers
1,2,3,…,8,9,10,11,…,73,…,101,…
The base is 10. 37510 = 3×102 + 7×101 + 5×100
Binary Numbers
0,1 A binary value is called a bit. This is what a computer system is using.
011012 = 0×24 + 1×23 + 1×22 + 0×21 + 1×20 =
What is the number in decimal form?
1310
E
Often, 1= true and 0 = false
Part I Numbers, Gates, and Combinational Logic Design
Part II Sequential Logic Design
David Broman [email protected]
5
Number Systems (2/3) Bytes, Nibbles, Words, MSB, LSB, …
It’s quite tedious to work with only binary numbers…
10100001000001011110101101001101 Therefore, bits are grouped into bytes, each consisting of 8 bits.
Microprocessors use data in the size of words. A 32-bit processor has 32-bit words, a 64-bit processor has 64-bit words.
1010 0001 0000 0101 1110 1011 0100 1101
4 bits (half a byte) is called a nibble.
In a group of bits, the least significant bit (lsb) is to the right. The most significant bit (msb) is to the left.
lsb 32-bit word
msb MSB LSB
Within a word, the terms are the most significant byte (MSB) and the least significant byte (LSB).
Part I Numbers, Gates, and Combinational Logic Design
Part II Sequential Logic Design
David Broman [email protected]
6
Number Systems (3/3) Hexadecimal Numbers
Problem: Nibbles cannot be identified directly in the byte.
1010 0001 0000 0101 1110 1011 0100 1101
A byte can hold 256 different values
16110
Are decimal numbers a good way to represent:
510 23510 Bytes? 7710
Nibbles? 1010 110 010 510 1410 1110 410 1310
Hexadecimal Numbers
The base is 16. Always two digits for each byte.
One digit = one nibble.
A1
A105EB4D16
0,1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F, 10, 11,…, 19, 1A, 1B,...
Coined at IBM in 1963. From Greek hexi (six) and Latin decem (ten). Source: Harris and Harris, 2013.
05 EB 4D
Part I Numbers, Gates, and Combinational Logic Design
Part II Sequential Logic Design
David Broman [email protected]
7
Logic Gates (1/3) AND, OR, NOT, and BUF
AND OR
NOT BUF
A 0 0 1 1
B 0 1 0 1
Y 00 0 1
B
AY
A 0 0 1 1
B 0 1 0 1
Y 01 1 1
A Y
B
AY
A YA 0 1
Y 10
A 0 1
Y 01
The small circle (called a bubble) inverse the signal.
NOT is also called an inverter.
Looks like not, but has no circle. Buffer. Logically the same as a wire. Relevant from an analog point of view.
Part I Numbers, Gates, and Combinational Logic Design
Part II Sequential Logic Design
David Broman [email protected]
8
Logic Gates (2/3) NAND, NOR, XOR, and XNOR
XOR XNOR
E
A 0 0 1 1
B 0 1 0 1
Y NAND
B
AY NOR
A 0 0 1 1
B 0 1 0 1
Y
B
AY
A 0 0 1 1
B 0 1 0 1
Y A 0 0 1 1
B 0 1 0 1
Y
NOT AND. Note the Small bubble at the end.
Exclusive OR, pronounced “ex-or”.
NOT OR.
H
B
AY
Exclusive NOT OR.
B
AY
11 1 0
10 0 0
01 1 0
1 00 1
Part I Numbers, Gates, and Combinational Logic Design
Part II Sequential Logic Design
David Broman [email protected]
9
Logic Gates (3/3) Multi-Input Logic Gates
XOR3
NOR5
AND3
Gates can be generalized to have more than two inputs. For instance:
AND gate with 3 inputs.
NOT OR gate with 5 inputs.
Exclusive OR gate with 3 inputs.
A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
Y C 0 1 0 1 0 1 0 1
An N-input XOR gate is also called a parity gate. It outputs 1 when odd number of inputs are 1.
ABC
Y
0 1 1 0 1 0 0 1
Part I Numbers, Gates, and Combinational Logic Design
Part II Sequential Logic Design
David Broman [email protected]
10
Combinational Circuit
This circuit is combinational because its outputs depend only on its inputs. The circuit is memoryless, that is, it has no memory.
E
A = 1
Y
B = 0
C = 1
1 0 1 1
=1 0 1
1
A = 0
Y
B = 1
C = 1
0 1 0
1 =1
1 1
0
We will introduce memory in Lecture 2
Observe that this (rather useless) circuit always outputs 1. As a logic formula, this is called a tautology.
H
Part I Numbers, Gates, and Combinational Logic Design
Part II Sequential Logic Design
David Broman [email protected]
11
Boolean Algebra (1/4) Truth Tables and Sum-of-Products Form
We can create a boolean expression from the truth table A
0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
Y 0 0 1 0 0 1 1 0
C 0 1 0 1 0 1 0 1
A truth table with random output (we have seen them before).
ABC + ABC + ABC
The line over a variable is called the complement and is the inverse of the variable (NOT). Sometimes a prime ‘ is used instead.
The AND of one or more variables is called a product.
AND can be written using “no space” or using a dot, e.g. A!B!C
OR is written using the + symbol.
This form is called sum-of-products (surprise!)
Part I Numbers, Gates, and Combinational Logic Design
Part II Sequential Logic Design
David Broman [email protected]
12
Boolean Algebra (2/4) Some Theorems
A!1 = A A+0 = A Identity A!0 = 0 Null Element
A!A = A
A+1 = 1
A+A =A Idempotency
A = A Involution A!A = 0 A+A = 1 Complements
A!B = B!A A+B = B+A Commutativity
E H
(A!B)!C = A!(B!C)
(A+B)+C = A+(B+C) Associativity
(A!B)+(A!C)= A!(B+C)
(A+B)!(A+C)= A+(B!C)
Distributivity
Theorem Dual Name Exercise: Derive the simplest form of expression
BA + AB + A
BA + AB + A
= AB + AB + A
= A(B+B) + A
= A!1 + A
= A + A
= A
Commutativity
Distributivity
Complements (dual)
Identity
Indempotency (dual)
Solution:
Note! Not as traditional algebra
Part I Numbers, Gates, and Combinational Logic Design
Part II Sequential Logic Design
David Broman [email protected]
13
Boolean Algebra (3/4) De Morgan’s Theorem
A1 ! A2 ! A3 … =
(A1 + A2 + A3 …)
Theorem Dual A1 + A2 + A3 … =
(A1 ! A2 ! A3 …)
B
AY
Important law. For CMOS (Complementary metal–oxide–semiconductor), NAND and NOR gates are preferred over AND and OR gates.
The law shows that these gates are equivalent
But how can we know that this theorem is true?
B
AY=
AB = A + B = Y
B
AY
B
AY=
A+B = A B = Y
Augustus De Morgan British mathematician and logician (1806 – 1871).
Part I Numbers, Gates, and Combinational Logic Design
Part II Sequential Logic Design
David Broman [email protected]
14
Boolean Algebra (4/4) Proof by Perfect Induction
A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
ABC 1 1 1 1 1 1 1 0
C 0 1 0 1 0 1 0 1
Perfect Induction = Proof by Exhaustion = Proof by Cases
Proof by perfect induction. Exhaustively show all cases in a truth table.
Prove the De Morgan’s Theorem for three variables
ABC = A + B + C A + B + C
1 1 1 1 1 1 1 0
Note that these two columns are equal
Part I Numbers, Gates, and Combinational Logic Design
Part II Sequential Logic Design
David Broman [email protected]
15
Combinational Blocks (1/3)
E
Multiplexers
S 0 0 0 0 1 1 1 1
D1 0 0 1 1 0 0 1 1
Y 0 1 0 1 0 0 1 1
D0 0 1 0 1 0 1 0 1
What is this?
0
1
S
D0
D1
It’s a 2:1 Multiplexer.
2 bits for the data input 1 output
The control signal S selects which input bit that is sent to the output.
S
D0
D1
One possible implementation. Convince yourself of its correctness!
Y
Y
Part I Numbers, Gates, and Combinational Logic Design
Part II Sequential Logic Design
David Broman [email protected]
16
Combinational Blocks (2/3) Multiplexers
E
00 01 10 11
S1 S0
Y
A multiplexer can be seen as a simple switch, selecting which signal that should pass through the block.
Y
4:1 multiplexer (4 inputs, 1 output).
D0 D1 D2 D3
What is the output signal Y for the 4:1 multiplexer with these inputs?
D0 = 1, D1 = 0, D2=1, D3=0, S1 = 1, S0 = 0
D0 D1 D2 D3
A 4:1 multiplexer can be defined hierarchically.
0
1 D0
D1
Y
0
1
S0
0
1
D2
D3
S1
S0
Answer: Y = 1
S1 S0
Part I Numbers, Gates, and Combinational Logic Design
Part II Sequential Logic Design
David Broman [email protected]
17
Combinational Blocks (3/3) Decoders
Decoder 00 01 10 11
A decoder has N inputs and 2N outputs. Asserts exactly one output.
Y0
A1 A0 Y1
Y2 Y3
2:4 decoder (2 inputs, 4 output).
A1 0 0 1 1
Y3 0 0 0 1
A0 0 1 0 1
Y2 0 0 1 0
Y1 0 1 0 0
Y0 1 0 0 0
Note that only one signal is 1 on each row. This is called one-hot.
Part I Numbers, Gates, and Combinational Logic Design
Part II Sequential Logic Design
David Broman [email protected]
18
Arithmetic Circuits and Numbers (1/7) Half and Full Adders
A half adder has a carry out signal.
Idea: Chain adders together…
Cout +
A B
S
A full adder has both carry out and carry in signals.
+
A B
Cout
S
Cin
A
0 0 1 1
B
0 1 0 1
S
0 1 1 0
Cout
0 0 0 1
How can we add bigger numbers?
A
0 0 1 1 0 0 1 1
B
0 1 0 1 0 1 0 1
S
0 1 1 0
Cout
0 0 0 1
Cin
0 0 0 0 1 1 1 1
E H
1 0 0 1
0 1 1 1
Exercise: Complete the truth table
Part I Numbers, Gates, and Combinational Logic Design
Part II Sequential Logic Design
David Broman [email protected]
19
Arithmetic Circuits and Numbers (2/7) Carry Propagate Adders
An N-bit carry propagate adder (CPA) sums two N-bit inputs.
+
A B
Cout
S
Cin
N N
N
Note the notation for a N-bit bus.
Three common implementations of CPAs are:
• Ripple-carry adder Simple but slow.
• Carry-lookahead adder Faster, divides into blocks.
• Prefix adder Even faster. Used in modern computers.
See course book (advanced part)
32-bit ripple-carry adder
+
A31
Cout C30
B31
S31
+
A30
C29
B30
S30
+
A1
C0
B1
S1
+
A0
Cin
B0
S0
C1
Part I Numbers, Gates, and Combinational Logic Design
Part II Sequential Logic Design
David Broman [email protected]
20
Arithmetic Circuits and Numbers (3/7) Negative Numbers, Sign/Magnitude
http://www.publicdomainpictures.net/view-image.php?image=93652&picture=negativ-film
How can we represent negative numbers?
Idea: Let msb represent the sign (1 = negative, 0 = positive) and the remaining bits the magnitude. This representation is called signed/magnitude numbers.
-610 + 710 = 110 = 000012
5 bits signed/magnitude numbers
-610 = 101102
710 = 001112
-710 = 101112
Can we add two numbers using binary addition?
610 = 001102
101102 + 001112 = 111012 = -1310
Should be
but…
Problem 1: Binary addition does not work…
000002 = +010 100002 = -010 and Problem 2: Strange effect; we have two numbers for zero...
Part I Numbers, Gates, and Combinational Logic Design
Part II Sequential Logic Design
David Broman [email protected]
21
Arithmetic Circuits and Numbers (4/7) Negative Numbers, Two’s Complement
Solution: Two’s complement numbers Which patterns can we find in the following 3-bit two’s complement numbers.
Only one number represent 0 (Solution to problem 1) 0002 = 010
0012 = 110 0102 = 210 0112 = 310
1002 = -410 1012 = -310 1102 = -210 1112 = -110
Positive numbers are represented as usual.
All negative numbers have msb set. This is called the sign bit.
Can represent one more negative number than positive numbers.
Negative numbers are listed in reverse order.
Part I Numbers, Gates, and Combinational Logic Design
Part II Sequential Logic Design
David Broman [email protected]
22
Arithmetic Circuits and Numbers (5/7) Negative Numbers, Two’s Complement
Why is it called two’s complement? 0002 = 010 0012 = 110 0102 = 210 0112 = 310
1002 = -410 1012 = -310 1102 = -210 1112 = -110
Because the negation of an N-bit value X is 2N – X.
Example: N = 3 and X = 3. Then 23 – 3 = 8 – 3 = 5 = 1012
Is binary addition working with two’s complement numbers?
5 bits two’s complement numbers (check yourself)
-610 = 110102
710 = 001112
-710 = 110012
610 = 001102
-610 + 710 = 110 = 000012
110102 + 001112 = 000012
Should be
Yes, it works (general proof left as an exercise). Note that the carry out is 1, but ignored here.
Part I Numbers, Gates, and Combinational Logic Design
Part II Sequential Logic Design
David Broman [email protected]
23
Arithmetic Circuits and Numbers (6/7) Negative Numbers, Two’s Complement
0002 = 010 0012 = 110 0102 = 210 0112 = 310
1002 = -410 1012 = -310 1102 = -210 1112 = -110
But, in this case we need a subtract operator to get negative numbers (we have an adder)…
Another way to take the two’s complement of a number X with N bits: • Invert all bit of number X and add 1.
Example: N = 3 and X = 3. X = 3 = 0112 inv(X) = 1002, 1002 + 0012 = 1012 (general proof omitted)
Part I Numbers, Gates, and Combinational Logic Design
Part II Sequential Logic Design
David Broman [email protected]
24
Arithmetic Circuits and Numbers (7/7) Subtract
Subtract is simple to implemented with a carry propagate adder (CPA): Invert input signal B and set Cin = 1.
+
A
B
Cout
S
Cin
N N
N
= 1
Note that setting carry in to 1 adds 1 to A + B.
We can easily create a circuit where S = 0 results in A + B and S = 1 results in A - B
0
1
S
B
+
A
Cout
S
N
N
N
N
Part I Numbers, Gates, and Combinational Logic Design
Part II Sequential Logic Design
David Broman [email protected]
25
Part II
Sequential Logic Design
Acknowledgement: The structure and several of the good examples are derived from the book “Digital Design and Computer Architecture” (2013) by D. M. Harris and S. L. Harris.
Part I Numbers, Gates, and Combinational Logic Design
Part II Sequential Logic Design
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Combinational vs. Sequential Logic
Circuit with memory
Sequential Logic Design (this lecture) • Depends on both current and prior input values. • As a consequence, sequential logic has memory. • Today, we will learn about:
Circuit without memory
Combinational Logic Design (previous lecture) • Output depends only on the input. • There is no memory.
B
A00 01 10 11
S1 S0
YD0 D1 D2 D3 + Cout Cin
N N
N
Latches Flip-Flips Registers
We will discuss other kinds of memories in course module 4: Memory hierarchy.
Part I Numbers, Gates, and Combinational Logic Design
Part II Sequential Logic Design
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Q Q
Q
Q
What is the difference between these two circuits?
Answer: None, but both circuits contain a cycle.
E
What is the value of Q?
Analysis by considering two cases:
Case I: Q = 0
Q
QCase II: Q = 1
1
1 0
0
Both cases are stable. The circuit is bistable.
Q
Q0
0 1
1 This circuit has 2 stable states. Hence, it is a memory that can store 1 bit of information.
Problem: We cannot decide what to store (there is no input)
Notation convention: T-connections connect, four way connections do not.
Bistability
Part I Numbers, Gates, and Combinational Logic Design
Part II Sequential Logic Design
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SR Latch
Q
QR
S
R
S Q
QS
0 0 1 1
R
0 1 0 1
Q
Q
Qpre
Qpre 0
1 0
1 0 0
What is the behavior of this circuit? Analyze the 4 cases for inputs S and R.
If S and R are zero, the circuit “remembers” the previous Q value, called Qpre. We have a memory…
Problem 1. The awkward case S=1, R=1 results in that both Q and Q are zero.
An SR latch can be implemented using different gates. This is the abstract symbol for an SR latch.
S is the SET signal and R is the RESET signal.
Problem 2. Mixes the issues of what and when updates are made. It is hard to design large circuits this way.
E
Part I Numbers, Gates, and Combinational Logic Design
Part II Sequential Logic Design
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D Latch
CLK
DQ
QR
S Q
Q
D
CLK
Q
Q
CLK
0 1 1
D
? 0 1
Q
Q
Qpre
Qpre 0
1 1 0
The D latch solves the problems with the SR latch. It has one data input D, and a clock input CLK.
The symbol ? means “don’t care”. It is used to simplify truth tables (we can skip one row in this case). Sometimes a symbol X or D is used to describe “don’t care”.
Symbol describing a D latch:
Also called a transparent latch or level-sensitive latch.
• CLK = 1, the latch is transparent (D flows through to Q).
• CLK = 0, the latch is opaque (the latch blocks data from flowing through).
E
Part I Numbers, Gates, and Combinational Logic Design
Part II Sequential Logic Design
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30
D Flip-Flop A flip-flop is edge-triggered and not level-triggered.
DQ
Q
CLK
D
Q
Q
CLK
D
Q
QDin Qout
CLK
master slave
Case I: CLK = 0 The master is transparent and the slave is opaque. Din flows to N.
Qout
N
Case II: CLK = 1 The slave is transparent and the master is opaque. N flows to Qout.
The D flip-flop (the standard flip-flop) copies D to Q on the rising edge, and remembers its state all other times.
These symbols describe D Flip-Flops. Condensed symbol
Part I Numbers, Gates, and Combinational Logic Design
Part II Sequential Logic Design
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31
Resettable and Enabled Flip-Flops
EN
D Q D Q0
1
EN CLK
D Q
An enabled flip-flop has an input EN. Its state changes only when EN = 1 and there is a raising clock edge (Called WR in the exercise).
RESET
D QD Q Q
DRESET
CLK
A resettable flip-flop resets the flip-flop to 0 when a reset signal is active.
The line above the signal name shows that the reset signal is active low: The reset is active on 0.
True or False physical Q/A “This resettable flip-flop is synchronously resettable, meaning that it resets on a rising clock edge. It is is not asynchronously resettable where the reset is independent of the clock.”
E
Answer: True
Part I Numbers, Gates, and Combinational Logic Design
Part II Sequential Logic Design
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Register An N-bit register consists of N flip-flops that share the same clock input.
CLK
D3:0 Q3:0 4 4
4-bit register built out of D flip-flops (using condensed symbol notation).
Abstract form of a 4-bit register.
Note that registers can also have enable signals, reset signals etc.
CLK
D3
D2
D1
D0
Q3
Q2
Q1
Q0
Part I Numbers, Gates, and Combinational Logic Design
Part II Sequential Logic Design
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Problematic Circuits
What is the value of Q?
Answer: it oscillates. This circuit is called a ring oscillator.
Q
Unstable circuit.
Illegal value (X)
A = 0
B = 1 Q
What is the value of Q?
Answer: Q = X, called an unknown or illegal value. For example, when a wire is driven to both 0 and 1 at the same time. This situation is called contention.
E
Part I Numbers, Gates, and Combinational Logic Design
Part II Sequential Logic Design
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Floating Values and Tristate Buffers
A Y
EE 0 0 1 1
A 0 1 0 1
Y ZZ 0 1
A tristate (or three-state) buffer has high impedance if the output enable signal E is not active.
Commonly used in buses when connecting multiple chips. If the buffers are not enabled at the same time, contention is avoided.
When the enable signal is not active, the output is said to be floating (using symbol Z).
Part I Numbers, Gates, and Combinational Logic Design
Part II Sequential Logic Design
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Output Enable Register
Exercise: Create a 2-bit register that has an output enable (OE) input signal. If OE = 0 then Q is floating, else it outputs the registers’ state.
CLK
D1
D0
Q1
Q0
OE
OE
D Q
E
Part I Numbers, Gates, and Combinational Logic Design
Part II Sequential Logic Design
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Register File (1/2)
CLK
A1 RD1
A2 N
NA3
NWD3
M
MRD2
M
WE3
A register file can be used to read and write data using an address.
This is a multi-ported register file. Two read ports and one write port. Reads and writes can be done in parallel.
Reading M bits from read data port RD1 is done by giving an N-bit read address to A1. Same for the second read port (RD2 and A2).
Writing M bits is done by giving write data to WD3, write address to A3, and setting write enable WE3 to 1.
Part I Numbers, Gates, and Combinational Logic Design
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Register File (2/2)
RD1
Example: Register file with address depth N = 2 (4 different addresses) and 8-bit words (M = 8).
00 01 10 11
8
A2
RD2 00 01 10 11
8
A1
Decoder 00 01 10 11
A3 2
WD3
8
8
8
8
CLK
EN
EN
EN
EN
WE3 Can also be implemented using tristate buffers (see exercises).
8
8
8
8
Part I Numbers, Gates, and Combinational Logic Design
Part II Sequential Logic Design
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Register-Transfer Level - Synchronous Sequential Circuits
It is hard to analyze large asynchronous circuits that contain cycles. Solution: Design synchronous sequential circuits, also called designing at the register-transfer level (RTL), which means that • combinational logic is combined with registers • states are only updated on clock edges
Which of the following circuits are using RTL design / sequential synchronous logic?
E
Yes, with no feedback
Combinational Logic Circuit
CLK
No, because of latch.
Combinational Logic Circuit
CLK
No, has a cycle without register in the path
Combinational Logic Circuit
Part I Numbers, Gates, and Combinational Logic Design
Part II Sequential Logic Design
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Finite State Machines (FSMs) Synchronous Sequential Logics can be defined as FSMs
Next State Logic
E
Moore Machine (M inputs, N outputs, k states)
Output Logic
next state k
CLK
state k outputs
N M inputs
Mealy Machine (M inputs, N outputs, k states)
Next State Logic
next state
CLK
Output Logic state
outputs
M k k N inputs
Outputs can be directly dependent on the inputs
Part I Numbers, Gates, and Combinational Logic Design
Part II Sequential Logic Design
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40
A Simple Mealy Machine Example
Next State Logic
next state
CLK
Output Logic state
outputs
M k k N inputs
EN
A
BC
QDY
CLK clock init 1st 2nd 3rd
A 1 1 1 0
Q 1
B 1 1 0 0
C 0 1 0 1
D Y
0 1 1
0 1 0 1
1 1 1 0
After 1st, 2nd etc. positive clock edge.
Part I Numbers, Gates, and Combinational Logic Design
Part II Sequential Logic Design
David Broman [email protected]
41
Edge-Triggered Timing Methodology How fast can we run a circuit?
Next State Logic
next state
CLK
Output Logic state
outputs
M k k N inputs
The clock period must be longer than the worst-case of delays in the circuit.
The worst-case delay is computed for the feedback loop through the next state logic.
delay = tprop + tcombinational + tsetup + tskew
A race may occur when the values of state elements depend on the relative speed of logic elements in the circuit.
Time to propagate through the flip-flop or register.
The longest delay in the combinational logic.
Necessary time before the rising clock edge.
Compensate for clock skew: clock signals reach state elements at different time.
Part I Numbers, Gates, and Combinational Logic Design
Part II Sequential Logic Design
David Broman [email protected]
42
Summary
Thanks for listening!
Some key take away points:
• Combinational Logic vs. Sequential Logic: Combinational logic has no memory, whereas sequential logic includes memory.
• Synchronous vs. Asynchronous Logic Design Synchronous Design makes design work easier.
• Mealy vs. Moore Machines Both are finite state machines (FSMs). Moore machines depend only on the state, whereas Mealy machines depend on the state and the input.
• Latches vs. Flip-Flops vs. Registers vs. Register File Flip-flops are edge triggered, registers combine flip-flops, and register files uses addresses to access data.