LM4549BSNAS598B –JULY 2012–REVISED JULY 2015 www.ti.com

Table of Contents8.3 Feature Description................................................. 141 Features .................................................................. 18.4 Device Functional Modes........................................ 162 Applications ........................................................... 18.5 Programming........................................................... 173 Description ............................................................. 18.6 Register Maps ......................................................... 264 Revision History..................................................... 2

9 Application and Implementation ........................ 325 Description (continued)......................................... 39.1 Application Information............................................ 326 Pin Configuration and Functions ......................... 49.2 Typical Application ................................................. 327 Specifications......................................................... 8 9.3 System Example ..................................................... 34

7.1 Absolute Maximum Ratings ...................................... 8 10 Power Supply Recommendations ..................... 357.2 ESD Ratings.............................................................. 811 Layout................................................................... 357.3 Recommended Operating Conditions....................... 8

11.1 Layout Guidelines ................................................. 357.4 Thermal Information .................................................. 912 Device and Documentation Support ................. 367.5 Electrical Characteristics .......................................... 9

12.1 Community Resources.......................................... 367.6 Timing Requirements .............................................. 1012.2 Trademarks ........................................................... 367.7 Typical Characteristics ............................................ 1312.3 Electrostatic Discharge Caution............................ 368 Detailed Description ............................................ 1412.4 Glossary ................................................................ 368.1 Overview ................................................................. 14

13 Mechanical, Packaging, and Orderable8.2 Functional Block Diagram ....................................... 14Information ........................................................... 36

4 Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (May 2013) to Revision B Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device FunctionalModes, Application and Implementation section, Power Supply Recommendations section, Layout section, Deviceand Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1

Changes from Original (May 2013) to Revision A Page

• Changed layout of National Data Sheet to TI format ........................................................................................................... 17

2 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated

Product Folder Links: LM4549B


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LM4549Bwww.ti.com SNAS598B –JULY 2012–REVISED JULY 2015

5 Description (continued)The LM4549B features the ability to connect several codecs together using the Extended AC Link configurationof one dedicated serial data signal to the Controller per codec. LM4549B systems support up to 8 simultaneouschannels of streaming data on Input Frames (Codec to Controller) while Output Frames (Controller to Codec)carry 2 streams to multiple codecs. The LM4549B may also be used in systems with the Texas InstrumentsLM4550B to support up to 6 simultaneous channels of streaming data on Output Frames.

The AC '97 architecture separates the analog and digital functions of the PC audio system allowing both forsystem design flexibility and increased performance.

Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 3



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DVDD1

XTL_OUT

SDATA_OUT

48

1

47 46

2

3

4

5

XTL_IN

DVSS1

NC

EAPD

ID1#

45

ID0#

6

7

8

9

10

11

12

LM4549B$&µ97 Rev 2.1

Codec

36

35

34

33

32

31

30

29

28

27

26

25

BIT_CLK

SDATA_IN

SYNC

RESET#

PC_BEEP

DVDD2

DVSS2

LINE_OUT_R

3DP

NC

LINE_OUT_L

3DN

NC

NC

AVSS

NC

VREF

VREF_OUT

AVDD

44

NC

43

NC

42

NC

41

LNLVL_OUT_R

40

NC

39

LNLVL_OUT_L

38

NC

37

MONO_OUT

PHONE

AUX_L

AUX_R

VIDEO_L

VIDEO_R

CD_L

CD_GND

CD_R

MIC1

MIC2

LINE_IN_L

LINE_IN_R

13 14 15 16 17 18 19 20 21 22 23 24


6 Pin Configuration and Functions

PT Package48-Pin LQFP

Top View

Pin FunctionsPIN

I/O DESCRIPTIONNAME NO.

Left Stereo Channel InputThis line level input (1 Vrms nominal) is selectable at the left channel of the stereo Record SelectMux for conversion by the left channel ADC. It can also be mixed into the left channel of the Stereo

AUX_L 14 I Mix 3D signal at MIX1 under the control of the Aux Volume register, 16h. The AUX_L level can bemuted (along with AUX_R) or adjusted from +12 dB to -34.5 dB in 1.5 -dB steps. Stereo Mix 3D iscombined into the Stereo Mix signal at MIX2 for access to the stereo outputs Line Out and LineLevel Out.Right Stereo Channel InputThis line level input (1 Vrms nominal) is selectable at the right channel of the stereo Record SelectMux for conversion by the right channel ADC. It can also be mixed into the right channel of the

AUX_R 15 I Stereo Mix 3D signal at MIX1 under the control of the Aux Volume register, 16h. The AUX_R levelcan be muted (along with AUX_L) or adjusted from +12 dB to -34.5 dB in 1.5-dB steps. Stereo Mix3D is combined into the Stereo Mix signal at MIX2 for access to the stereo outputs Line Out andLine Level Out.AC Ground ReferenceThis input is the reference for the signals on both CD_L and CD_R. CD_GND is not a DC groundand should be AC-coupled to the stereo source ground common to both CD_L and CD_R. The

CD_GND 19 I three inputs, CD_GND, CD_L and CD_R act together as a quasi-differential stereo input withCD_GND providing AC common-mode feedback to reject ground noise. This can improve the inputSNR for a stereo source with a good common ground but precision resistors may be needed in anyexternal attenuators to achieve the necessary balance between the two channels.Left Stereo Channel InputThis line level input (1 Vrms nominal) is selectable at the left channel of the stereo Input Mux forconversion by the left channel ADC. It can also be mixed into the left channel of the Stereo Mix 3DCD_L 18 I signal at MIX1 under the control of the CD Volume register, 12h. The CD_L level can be muted(along with CD_R) or adjusted from +12 dB to -34.5 dB in 1.5-dB steps. Stereo Mix 3D is mixed intothe Stereo Mix signal at MIX2 for access to the stereo outputs Line Out and Line Level Out.Right Stereo Channel InputThis line level input (1 Vrms nominal) is selectable at the right channel of the stereo Input Mux forconversion by the right channel ADC. It can also be mixed into the right channel of the Stereo MixCD_R 20 I 3D signal at MIX1 under the control of the CD Volume register, 12h. The CD_R level can be muted(along with CD_L) or adjusted from +12 dB to -34.5 dB in 1.5-dB steps. Stereo Mix 3D is combinedinto the Stereo Mix signal at MIX2 for access to the stereo outputs Line Out and Line Level Out.




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Pin Functions (continued)PIN


Left Stereo Channel InputThis line level input (1 Vrms nominal) is selectable at the left channel of the stereo Record SelectMux for conversion by the left channel ADC. It can also be mixed into the left channel of the Stereo

LINE_IN_L 23 I Mix 3D signal at MIX1 under the control of the Line In Volume register, 10h. The LINE_IN_L levelcan be muted (along with LINE_IN_R) or adjusted from +12 dB to -34.5 dB in 1.5-dB steps. StereoMix 3D is combined into the Stereo Mix signal at MIX2 for access to the stereo outputs Line Outand Line Level Out.Right Stereo Channel InputThis line level input (1 Vrms nominal) is selectable at the right channel of the stereo Input Mux forconversion by the right channel ADC. It can also be mixed into the right channel of the Stereo Mix

LINE_IN_R 24 I 3D signal at MIX1 under the control of the Line In Volume register, 10h. The LINE_IN_R level canbe muted (along with LINE_IN_L) or adjusted from +12 dB to -34.5 dB in 1.5 dB steps. Stereo Mix3D is combined into the Stereo Mix signal at MIX2 for access to the stereo outputs Line Out andLine Level Out.Left Stereo Channel OutputThis line level output (1 Vrms nominal) is fed from the left channel of the Stereo Mix signal fromLINE_OUT_L 35 O MIX2 via the Master Volume register, 02h. The LINE_OUT_L amplitude can be muted (along withLINE_OUT_R) or adjusted from 0 dB to -46.5 dB in 1.5-dB steps.Right Stereo Channel OutputThis line level output (1 Vrms nominal) is fed from the right channel of the Stereo Mix signal fromLINE_OUT_R 36 O MIX2 via the Master Volume register, 02h. The LINE_OUT_R amplitude can be muted (along withLINE_OUT_L) or adjusted from 0 dB to -46.5 dB in 1.5-dB steps.Left Stereo Channel OutputThis line level output (1 Vrms nominal) is fed from the left channel of the Stereo Mix signal fromLNLVL_OUT_L 39 O MIX2 via the Line Level Volume register, 04h. The LNLVL_OUT_L amplitude can be muted (alongwith LNLVL_OUT_R) or adjusted from 0 dB to - 46.5 dB in 1.5-dB stepsRight Stereo Channel OutputThis line level output (1 Vrms nominal) is fed from the right channel of the Stereo Mix signal fromLNLVL_OUT_R 41 O MIX2 via the Line Level Volume register, 04h. The LNLVL_OUT_R amplitude can be muted (alongwith LNLVL_OUT_L) or adjusted from 0 dB to - 46.5 dB in 1.5-dB stepsMono microphone inputEither MIC1 or MIC2 can be muxed to a programmable boost amplifier with selection by the MS bit(bit D8) in the General Purpose register, 20h. The boost amplifier gain (0 dB or 20 dB) is set by the20dB bit (D6) in the Mic Volume register, 0Eh. Nominal input levels at the two gain settings are 1Vrms and 0.1 Vrms respectively. The amplifier output is selectable (Record Select register, 1Ah) by

MIC1 21 I either the right or left channels of the Record Select Mux for conversion on either or both channelsof the stereo ADCs. The amplifier output can also be accessed at the stereo mixer MIX1 (mutingand mixing adjustments via Mic Volume register, 0Eh) where it is mixed equally into both left andright channels of Stereo Mix 3D for access to the stereo outputs Line Out and Line Level Out.Access to the Mono analog output is selected by a mux controlled by the MIX bit (D9) in GeneralPurpose register, 20h.Mono microphone inputEither MIC1 or MIC2 can be muxed to a programmable boost amplifier with selection by the MS bit(bit D8) in the General Purpose register, 20h. The boost amplifier gain (0 dB or 20 dB) is set by the20dB bit (D6) in the Mic Volume register, 0Eh. Nominal input levels at the two gain settings are 1Vrms and 0.1 Vrms respectively. The amplifier output is selectable (Record Select register, 1Ah) by

MIC2 22 I either the right or left channels of the Record Select Mux for conversion on either or both channelsof the stereo ADCs. The amplifier output can also be accessed at the stereo mixer MIX1 (mutingand mixing adjustments via Mic Volume register, 0Eh) where it is mixed equally into both left andright channels of Stereo Mix 3D for access to the stereo outputs Line Out and Line Level Out.Access to the Mono analog output is selected by a mux controlled by the MIX bit (D9) in GeneralPurpose register, 20h.Mono OutputThis mono line level output (1 Vrms nominal) is fed from either a microphone input (MIC1 or MIC2,after boost amplifier) or from the mono sum of the left and right Stereo Mix 3D channels from MIX1.

MONO_OUT 37 O The optional TI 3D Sound enhancement can be disabled (default) by the 3D bit (bit D13) in theGeneral Purpose register, 20h. Choice of input is by the MIX bit (D9) in the same register. MIX=0selects a microphone input. Output level can be muted or adjusted from 0 dB to -46.5 dB in 1.5-dBsteps through the Mono Volume register, 06h.




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Mono InputThis line level (1 Vrms nominal) mono input is mixed equally into both channels of the Stereo Mixsignal at MIX2 under the control of the PC_Beep Volume control register, 0Ah. The PC_BEEP levelcan be muted or adjusted from 0 dB to -45 dB in 3 dB steps. The Stereo Mix signal feeds both the

PC_BEEP 12 I Line Out and Line Level Out analog outputs and is also selectable at the Record Select Mux.During Initialization or Cold Reset, (reset pin held active low), PC_BEEP is switched directly to bothchannels of the Line Out stereo output, bypassing all volume controls. This allows signals such asPC power-on self-test tones to be heard through the audio system of the PC before the codecregisters are configured.Mono InputThis line level (1 Vrms nominal) mono input is selectable at the Record Select Mux for conversionby either channel of the stereo ADC. It can also be mixed equally into both channels of the StereoPHONE 13 I Mix signal at MIX2 under the control of the Phone Volume register, 0Ch. The PHONE level can bemuted or adjusted from +12 dB to -34.5 dB in 1.5-dB steps. The Stereo Mix signal feeds both theLine Out and Line Level Out analog stereo outputs and is also selectable at the Record Select Mux.Left Stereo Channel InputThis line level input (1 Vrms nominal) is selectable at the left channel of the stereo Record SelectMux for conversion by the left channel ADC. It can also be mixed into the left channel of the Stereo

VIDEO_L 16 I Mix 3D signal at MIX1 under the control of the Video Volume register, 14h. The VIDEO_L level canbe muted (along with VIDEO_R) or adjusted from +12 dB to -34.5 dB in 1.5-dB steps. Stereo Mix3D is combined into the Stereo Mix signal at MIX2 for access to the stereo outputs Line Out andLine Level Out.Right Stereo Channel InputThis line level input (1 Vrms nominal) is selectable at the right channel of the stereo Record SelectMux for conversion by the right channel ADC. It can also be mixed into the right channel of the

VIDEO_R 17 I Stereo Mix 3D signal at MIX1 under the control of the Video Volume register, 14h. The VIDEO_Rlevel can be muted (along with VIDEO_L) or adjusted from +12 dB to -34.5 dB in 1.5-dB steps.Stereo Mix 3D is combined into the Stereo Mix signal at MIX2 for access to the stereo outputs LineOut and Line Level Out.

DIGITAL I/O AND CLOCKINGAC Link clockAn OUTPUT when in Primary Codec mode. This pin provides a 12.288 MHz clock for the AC Link.The clock is derived (internally divided by two) from the 24.576 MHz signal at the crystal inputBIT_CLK 6 I/O (XTL_IN).This pin is an INPUT when the codec is configured in any of the Secondary Codec modes andwould normally use the AC Link clock generated by a Primary Codec.External Amplifier Power Down control signalThis output is set by the EAPD bit (bit D15) in the Powerdown Control/ Status register, 26h. As with

EAPD 47 O the other logic outputs, the output voltage is set by DVDD. This pin is intended to be connected tothe shutdown pin on an external power amplifier. For normal operation the default value of EAPD =0 will enable the external amplifier allowing an input on PC_BEEP to be heard during Cold Reset.Codec IdentityID1# and ID0# determine the Codec Identity for multiple codec use. The Codec Identity configuresthe codec in either Primary or one of three Secondary Codec modes. These Identity pins are of

ID0# 45 I inverted polarity relative to the Codec Identity bits ID1, ID0 (bits D15, D14) in the read-onlyExtended Audio ID register, 28h. If the ID0# pin (pin 45) is connected to ground then the ID0 bit(D14, reg 28h) will be set to “1”. Similarly, connection to DVDD will set the ID0 bit to “0”. If left open(NC), ID0# is pulled high by an internal pull-up resistor.Codec IdentityID1# and ID0# determine the codec address for multiple codec use. The Codec Identity configuresthe codec in either Primary or one of three Secondary Codec modes. These Identity pins are of

ID1# 46 I inverted polarity relative to the Codec Identity bits ID1, ID0 (bits D15, D14) in the read-onlyExtended Audio ID register, 28h. If the ID1# pin (pin 46) is connected to ground then the ID1 bit(D15, reg 28h) will be set to “1”. Similarly, connection to DVDD will set the ID1 bit to “0”. If left open(NC), ID1# is pulled high by an internal pull-up resistor.Cold ResetThis active low signal causes a hardware reset which returns the control registers and all internalcircuits to their default conditions. RESET# MUST be used to initialize the LM4549B after Power OnRESET# 11 I when the supplies have stabilized. Cold Reset also clears the codec from both ATE and Vendortest modes. In addition, while active, it switches the PC_BEEP mono input directly to both channelsof the LINE_OUT stereo output.




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Output from codecThis is the output for AC Link Input Frames from the LM4549B codec to an AC '97 Digital AudioSDATA_IN 8 O Controller. These frames can contain both codec status data and PCM audio data from the ADCs.The LM4549B clocks data from this output on the rising edge of BIT_CLK.Input to codecThis is the input for AC Link Output Frames from an AC '97 Digital Audio Controller to the LM4549BSDATA_OUT 5 I codec. These frames can contain both control data and DAC PCM audio data. This input issampled by the LM4549B on the falling edge of BIT_CLK.AC Link frame marker and Warm ResetThis input defines the boundaries of AC Link frames. Each frame lasts 256 periods of BIT_CLK. Innormal operation SYNC is a 48 kHz positive pulse with a duty cycle of 6.25% (16/256). SYNC issampled on the falling edge of BIT_CLK and the codec takes the first positive sample of SYNC asSYNC 10 I defining the start of a new AC Link frame. If a subsequent SYNC pulse occurs within 255 BIT_CLKperiods of the frame start it will be ignored.SYNC is also used as an active high input to perform an (asynchronous) Warm Reset. Warm Resetis used to clear a power down state on the codec AC Link interface.24.576-MHz crystal or oscillator inputTo complete the oscillator circuit use a fundamental mode crystal operating in parallel resonanceand connect a 1MΩ resistor across pins 2 and 3. Choose the load capacitors (Figure 22, C1, C2) tosuit the crystal (e.g. C1 = C2 = 33 pF for a crystal designed for a 20 pF load. Assumes that each

XTL_IN 2 I 'Input + trace' capacitance = 7 pF)This pin may also be used as the input for an external oscillator (24.576 MHz nominal) at standardlogic levels (VIH, VIL).This pin is only used when the codec is in Primary mode. It may be left open (NC) for anySecondary mode.24.576-MHz crystal outputUsed with XTAL_IN to configure a crystal oscillator.XTL_OUT 3 O When the codec is used with an external oscillator this pin should be left open (NC).When the codec is configured in a Secondary mode this pin is not used and may be left open (NC).

POWER SUPPLIES AND REFERENCESAVDD 25 I Analog supplyAVSS 26 I Analog groundDVDD1 1 I Digital supplyDVDD2 9 I Digital supplyDVSS1 4 I Digital groundDVSS2 7 I Digital ground

Nominal 2.2-V internal referenceVREF 27 O Not intended to sink or source current. Use short traces to bypass (3.3-µF, 0.1-µF) this pin to

maximize codec performance. See text.Nominal 2.2-V reference outputVREF_OUT 28 O Can source up to 5 mA of current and can be used to bias a microphone.

3D SOUND AND NO-CONNECTS (NC)3DN 34 These pins are used to complete the TI 3D Sound stereo enhancement circuit. Connect a 0.022 µF

capacitor between pins 3DP and 3DN. TI 3D Sound can be turned on and off via the 3D bit (D13) inO the General Purpose register, 20h. TI 3D Sound uses a fixed-depth type stereo enhancement

3DP 33 circuit hence the 3D Control register, 22h is read-only and is not programmable. If TI 3D Sound isnot needed, these pins should be left open (NC).




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29303132

These pins are not used and should be left open (NC).38NC NC For second source applications these pins may be connected to a noise-free supply or ground (e.g.

40 AVDD or AVSS), either directly or through a capacitor.42434448

7 Specifications

7.1 Absolute Maximum Ratingsover operating free-air temperature range (unless otherwise noted) (1) (2)

MIN MAX UNITSupply Voltage 6 6 VInput Voltage −0.3 VDD +0.3 VJunction Temperature 150 °C

Vapor Phase (60 sec.) 215Soldering Information °C

Infrared (15 sec.) 220Storage Temperature, Tstg –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, which do not imply functional operation of the device at these or any other conditions beyond those indicated under RecommendedOperating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability andspecifications.

7.2 ESD RatingsVALUE UNIT

All pins except 3 ±2000Human-body model (HBM), perANSI/ESDA/JEDEC JS-001 (1) Pin 3 ±750

V(ESD) Electrostatic discharge VAll pins except 3 ±200

Machine Model (MM)Pin 3 ±100

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditionsover operating free-air temperature range (unless otherwise noted)

MIN MAX UNITTemperature TMIN ≤ TA ≤ TMAX

(1) −40 85 °CAnalog Supply 4.2 5.5 VDigital Supply 3 5.5 V

(1) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, RθJA, and the ambient temperatureTA. The maximum allowable power dissipation is PDMAX = (TJMAX– TA)/RθJA or the number given in Absolute Maximum Ratings,whichever is lower. For the LM4549B, TJMAX = 150°C. The typical junction-to-ambient thermal resistance is 74°C/W for package numberPT0048A.




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7.4 Thermal InformationLM4549B

THERMAL METRIC (1) PT (LQFP) UNIT48 PINS

RθJA Junction-to-ambient thermal resistance 74 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics applicationreport, SPRA953.

7.5 Electrical CharacteristicsThe following specifications apply for AVDD = 5 V, DVDD = 3.3 V, Fs = 48 kHz, single codec configuration, (primary mode)unless otherwise noted. Limits apply for TA= 25°C. The reference for 0 dB is 1 Vrms unless otherwise specified. (1) (2)

PARAMETER TEST CONDITIONS MIN TYP (3) MAX (4) UNITAVDD Analog Supply 4.2 5.5 VDVDD Digital Supply 3 5.5 V

DVDD = 5 V 34Digital Quiescent PowerDIDD mASupply Current DVDD = 3.3 V 19Analog Quiescent PowerAIDD AVDD = 5.5 V 53 mASupply Current

IDSD Digital Shutdown Current PR543210 = 111111 19 µAIASD Analog Shutdown Current PR543210 = 111111 70 µAVREF Reference Voltage No pullup resistor 2.16 VPSRR Power Supply Rejection Ratio 40 dBANALOG LOOPTHROUGH MODE (5)

Dynamic (6) CD Input to Line Output, -60 dB Input THD+N 90 97 dBTHD Total Harmonic Distortion VO = -3 dB, f = 1 kHz, RL = 10 kΩ 0.013% 0.02%ANALOG INPUT SECTION

LINE_IN, AUX, CD, VIDEO, PC_BEEP,VIN Line Input Voltage 1 VrmsPHONEVIN Mic Input with 20 dB Gain 0.1 VrmsVIN Mic Input with 0 dB Gain 1 VrmsXtalk Crosstalk CD Left to Right -95 dBZIN Input Impedance (6) All Analog Inputs 10 40 kΩCIN Input Capacitance (6) 3.7 7 pF

Interchannel Gain Mismatch CD Left to Right 0.1 dBRECORD GAIN AMPLIFIER - ADCAS Step Size 0 dB to 22.5 dB 1.5 dBAM Mute Attenuation (6) 86 dB

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions forwhich the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electricalspecifications under particular test conditions which ensure specific performance limits. This assumes that the device is within theOperating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indicationof device performance.

(2) All voltages are measured with respect to the ground pin, unless otherwise specified.(3) Typicals are measured at 25°C and represent the parametric norm.(4) Limits are specified to AOQL (Average Outgoing Quality Level).(5) Loopthrough mode describes a path from an analog input through the analog mixer to an analog output(6) These specifications are ensured by design and characterization; they are not production tested.




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Electrical Characteristics (continued)The following specifications apply for AVDD = 5 V, DVDD = 3.3 V, Fs = 48 kHz, single codec configuration, (primary mode)unless otherwise noted. Limits apply for TA= 25°C. The reference for 0 dB is 1 Vrms unless otherwise specified.(1)(2)

PARAMETER TEST CONDITIONS MIN TYP (3) MAX (4) UNITMIXER SECTIONAS Step Size +12 dB to -34.5 dB 1.5 dBAM Mute Attenuation 86 dBANALOG TO DIGITAL CONVERTERS

Resolution 18 BitsDynamic (6) -60 dB Input THD+N, A-Weighted 86 90 dBFrequency Response -1 dB Bandwidth 20 kHz

DIGITAL TO ANALOG CONVERTERSResolution 18 BitsDynamic (6) -60 dB Input THD+N, A-Weighted 82 89 dB

THD Total Harmonic Distortion VIN = -3 dB, f = 1 kHz, RL = 10 kΩ 0.01%Frequency Response 20 - 21 kHzGroup Delay (6) Sample Frequency = 48 kHz 0.36 1 msOut of Band Energy (7) -40 dBStop Band Rejection 70 dB

DT Discrete Tones -96 dBANALOG OUTPUT SECTIONAS Step Size 0 dB to -46.5 dB 1.5 dBAM Mute Attenuation 86 dBZOUT Output Impedance (6) All Analog Outputs 220 ΩDIGITAL I/O (6)

0.65 xVIH High level input voltage VDVDD

0.35 xVIL Low level input voltage VDVDD

0.90 xVOH High level output voltage IO = 2.5 mA VDVDD

0.10 xVOL Low level output voltage IO = 2.5 mA VDVDD

IL Input Leakage Current AC Link inputs ±10 µAIL Tri state Leakage Current High impedance AC Link outputs ±10 µACIN AC-Link I/O capacitance (6) SDout, BitClk, SDin, Sync, Reset# only 4 7.5 pFIDR Output drive current AC Link outputs 5 mA

(7) Out of band energy is measured from 28.8 kHz to 100 kHz relative to a 1-Vrms DAC output.

7.6 Timing RequirementsMIN NOM MAX UNIT

FBC BIT_CLK frequency 12.288 MHzTBCP BIT_CLK period 81.4 nsTCH BIT_CLK high Variation of BIT_CLK duty cycle from 50% ±20%FSYNC SYNC frequency 48 kHzTSP SYNC period 20.8 µsTSH SYNC high pulse width 1.3 µsTSL SYNC low pulse width 19.5 µs

Setup Time for codecTDSETUP SDATA_OUT to falling edge of BIT_CLK 10 3.5 nsdata input




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BIT_CLK

SDATA_IN

TCO

TDHOLDTDSETUP

SYNC

TS

THOLD

SDATA_OUT

SYNC

TSH

TSL

TSP

TBCH

TBCL

TBCP

BIT_CLK


Timing Requirements (continued)MIN NOM MAX UNIT

Hold Time for codecTDHOLD Hold time of SDATA_OUT from falling edge of BIT_CLK 10 5.3 nsdata input (1)

Setup Time for codecTSSETUP SYNC to falling edge of BIT_CLK 10 3.8 nsSYNC input (1)

Hold Time for codecTSHOLD Hold time of SYNC from falling edge of BIT_CLK 10 nsSYNC input (1)

TCO Output Valid Delay Output Delay of SDATA_IN from rising edge of BIT_CLK 5.2 15 nsTRISE Rise Time (1) BIT_CLK, SYNC, SDATA_IN or SDATA_OUT 6 nsTFALL Fall Time (1) BIT_CLK, SYNC, SDATA_IN or SDATA_OUT 6 ns

RESET# active lowTRST_LOW For Cold Reset 1 µspulse width (1)

RESET# inactive toTRST2CLK For Cold Reset 162.8 271 nsBIT_CLK start upSYNC active high pulseTSH For Warm Reset 1 µswidth (1)

TSYNC2CL SYNC inactive to For Warm Reset 162.8 nsK BIT_CLK start upTS2_PDOW AC Link Power Down Delay from end of Slot 2 to BIT_CLK, SDATA_IN low 1 µsN DelayTSUPPLY2 Power-On Reset Time from minimum valid supply levels to end of Reset 1 µsRST

Setup to trailing edge ofTSU2RST For ATE Test Mode 15 nsRESET# (1)

Rising edge of RESET#TRST2HZ For ATE Test Mode 25 nsto Hi-Z (1)

(1) These specifications are ensured by design and characterization; they are not production tested.

Figure 1. Clocks

Figure 2. Data Delay, Setup and Hold




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SYNC

TSH TSYNC2CLK

BIT_CLK

RESET#

TRST_LOW TRST2CLK

BIT_CLK

RESET#

TRST_LOW TRST2CLK

BIT_CLK

DVDD, AVDD

TSUPPLY2RST

DVDD (min), AVDD (min)

Input: VIH Output: VOH

Input: VIL Output: VOL

SYNCBIT_CLK

SDATA_INSDATA_OUT

TRISE TFALL

10%

90% 90%

10%


Figure 3. Digital Rise and Fall

Figure 4. Legend

Figure 5. Power-On Reset

Figure 6. Cold Reset

Figure 7. Warm Reset




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7.7 Typical Characteristics

Figure 8. ADC Noise Floor Figure 9. DAC Noise Floor

Figure 10. Line Out Noise Floor (Analog Loopthrough) Figure 11. Line Level Out Noise Floor (Analog Loopthrough)

Figure 12. ADC Frequency Response Figure 13. DAC Frequency Response




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DA

C S

AM

PLE

RA

TE

C

ON

VE

RT

ER

: 2C

hA

DC

SA

MP

LE R

AT

E

CO

NV

ER

TE

R: 3

2h

6

6

6

MIC1

AUX

MIC2RECORD

SELECT

MUX

CD

VIDEO

LINE_IN

PHONE

PC_BEEP

LINE_OUT

LNLVL_OUT

MONO_OUT

EAPD

RESET#

SDATA_OUT

SYNC

BIT_CLK

SDATA_IN

XTAL_OUT

XTAL_IN

ID0#

ID1#

*

*

*

6

MIX2

+

MIX1

STEREO SIGNAL PATH

MONO SIGNAL PATHGain Attenuation Mute(Mute is default)

NNAddress of Analog Input Volume Control Register

NN (HEX)

G A M

* Asterisk denotes default setting after Cold Reset

DIGITAL SIGNAL PATH

18

18

18

18

16

Control bit m in Register with hexadecimal address NN

Dm, NNh

Control Register with hexadecimal address NN

NNh

6'DAC

6'DAC

6'ADC

6'ADC

18h

*GAIN: D6,0Eh

*0 dB/20 dB

$&¶97 REGISTERS

CODEC IDENTITY SELECT

AC

LIN

K IN

TE

RF

AC

E

D13, 20h

NATIONAL 3D SOUND

GAINATTENMUTE

1Ch

GAINMUTE

Atten Mute

MONO VOLUME: 06h

Atten Mute

LINE LEVEL VOLUME: 04h

Atten Mute

MASTER VOLUME: 02h

GAM

0C

GAM

0A

AM

0E

GAM

10

GAM

12

GAM

14

GAM

16

GAM

POWER SUPPLY and

REFERENCESMONOMIX

MIX

ST

ER

EO

M

IX

STEREOMIX 3D

POP

MS

*


8 Detailed Description

8.1 OverviewThe LM4549B codec can mix, process and convert among analog (stereo and mono) and digital (AC Link format)inputs and outputs. There are four stereo and four mono analog inputs and two stereo and one mono analogoutputs. A single codec supports data streaming on two input and two output channels of the AC Link digitalinterface simultaneously.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 ADC Inputs and OutputsAll four of the stereo analog inputs and three of the mono analog inputs can be selected for conversion by the18-bit stereo ADC. Digital output from the left and right channel ADCs is always located in AC Link Input Frameslots 3 and 4 respectively. Input level to either ADC channel can be muted or adjusted from the Record Gainregister, 1Ch. Adjustments are in 1.5 dB steps over a gain range of 0 dB to +22.5 dB and both channels mutetogether (mute bit D15). Input selection for the ADC is through the Record Select Mux controlled from the RecordSelect register, 1Ah, together with microphone selection controlled by the MS bit (bit D8) in the General Purposeregister, 20h. One of the stereo inputs, CD_IN, uses a quasi-differential 3-pin interface where both stereochannel inputs are referenced to the third pin, CD_GND. CD_GND should be AC coupled to the source groundand provides common-mode feedback to cancel ground noise. It is not a DC ground. The other three stereoinputs, LINE_IN, AUX and VIDEO are 2-pin interfaces, single-ended for each stereo channel, with analog ground




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Feature Description (continued)(AVSS) as the signal reference. Either of the two mono microphone inputs can be muxed to a programmableboost amplifier before selection for either channel of the ADC. The Microphone Mux is controlled by theMicrophone Selection (MS) bit (D8) in the General Purpose register (20h) and the 20 dB programmable boost isenabled by the 20dB bit (D6) in register 0Eh. The mono PHONE input may also be selected for either ADCchannel.

8.3.2 Analog Mixing: MIX1Five analog inputs are available for mixing at the stereo mixer, MIX1 – all four stereo and one mono, namely themicrophone input selected by MS (D8, reg 20h). Digital input to the codec can be directed to either MIX1 or toMIX2 after conversion by the 18-bit stereo DAC and level adjustment by the PCM Out Volume control register(18h). Each input to MIX1 may be muted or level adjusted using the appropriate Mixer Input Volume Register:Mic Volume (0Eh), Line_In Volume (10h), CD Volume (12h), Video Volume (14h), Aux Volume (16h) and PCMOut Volume (18h). The mono microphone input is mixed equally into left and right stereo channels but stereomixing is orthogonal, that is, left channels are only mixed with other left channels and right with right. The left andright amplitudes of any stereo input may be adjusted independently however mute for a stereo input acts on bothleft and right channels.

8.3.3 DAC Mixing and 3D ProcessingControl of routing the DAC output to MIX1 or MIX2 is by the POP bit (D15) in the General Purpose register, 20h.If MIX1 is selected (default, POP=0) then the DAC output is available for processing by the TI 3D Sound circuitry.If MIX2 is selected, the DAC output will bypass the 3D processing. This allows analog inputs to be enhanced bythe analog 3D Sound circuitry prior to mixing with digital audio. The digital audio may then use alternative digital3D enhancements. TI 3D Sound circuitry is enabled by the 3D bit (D13) in the General Purpose register, 20h,and is a fixed depth implementation. The 3D Control register, 22h, is therefore not programmable (read-only).The 3D Sound circuitry defaults to disabled after reset.

8.3.4 Analog Mixing: MIX2MIX2 combines the output of MIX1 (Stereo Mix 3D) with the two mono analog inputs, PHONE and PC_BEEP;each are level-adjusted by the input control registers Phone Volume (0Ch) and PC_Beep Volume (0Ah)respectively. If selected by the POP bit (D15, reg 20h), the DAC output is also summed into MIX2.

8.3.5 Stereo MixThe output of MIX2 is the signal, Stereo Mix. Stereo Mix is used to drive both the Line output (LINE_OUT) andthe Line Level output (LNLVL_OUT) and can also be selected as the input to the ADC by the Record Select Mux.In addition, the two channels of Stereo Mix are summed to form a mono signal (Mono Mix) also selectable by theRecord Select Mux as an input to either channel of the ADC.

8.3.6 Stereo OutputsThe output volume from LINE_OUT and LNLVL_OUT can be muted or adjusted by 0 dB to 45 dB in nominal 3-dB steps under the control of the output volume registers Master Volume (02h) and Line Level Volume (04h)respectively. As with the input volume registers, adjustments to the levels of the two stereo channels can bemade independently but both left and right channels share a mute bit (D15).

8.3.7 Mono OutputThe mono output (MONO_OUT) is driven by one of two signals selected by the MIX bit (D9) in the GeneralPurpose register, 20h. The signal selected by default (MIX = 0) is the mono summation of the two channels ofStereo Mix 3D, the stereo output of the mixer MIX1. Setting the control bit MIX = 1, selects a microphone input,MIC1 or MIC2. The choice of microphone is controlled by the Microphone Select (MS) bit (D8) also in theGeneral Purpose register, 20h.




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Feature Description (continued)8.3.8 Analog Loopthrough and Digital LoopbackAnalog Loopthrough refers to an all-analog signal path from an analog input through the mixers to an analogoutput. Digital Loopback refers to a mixed-mode analog and digital signal path from an analog input through theADC, looped-back (LPBK bit – D7, 20h) through the DAC and mixers to an analog output. This is an 18-bit digitalloopback at 48 kHz, bypassing the the SRC logic even if an SRC rate other than 48 kHz is selected.

8.3.9 ResetsCOLD RESET is performed when RESET# (pin 11) is pulled low for > 1 µs. It is a complete reset. All registersand internal circuits are reset to their default state. It is the only reset which clears the ATE and Vendor testmodes.

WARM RESET is performed when SYNC (pin 10) is held high for > 1 µs and the codec AC Link digital interfaceis in power down (PR4 = 1, Power-down Control / Status register, 26h). It is used to clear PR4 and power up theAC Link digital interface but otherwise does not change the contents of any internal circuitry.

REGISTER RESET is performed when any value is written to the RESET register, 00h. It resets all registers totheir default state and will modify circuit configurations accordingly but does not reset any other internal circuits.

8.3.10 Backwards CompatibilityThe LM4549B is improved compared with the LM4549A. If it is required to build a board that will use either part,a 10-kΩ resistor must be added from the VREF pin (pin 27) to AVDD for the LM4549A. It is not required for theLM4549B. Addition of this resistor will slightly increase the temperature coefficient of the internal bandgapreference and decrease the THD performance, but overall performance will still be better than the LM4549A. TheLM4549A requires that pins 1 and 9 (DVDD) connect directly to a 27 nH. inductor before going to the 3.3-V digitalsupply and the bypass capacitors. The inductor is not required for the LM4549B and should not be used.

8.4 Device Functional Modes

8.4.1 Low Power Modes

The LM4549B provides 6 bits to control the powerdown state of internal analog and digital subsections andclocks. It also provides one bit intended to control an external analog power amplifier. These 7 bits (PR0 – PR5,EAPD) are located in the 8 MSBs of the Powerdown Control/Status register, 26h. The status of the four mainanalog subsections is given by the 4 LSBs in the same register, 26h.

The power-down bits are implemented in compliance with AC '97 Rev 2.1 to support the standard device powermanagement states D0 – D3 as defined in the ACPI and PCI Bus Power Management Specification.

PR0 controls the power-down state of the ADC and associated sampling rate conversion circuitry. PR1 controlspower down for the DAC and the DAC sampling rate conversion circuitry. PR2 powers down the mixer circuits(MIX1, MIX2, TI 3D Sound, Mono Out, Line Out). PR3 powers down VREF in addition to all the same mixercircuits as PR2. PR4 powers down the AC Link Digital Interface – see Figure 14 for signal power-down timing.PR5 disables internal clocks but leaves the crystal oscillator and BIT_CLK running (needed for minimum Primarymode power-down dissipation in multi-codec systems). PR6 is not used. EAPD controls the External AmplifierPower-Down pin (pin 47).

After a subsection has undergone a power-down cycle, the appropriate status bit(s) in the Power-DownControl/Status register (26h) must be polled to confirm readiness. In particular the startup time of the VREFcircuitry depends on the value of the decoupling capacitors on pin 27 (3.3 µF, 0.1 µF in parallel isrecommended).

When the AC Link Digital Interface is powered down the codec output signals SDATA_IN and BIT_CLK (Primarymode) are cleared to zero and no control data can be passed between controller and codec(s). This power-downstate can be cleared in two ways: Cold Reset (RESET# = 0) or Warm Reset (SYNC = 1, no BIT_CLK). ColdReset sets all registers back to their default values (including clearing PR4) whereas Warm Reset only clears thePR4 bit and restarts the AC Link Digital Interface leaving all register contents otherwise unaffected. For Warm




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SLOT #

SYNC

AC LINK

OUTPUT

FRAMES:

SDATA_OUT

0 1 2 3 4 65 7 1098 11 12

RSRVTAGCMD

ADR

CMD

DATA

PCM

LEFT

PCM

RIGHTRSRVRSRV RSRV RSRVRSRV RSRV RSRV

AC LINK INPUT

FRAMES:

SDATA_IN

RSRVTAGSTAT

ADR

STAT

DATA

PCM

LEFT

PCM

RIGHTRSRVRSRV RSRV RSRVRSRV RSRV RSRV

Codec ID: to select target codec in multiple codec configurations

Slot Request bits, 11 & 10: to request data from Output Frame slots 3 & 4

TAG

PHASEDATA PHASE

SYNC

BIT_CLK

SDATA_OUT

SDATA_IN

Slot 12Prev. Frame

TAG

TAG

Slot 0

Slot 12Prev. Frame

Write to

REG. 26h

Data

PR4 = 1

Note: BIT_CLK and data transitions are not to scale TS2_PDOWN

Slot 1 Slot 2


Device Functional Modes (continued)Reset (see Figure 7), the SYNC input is used asynchronously. The LM4549B codec allows the AC Link digitalinterface powerdown state to be cleared immediately so that its duration can be essentially as short as TSH, theWarm Reset pulse width. However for conformance with AC '97 Rev 2.1, Warm Reset should not be appliedwithin four frame times of power down that is, the AC Link powerdown state should be allowed to last at least82.8 µs.

Figure 14. AC Link Power-Down Timing

8.4.2 Test Modes

AC '97 Rev 2.1 defines two test modes: ATE test mode and Vendor test mode. Cold Reset is the only way to exiteither of them. The ATE test mode is activated if SDATA_OUT is sampled high by the trailing edge (zero-to-onetransition) of RESET#. In ATE test mode the codec AC Link outputs SDATA_IN and BIT_CLK are configured to ahigh impedance state to allow tester control of the AC Link interface for controller testing. ATE test mode timingparameters are given in the Electrical Characteristics table. The Vendor test mode is entered if SYNC is sampledhigh by the zero-to-one transition of RESET#. Neither of these entry conditions can occur in normal AC Linkoperation but take care to avoid mistaken activation of the test modes when using non-standard controllers.

8.5 Programming

8.5.1 AC Link Serial Interface Protocol

Figure 15. AC Link Bidirectional Audio Frame




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BIT_CLK

SDATA_OUT

SYNC

End of previous

Audio Frame

Valid

Frame

Slot

(1)

Slot

(4)Bit 19 Bit 0

Bit 19

Slot 2

Bit 0Slot 12

SLOTS 2 to 12SLOT 1

ID0

Tag bits: &uv^o^so]_], Codec ID

ID1

Tag Phase 20.8 Ps(48 kHz)

Data Phase

Read / Write Request,

Command Address

Slot (x) = ³1´LQGLFDWHVWLPHVORWx contains valid PCM dataCodec ID = (ID1, ID0) - codec address for multiple codecs

Data: Command and Audio


Programming (continued)

Figure 16. AC Link Output Frame

8.5.1.1 AC Link Output Frame: SDATA_OUT, Controller Output to LM4549B Input

The AC Link Output Frame carries control and PCM data to the LM4549B control registers and stereo DAC.Output Frames are carried on the SDATA_OUT signal which is an output from the AC '97 Digital Controller andan input to the LM4549B codec. As shown in Figure 15, Output Frames are constructed from thirteen time slots:one Tag Slot followed by twelve Data Slots. Each Frame consists of 256 bits with each of the twelve Data Slotscontaining 20 bits. Input and Output Frames are aligned to the same SYNC transition. Note that since theLM4549B is a two channel codec, it only accepts data in 4 of the twelve Data Slots – 2 for control, one each forPCM data to the left and right channel DACs. Data Slot 3 & 4 are used to stream data to the stereo DAC for allmodes selected by the Identity pins ID1#, ID0#.

A new Output Frame is signaled with a low-to-high transition of SYNC. SYNC should be clocked from thecontroller on a rising edge of BIT_CLK and, as shown in Figure 16 and Figure 17, the first tag bit in the Frame(“Valid Frame”) should be clocked from the controller by the next rising edge of BIT_CLK and sampled by theLM4549B on the following falling edge. The AC '97 Controller should always clock data to SDATA_OUT on arising edge of BIT_CLK and the LM4549B always samples SDATA_OUT on the next falling edge. SYNC issampled with the falling edge of BIT_CLK.

The LM4549B checks each Frame to ensure 256 bits are received. If a new Frame is detected (a low-to-hightransition on SYNC) before 256 bits are received from the old Frame then the new Frame is ignored i.e. the dataon SDATA_OUT is discarded until a valid new Frame is detected.

The LM4549B expects to receive data MSB first, in an MSB justified format.

8.5.1.1.1 SDATA_OUT: Slot 0 – Tag Phase

The first bit of Slot 0 is designated the "Valid Frame" bit. If this bit is 1, it indicates that the current Output Framecontains at least one slot of valid data and the LM4549B will check further tag bits for valid data in the expectedData Slots. With the codec in Primary mode, a controller will indicate valid data in a slot by setting the associatedtag bit equal to 1. Since it is a two channel codec the LM4549B can only receive data from four slots in a givenframe and so only checks the valid-data bits for 4 slots. In Primary mode these tag bits are for: slot 1 (CommandAddress), slot 2 (Command Data), slot 3 (PCM data for left DAC) and slot 4 (PCM data for right DAC).

The last two bits in the Tag contain the Codec ID used to select the target codec to receive the frame in multiplecodec systems. When the frame is being sent to a codec in one of the Secondary modes the controller does notuse bits 14 and 13 to indicate valid Command Address and Data in slots 1 and 2. Instead, this role is performedby the Codec ID bits – operation of the Extended AC Link assumes that the controller would not access asecondary codec unless it was providing valid Command Address and/or Data. When in one of the secondarymodes the LM4549B only checks the tag bits for the Codec ID and for valid data in the two audio data slots 3 &4.




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BIT_CLK

SDATA_OUT

SYNC

LM4549B samples

SYNC assertion

LM4549B samples

first bit of SDATA_OUT

End of previous

Audio Frame

Valid

Frame

Slot

(1)

Slot

(2)


Programming (continued)When sending an Output Frame to a Secondary mode codec, a controller should set tag bits 14 and 13 to zero.

Figure 17. Start of AC Link Output Frame

Table 1. Slot 0, Output FrameBit Description Comment15 Valid Frame 1 = Valid data in at least one slot.14 Control register address 1 = Valid Control Address in Slot 1 (Primary codec only)13 Control register data 1 = Valid Control Data in Slot 2 (Primary codec only)

1 = Valid PCM Data in Slot 312 Left DAC data in Slot 3 (Primary & all Secondary modes)1 = Valid PCM Data in Slot 411 Right DAC data in Slot 4 (Primary & all Secondary modes)

10:2 Not Used Controller should stuff these slots with “0”sCodec ID The codec ID is used in a multi-codec system to identify the target Secondary1,0 (ID1, ID0) codec for the Control Register address and/or data sent in the Output Frame

8.5.1.1.2 SDATA_OUT: Slot 1 – Read/Write, Control Address

Slot 1 is used by a controller to indicate both the address of a target register in the LM4549B and whether theaccess operation is a register read or register write. The MSB of slot 1 (bit 19) is set to 1 to indicate that thecurrent access operation is 'read'. Bits 18 through 12 are used to specify the 7-bit register address of the read orwrite operation. The least significant twelve bits are reserved and should be stuffed with zeros by the AC '97controller.

Table 2. Slot 1, Output FrameBits Description Comment

1 = Read19 Read/Write 0 = Write18:12 Register Address Identifies the Status/Command register for read/write11:0 Reserved Controller should set to "0"

8.5.1.1.3 SDATA_OUT: Slot 2 – Control Data

Slot 2 is used to transmit 16-bit control data to the LM4549B when the access operation is 'write'. The leastsignificant four bits should be stuffed with zeros by the AC '97 controller. If the access operation is a registerread, the entire slot, bits 19 through 0 should be stuffed with zeros.




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BIT_CLK

SDATA_IN

SYNC

End of previous

Audio Frame

Codec

Ready

Slot

(1)

Slot

(4)^0_ Bit 19 Bit 0

Bit 19

Slot 2

Bit 0Slot 12

SLOTS 2 to 12SLOT 1

^0_

Tag bits: ZÇv^o^so]_]

Tag Phase 20.8 Ps(48 kHz)

Data Phase

Status Address / Slot

Request bits for VSA

Slot (x) = ³1´LQGLFDWHVWLPHVORWx contains valid PCM data Data: Status and Audio


Table 3. Slot 2, Output FrameBits Description Comment19:4 Control Register Write Data Controller should stuff with zeros if operation is “read”3:0 Reserved Set to "0"

8.5.1.1.4 SDATA_OUT: Slots 3 & 4 – PCM Playback Left/Right Channels

Slots 3 and 4 are 20-bit fields used to transmit PCM data to the left and right channels of the stereo DAC for allcodec Primary and Secondary modes. Any unused bits should be stuffed with zeros. The LM4549B DACs have18-bit resolution and will therefore use the 18 MSBs of the 20-bit PCM data (MSB justified).

Table 4. Slots 3 & 4, Output FrameBits Description Comment

PCM DAC Data Slots used to stream data to DACs for all Primary or Secondary modes.19:0 (Left /Right Channels) Set unused bits to "0"

8.5.1.1.5 SDATA_OUT: Slots 5 to 12 – Reserved

These slots are not used by the LM4549B and should all be stuffed with zeros by the AC '97 Controller.

Figure 18. AC Link Input Frame

8.5.1.2 AC Link Input Frame: SDATA_IN, Controller Input from LM4549B Output

The AC Link Input Frame contains status and PCM data from the LM4549B control registers and stereo ADC.Input Frames are carried on the SDATA_IN signal which is an input to the AC '97 Digital Audio Controller and anoutput from the LM4549B codec. As shown in Figure 15, Input Frames are constructed from thirteen time slots:one Tag Slot followed by twelve Data Slots. The Tag Slot, Slot 0, contains 16 bits of which 5 are used by theLM4549B. One is used to indicate that the AC Link interface is fully operational and the other 4 to indicate thevalidity of the data in the four of the twelve following Data Slots that are used by the LM4549B. Each Frameconsists of 256 bits with each of the twelve data slots containing 20 bits.

A new Input Frame is signaled with a low-to-high transition of SYNC. SYNC should be clocked from the controlleron a rising edge of BIT_CLK and, as shown in Figure 18 and Figure 19, the first tag bit in the Frame (“CodecReady”) is clocked from the LM4549B by the next rising edge of BIT_CLK. The LM4549B always clocks data toSDATA_IN on a rising edge of BIT_CLK and the controller is expected to sample SDATA_IN on the next fallingedge. The LM4549B samples SYNC on the falling edge of BIT_CLK.

Input and Output Frames are aligned to the same SYNC transition.

The LM4549B checks each Frame to ensure 256 bits are received. If a new Frame is detected (a low-to-hightransition on SYNC) before 256 bits are received from an old Frame then the new Frame is ignored, that is, novalid data is sent on SDATA_IN until a valid new Frame is detected.




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BIT_CLK

SDATA_IN

SYNC

LM4549B samples

SYNC assertion

LM4549B outputs

first bit of SDATA_IN

End of previous

Audio Frame

Codec

Ready

Slot

(1)

Slot

(2)


The LM4549B transmits data MSB first, in a MSB justified format. All reserved bits and slots are stuffed with 0sby the LM4549B.

Figure 19. Start of AC Link Input Frame

8.5.1.2.1 SDATA_IN: Slot 0 – Codec/Slot Status Bits

The first bit (bit 15, “Codec Ready”) of slot 0 in the AC Link Input Frame indicates when theAC Link digitalinterface of the codec and the status and control registers are fully operational. The digital controller is then ableto read the LSBs from the Power-Down Control/Stat register (26h) to determine the status of the four mainanalog subsections. It is important to check the status of these subsections after Initialization, Cold Reset, or theuse of the power-down modes in order to minimize the risk of distorting analog signals passed before thesubsections are ready.

The 4 bits 14, 13, 12 and 11 indicate that the data in slots 1, 2, 3 and 4, respectively, are valid.

Table 5. Slot 0, Input FrameBit Description Comment15 Codec Ready Bit 1 = AC Link Interface Ready14 Slot 1 data valid 1 = Valid Status Address or Slot Request13 Slot 2 data valid 1 = Valid Status Data

1 = Valid PCM Data12 Slot 3 data valid (Left ADC)1 = Valid PCM Data11 Slot 4 data valid (Right ADC)

8.5.1.2.2 SDATA_IN: Slot 1 – Status Address / Slot Request Bits

This slot echoes (in bits 18 – 12) the 7-bit address of the codec control/status register received from thecontroller as part of a read-request in the previous frame. If no read-request was received, the codec stuffs thesebits with zeros.

Bits 11, 10 are Slot Request bits that support the Variable Rate Audio (VRA) capabilities of the LM4549B. For allcodec Primary and Secondary modes, the left and right channels of the DAC take PCM data from slots 3 and 4in the Output Frame respectively. The codec uses bits 11 and 10 to request DAC data from these two slots. Ifbits 11 and 10 are set to 0, the controller should respond with valid PCM data in slots 3 and 4 of the next OutputFrame. If bits 11 and 10 are set to 1, the controller should not send data.

The codec has full control of the slot request bits. By default, data is requested in every frame, corresponding toa sample rate equal to the frame rate (SYNC frequency) – 48 kHz when XTAL_IN = 24.576 MHz. To sendsamples at a rate below the frame rate, a controller should set VRA = 1 (bit 0 in the Extended AudioControl/Status register, 2Ah) and program the desired rate into the PCM DAC Rate register, 2Ch. Both DACchannels operate at the same sample rate. Values for common sample rates are given in the Register Mapssection (Sample Rate Control Registers, 2Ch, 32h) but any rate between 4 kHz and 48 kHz (to a resolution of 1




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Hz) is supported. Slot Requests from the LM4549B are issued completely deterministically. For example if asample rate of 8000 Hz is programmed into 2Ch then the LM4549B will always issue a slot request in every sixthframe. A frequency of 9600 Hz will result in a request every fifth frame while a frequency of 8800 Hz will causeslot requests to be spaced alternately five and six frames apart. This determinism makes it easy to plan taskscheduling on a system controller and simplifies application software development.

The LM4549B will ignore data in Output Frame slots that do not follow an Input Frame with a Slot Request. Forexample, if the LM4549B is expecting data at a 8000 Hz rate yet the AC '97 Digital Audio Controller continues tosend data at 48000 Hz, then only those one-in-six audio samples that follow a Slot Request will be used by theDAC. The rest will be discarded.

Bits 9 – 2 are request bits for slots not used by the LM4549B and are stuffed with zeros. Bits 1 and 0 arereserved and are also stuffed with zeros.

Table 6. Slot 1, Input FrameBits Description Comment19 Reserved Stuffed with 0 by LM4549B

18:12 Status Register Index Echo of the requested Status Register address.0 = Controller should send valid data in Slot 3 of the next Output

Slot 3 Request bit Frame.11 (For left DAC PCM data)1 = Controller should not send Slot 3 data.0 = Controller should send valid data in Slot 4 of the next Output

Slot 4 Request bit Frame.10 (For right DAC PCM data)1 = Controller should not send Slot 4 data.

9:2 Unused Slot Request bits Stuffed with 0s by LM4549B1,0 Reserved Stuffed with 0s by LM4549B

8.5.1.2.3 SDATA_IN: Slot 2 – Status Data

This slot returns 16-bit status data read from a codec control and status register. The codec sends the data inthe frame following a read-request by the controller (bit 15, slot 1 of the Output Frame). If no read-request wasmade in the previous frame the codec will stuff this slot with zeros.

Table 7. Slot 2, Input FrameBits Description Comment

Data read from a codec control/status register.19:4 Status Data Stuffed with 0s if no read-request in previous frame.3:0 Reserved Stuffed with 0s by LM4549B

8.5.1.2.4 SDATA_IN: Slot 3 – PCM Record Left Channel

This slot contains sampled data from the left channel of the stereo ADC. The signal to be digitized is selectedusing the Record Select register (1Ah) and subsequently routed through the Record Select Mux and the RecordGain amplifier to the ADC.

This is a 20-bit slot and the digitized 18-bit PCM data is transmitted in an MSB justified format. The remaining 2LSBs are stuffed with zeros.

Table 8. Slot 3, Input FrameBits Description Comment19:2 PCM Record Left Channel data 18-bit PCM sample from left ADC1:0 Reserved Stuffed with 0s by LM4549B

8.5.1.2.5 SDATA_IN: Slot 4 – PCM Record Right Channel

This slot contains sampled data from the right channel of the stereo ADC. The signal to be digitized is selectedusing the Record Select register (1Ah) and subsequently routed through the Record Select Mux and the RecordGain amplifier to the ADC.




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This is a 20-bit slot and the digitized 18-bit PCM data is transmitted in an MSB justified format. The remaining 2LSBs are stuffed with zeros.

Table 9. Slot 4, Input FrameBits Description Comment19:2 PCM Record Right Channel data 18-bit PCM sample from right ADC1:0 Reserved Stuffed with "0"s by LM4549B

8.5.1.2.6 SDATA_IN: Slots 5 to 12 – Reserved

Slots 5 – 12 of the AC Link Input Frame are not used for data by the LM4549B and are always stuffed withzeros.

8.5.2 Multiple Codecs

8.5.2.1 Extended AC LinkUp to four codecs can be supported on the extended AC Link. These multiple codec implementations should runoff a common BIT_CLK generated by the Primary Codec. All codecs share the AC '97 Digital Controller outputsignals, SYNC, SDATA_OUT, and RESET#. Each codec, however, supplies its own SDATA_IN signal back tothe controller, with the result that the controller requires one dedicated input pin per codec. (Figure 20).

By definition there can be one Primary Codec and up to three Secondary Codecs on an extended AC Link. ThePrimary Codec has a Codec Identity = (ID1, ID0) = ID = 00 while Secondary Codecs may have identities equal to01, 10 or 11. The Codec Identity is used as a chip select function. This allows the Command and Status registersin any of the codecs to be individually addressed although the access mechanism for Secondary Codecs differsslightly from that for a Primary.

The Identity control pins, ID1#, ID0# (pins 46 and 45) are internally pulled up to DVDD. The Codec may thereforebe configured as 'Primary' either by leaving ID1#, ID0# open (NC) or by strapping them externally to DVDD(Digital Supply).

The difference between Primary and Secondary codec modes is in their timing source and in the Tag Bithandling in Output Frames for Command/Status register access. For a timing source, a Primary codec dividesdown by 2 the frequency of the signal on XTAL_IN and also generates this as the BIT_CLK output for the use ofthe controller and any Secondary codecs. Secondary codecs use BIT_CLK as an input and as their timing sourceand do not use XTAL_IN or XTAL_OUT. The use of Tag Bits is described below.

8.5.2.2 Secondary Codec Register AccessFor Secondary Codec access, the controller must set the tag bits for Command Address and Data in the OutputFrame as invalid (that is, equal to 0). The Command Address and Data tag bits are in slot 0, bits 14 and 13 andOutput Frames are those in the SDATA_OUT signal from controller to codec. The controller must also place thenon-zero value (01, 10, or 11) corresponding to the Identity (ID1, ID0) of the target Secondary Codec into theCodec ID field (slot 0, bits 1 and 0) in that same Output Frame. The value set in the Codec ID field determineswhich of the three possible Secondary Codecs is accessed. Unlike a Primary Codec, a Secondary Codec willdisregard the Command Address and Data tag bits when there is a match between the 2-bit Codec ID value (slot0, bits 1 and 0) and the Codec Identity (ID1, ID0). Instead it uses the Codec-ID/Identity match to indicate that theCommand Address in slot 1 and (if a write) the Command Data in slot 2 are valid.

When reading from a Secondary Codec, the controller must send the correct Codec ID bits (that is, the targetCodec Identity in slot 0, bits 1 and 0) along with the read-request bit (slot 1, bit 19) and target register address(slot 1, bits 18 – 12). To write to a Secondary Codec, a controller must send the correct Codec ID bits when slot1 contains a valid target register address and write indicator bit and slot 2 contains valid target register data. Awrite operation is only valid if the register address and data are both valid and sent within the same frame. Whenaccessing the Primary Codec, the Codec ID bits are cleared and the tag bits 14 and 13 resume their roleindicating the validity of Command Address and Data in slots 1 and 2.

The use of the tag bits in Input Frames (carried by the SDATA_IN signal) is the same for Primary and SecondaryCodecs.

The Codec Identity is determined by the inverting input pins ID1#, ID0# (pins 46 and 45) and can be read as thevalue of the ID1, ID0 bits (D15, D14) in the Extended Audio ID register, 28h of the target codec.




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Slots in the AC Link Output Frame are always mapped to carry data to the left DAC channel in slot 3 and data tothe right DAC channel in slot 4. Similarly, slots in AC Link Input Frames are always mapped such that PCM datafrom the left ADC channel is carried by slot 3 and PCM data from the right ADC channel by slot 4. OutputFrames are those carried by the SDATA_OUT signal from the controller to the codec while Input Frames arethose carried by the SDATA_IN signal from the codec to the controller.

8.5.2.2.1 Slot 0: TAG bits in Output Frames (Controller to Codec)

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Valid Slot 1 Slot 2 Slot 3 Slot 4 X X X X X X X X X ID1 ID0Frame Valid Valid Valid Valid

8.5.2.2.2 Extended Audio ID register (28h): Support for Multiple Codecs

Reg Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DefaultExtended28h ID1 ID0 X X X X X X X X X X X X X VRA X001hAudio ID




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$&¶97 SECONDARY 2ID = 10

[97 SECONDARY 1

DOCKING: ID = 01

$&¶97 SECONDARY 3ID = 11

[97 PRIMARY

MASTER: ID = 00

SDATA_IN1

SDATA_IN2

SYNC

SDATA_IN0

RESET#

SDATA_OUT

BIT_CLK

ID1#

ID0#

SYNC

SDATA_IN

RESET#

SDATA_OUT

BIT_CLK

45

46

Slots 3 & 4

Line_Out_L

Line_Out_R

DVDD/NC

DVDD/NC

ID1#

ID0#

SYNC

SDATA_IN

RESET#

SDATA_OUT

BIT_CLK

45

46

Slots 3 & 4

Line_Out_L

Line_Out_R

DVDD/NC

ID1#

ID0#

SYNC

SDATA_IN

RESET#

SDATA_OUT

BIT_CLK

45

46

Slots 3 & 4

DVDD/NC

ID1#

ID0#

SYNC

SDATA_IN

RESET#

SDATA_OUT

BIT_CLK

45

46

Slots 3 & 4

Line_Out_L

Line_Out_R

[97

DIGITAL CONTROLLER

SDATA_IN3

Line_Out_L

Line_Out_R

XTAL_IN

XTAL_OUT


Figure 20. Multiple Codecs using Extended AC Link




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8.6 Register Maps

Table 10. LM4549B Register MapREG Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

00h Reset X 0 0 0 1 1 0 1 0 1 0 0 0 0 0 0 0D40h

02h Master Volume Mute X ML5 ML4 ML3 ML2 ML1 ML0 X X MR5 MR4 MR3 MR2 MR1 MR0 8000h

Output Volume 04h Line Level Volume Mute X ML5 ML4 ML3 ML2 ML1 ML0 X X MR5 MR4 MR3 MR2 MR1 MR0 8000h

06h Mono Volume Mute X X X X X X X X X MM5 MM4 MM3 MM2 MM1 MM0 8000h

0Ah PC_Beep Volume Mute X X X X X X X X X X PV3 PV2 PV1 PV0 X 0000h

0Ch Phone Volume Mute X X X X X X X X X X GN4 GN3 GN2 GN1 GN0 8008h

0Eh Mic Volume Mute X X X X X X X X 20dB X GN4 GN3 GN2 GN1 GN0 8008h

10h Line In Volume Mute X X GL4 GL3 GL2 GL1 GL0 X X X GR4 GR3 GR2 GR1 GR0 8808hInput Volume

12h CD Volume Mute X X GL4 GL3 GL2 GL1 GL0 X X X GR4 GR3 GR2 GR1 GR0 8808h

14h Video Volume Mute X X GL4 GL3 GL2 GL1 GL0 X X X GR4 GR3 GR2 GR1 GR0 8808h

16h Aux Volume Mute X X GL4 GL3 GL2 GL1 GL0 X X X GR4 GR3 GR2 GR1 GR0 8808h

18h PCM Out Volume Mute X X GL4 GL3 GL2 GL1 GL0 X X X GR4 GR3 GR2 GR1 GR0 8808h

1Ah Record Select X X X X X SL2 SL1 SL0 X X X X X SR2 SR1 SR0 0000hADC Sources

1Ch Record Gain Mute X X X GL3 GL2 GL1 GL0 X X X X GR3 GR2 GR1 GR0 8000h

20h General Purpose POP X 3D X X X MIX MS LPBK X X X X X X X 0000h

3D Control22h X 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0101h(Read Only)

X 24h Reserved X X X X X X X X X X X X X X X X 0000h

26h Powerdown Ctrl/Stat EAPD PR6 PR5 PR4 PR3 PR2 PR1 PR0 X X X X REF ANL DAC ADC 000Xh

28h Extended Audio ID ID1 ID0 X X X X 0 0 0 0 X X 0 X 0 VRA X001h

Extended Audio2Ah X X X X X X X X X X X X X X X VRA 0000hControl/Status

2Ch PCM DAC Rate SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h

32h PCM ADC Rate SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h

X 5Ah Vendor Reserved 1 X X X X X X X X X X X X X X X X 0000h

X 74h Vendor Reserved 2 X X X X X X X X X X X X X X X X 0000h

X 7Ah Vendor Reserved 3 X X X X X X X X X X X X X X X X 0000h

7Ch Vendor ID1 0 1 0 0 1 1 1 0 0 1 0 1 0 0 1 1 4E53h

7Eh Vendor ID2 0 1 0 0 0 0 1 1 0 1 0 0 1 0 0 1 4349h




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8.6.1 Reset Register (00h)Writing any value to this register causes a Register Reset which changes all registers back to their defaultvalues. If a read is performed on this register, the LM4549B will return a value of 0D40h. This value can beinterpreted in accordance with the AC '97 Specification to indicate that TI 3D Sound is implemented and 18-bitdata is supported for both the ADCs and DACs.

8.6.2 Master Volume Register (02h)This output register allows the output level from either channel of the stereo LINE_OUT to be muted orattenuated over the range 0 dB – 46.5 dB in nominal 1.5-dB steps. There are 6 bits of volume control for eachchannel and both stereo channels can be individually attenuated. The mute bit (D15) acts simultaneously on bothstereo channels of LINE_OUT. The AC'97 specification states that support for the MSB of the level is optional. Allsix bits may be written to the register, but if the MSB is a 1, the MSB is ignored and the register will be set to 011111. This will be the value when the register is read, allowing the software driver to detect whether the MSB issupported or not.

Table 11. Master Volume Register (02h)Mute Mx5:Mx0 Function

0 0 00000 0 dB attenuation0 0 11111 46.5 dB attenuation0 1 xxxxx As Written0 0 11111 As read back1 X XXXXX mute (1)

Default: 8000h

(1) Default settings

8.6.3 Line Level Volume Register (04h)This output register allows the level from both channels of LNLVL_OUT to be muted or individually attenuatedover the range 0 dB to –46.5 dB in nominal 1.5-dB steps. There are 6 bits of volume control for each channelplus one mute bit. The mute bit (D15) acts on both channels. Operation of this register and LNLVL_OUTmatches that of the Master Volume register and the LINE_OUT output.

8.6.4 Mono Volume Register (06h)This output register allows the level from MONO_OUT to be muted or attenuated over the range 0 dB – 46.5 dBin nominal 1.5-dB steps. There are 6 bits of volume control and one mute bit (D15). All 6 bits may be written tothe register, but if the MSB is a 1, the MSB is ignored and the register will be set to 0 11111. This will be thevalue when the register is read, allowing the software driver to detect whether the MSB is supported or not.

Table 12. Mono Volume Register (06h) FunctionsMute MM5:MM0 Function

0 0 00000 0 dB attenuation0 0 11111 46.5 dB attenuation0 1 xxxxx As written0 0 11111 As read back1 X XXXXX mute (1)

Default: 8000h

(1) \Default settings

8.6.5 PC Beep Volume Register (0Ah)This input register adjusts the level of the mono PC_BEEP input to the stereo mixer MIX2 where it is summedequally into both channels of the Stereo Mix signal. PC_BEEP can be both muted and attenuated over a range of0 dB to –45 dB in nominal 3 dB-steps. Note that the default setting for the PC_Beep Volume register is 0 dBattenuation rather than mute.




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Table 13. PC Beep Volume Register (0Ah) FunctionsMute PV3:PV0 Function

0 0000 0 dB attenuation (1)

0 1111 45 dB attenuation1 XXXX mute (1)

Default: 0000h


8.6.6 Mixer Input Volume Registers (Index 0Ch - 18h)These input registers adjust the volume levels into the stereo mixers MIX1 and MIX2. Each channel may beadjusted over a range of +12 dB gain to –34.5 dB attenuation in 1.5-dB steps. For stereo ports, volumes of theleft and right channels can be independently adjusted. Muting a given port is accomplished by setting the MSB to1. Setting the MSB to 1 for stereo ports mutes both the left and right channels. The Mic Volume register (0Eh)controls an additional 20 dB boost for the selected microphone input by setting the 20dB bit (D6).

Table 14. Mixer Input Volume Registers (Index 0Ch - 18h) FunctionsMute Gx4:Gx0 Function

0 0 0000 +12 dB gain0 0 1000 0 dB gain0 1 1111 –34.5 dB attenuation1 X XXXX mute (1)

Default: 8008h (mono registers)8808h (stereo registers)


8.6.7 Record Select Register (1Ah)This register independently controls the sources for the right and left channels of the stereo ADC. The defaultvalue of 0000h corresponds to selecting the (mono) Mic input for both channels.

Table 15. Record Select Register (1Ah) FunctionsSL2:SL0 Source for Left Channel ADC

0 Mic input (1)

1 CD input (L)2 VIDEO input (L)3 AUX input (L)4 LINE_IN input (L)5 Stereo Mix (L)6 Mono Mix7 PHONE input


SR2:SR0 Source for Right Channel ADC0 Mic input (1)

1 CD input (R)2 VIDEO input (R)3 AUX input (R)4 LINE_IN input (R)5 Stereo Mix (R)6 Mono Mix





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SR2:SR0 Source for Right Channel ADC7 PHONE input

Default: 0000h

8.6.8 Record Gain Register (1Ch)This register controls the input levels for both channels of the stereo ADC. The inputs come from the RecordSelect Mux and are selected via the Record Select Control register, 1Ah. The gain of each channel can beindividually programmed from 0dB to +22.5 dB in 1.5-dB steps. Both channels can also be muted by setting theMSB to 1.

Table 16. Record Gain Register (1Ch) FunctionsMute Gx3:Gx0 Function

0 1111 22.5 dB gain0 0000 0 dB gain1 XXXX mute (1)

Default: 8000h


8.6.9 General Purpose Register (20h)This register controls many miscellaneous functions implemented on the LM4549B. The miscellaneous controlbits include POP which allows the DAC output to bypass the TI 3D Sound circuitry, 3D which enables or disablesthe TI 3D Sound circuitry, MIX which selects the MONO_OUT source, MS which controls the MicrophoneSelection mux and LPBK which connects the output of the stereo ADC to the input of the stereo DAC. LPBKprovides a mixed-mode analog and digital loopback path between analog inputs and analog outputs. This is an18 bit digital loopback at 48 kHz, bypassing the SRC logic, even if a sample rate other than 48 kHz is selected.

Table 17. General Purpose Register (20h) FunctionsBIT Function

0 (1) = 3D allowedPOP PCM Out Path:

1 = 3D bypassed0 (1) = off

3D TI 3D Sound:1 = on

0 (1) = MixMIX Mono output select:

1 = Mic0 (1) = MIC1

MS Mic select:1 = MIC2

0 (1) = No LoopbackLPBK ADC/DAC Loopback:

1 = LoopbackDefault: 0000h


8.6.10 3D Control Register (22h)This read-only (0101h) register indicates, in accordance with the AC '97 Rev 2.1 Specification, the fixed depthand center characteristics of the TI 3D Sound stereo enhancement.

8.6.11 Power-Down Control / Status Register (26h)This read/write register is used both to monitor subsystem readiness and also to program the LM4549B power-down states. The 4 LSBs indicate status and 7 of the 8 MSBs control power down.




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The 4 LSBs of this register indicate the status of the 4 audio subsections of the codec: Reference voltage,Analog mixers and amplifiers, DAC section, ADC section. When the "Codec Ready" indicator bit in the AC LinkInput Frame (SDATA_IN: slot 0, bit 15) is a "1", it indicates that the AC Link and AC '97 registers are in a fullyoperational state and that control and status information can be transferred. It does NOT indicate that the codecis ready to send or receive audio PCM data or to pass signals through the analog I/O and mixers. To determinethat readiness, the Controller must check that the 4 LSBs of this register are set to 1 indicating that theappropriate audio subsections are ready.

The power-down bits PR0 – PR5 control internal subsections of the codec. They are implemented in compliancewith AC '97 Rev 2.1 to support the standard device power management states D0 – D3 as defined in the ACPIand PCI Bus Power Management Specification.

PR0 controls the powerdown state of the ADC and associated sampling rate conversion circuitry. PR1 controlspower down for the DAC and the DAC sampling rate conversion circuitry. PR2 powers down the mixer circuits(MIX1, MIX2, TI 3D Sound, Mono Out, Line Out). PR3 powers down VREF in addition to all the same mixercircuits as PR2. PR4 powers down the AC Link digital interface – see Figure 14 for signal power-down timing.PR5 disables internal clocks. PR6 is not used. EAPD controls the External Amplifier Power Down bit.

Table 18. Power-Down Control (26h)BIT# BIT Function: Status

0 ADC 1 = ADC section ready to transmit data1 DAC 1 = DAC section ready to accept data2 ANL 1 = Analog mixers ready3 REF 1 = VREF is up to nominal level

Table 19. Status Register (26h)BIT# BIT Function: Powerdown

8 PR0 1 = Power-down ADCs and Record Select Mux9 PR1 1 = Power-down DACs10 PR2 1 = Power-down Analog Mixer (VREF still on)11 PR3 1 = Power-down Analog Mixer (VREF off)12 PR4 1 = Power-down AC Link digital interface (BIT_CLK off)13 PR5 1 = Disable Internal Clock14 PR6 Not Used

External Amplifier Power Down15 EAPD

0 (1) = Set EAPD Pin to 0 (pin 47)Default: 000Fh If ready;otherwise 000Xh


8.6.12 Extended Audio ID Register (28h)This read-only (X001h) register identifies which AC '97 Extended Audio features are supported. The LM4549Bfeatures VRA (Variable Rate Audio) and ID1, ID0 (Multiple Codec support). VRA is indicated by a 1 in bit 0. Thetwo MSBs, ID1 and ID0, show the current Codec Identity as defined by the Identity pins ID1#, ID0#. Note that theexternal logic connections to ID1#, ID0# (pins 46 and 45) are inverse in polarity to the value of the Codec Identity(ID1, ID0) held in bits D15, D14. Codec mode selections are shown in the table below.

Table 20. Extended Audio ID Register (28h) Codec Identity ModePin 46 Pin 45 D15,28h D14,28h Codec Identity(ID1#) (ID0#) (ID1) (ID0) Mode

NC/DVDD NC/DVDD 0 0 PrimaryNC/DVDD GND 0 1 Secondary 1

GND NC/DVDD 1 0 Secondary 2GND GND 1 1 Secondary 3




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8.6.13 Extended Audio Status/Control register (2Ah)This read/write register provides status and control of the variable sample rate capabilities in the LM4549B.Setting the LSB of this register to 1 enables Variable Rate Audio (VRA) mode and allows DAC and ADC samplerates to be programmed through registers 2Ch and 32h respectively.

Table 21. Extended Audio Status/Control register (2Ah) FunctionsBIT FunctionVRA 0 (1) = VRA off (Frame-rate sampling)

1 = VRA onDefault: 0000h


8.6.14 Sample Rate Control Registers (2Ch, 32h)These read/write registers are used to set the sample rate for the left and right channels of the DAC (PCM DACRate, 2Ch) and the ADC (PCM ADC Rate, 32h). When Variable Rate Audio is enabled via bit 0 of the ExtendedAudio Control/Status register (2Ah), the sample rates can be programmed, in 1 Hz increments, to be any valuefrom 4 kHz to 48 kHz. The value required is the hexadecimal representation of the desired sample rate, forexample 800010 = 1F40h. Below is a list of the most common sample rates and the corresponding register (hex)values.

Table 22. Common Sample RatesSR15:SR0 Sample Rate (Hz)

1F40h 80002B11h 110253E80h 160005622h 22050AC44h 44100

BB80h (1) 48000 (1)


8.6.15 Vendor ID Registers (7Ch, 7Eh)These two read-only (4E53h, 4349h) registers contain TI's Vendor ID and TI's LM45xx codec versiondesignation. The first 24 bits (4Eh, 53h, 43h) represent the three ASCII characters “NSC” which is TI's Vendor IDfor Microsoft's Plug and Play. The last 8 bits are the two binary coded decimal characters, 4, 9 and identify thecodec to be an LM4549B.

8.6.16 Reserved RegistersDo not write to reserved registers. In particular, do not write to registers 24h, 5Ah, 74h and 7Ah. All registers notlisted in the LM4549B Register Map are reserved. Reserved registers will return 0000h if read.




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Line

Input

LM4549B$&µ97 Rev 2.1

Codec

LINE_IN_R24

LINE_IN_L23

LINE_OUT_L1.0 PF35

Line

Output

AVDD DVDD1

DVSS1 DVSS2

DVDD2

AVSS

Microphone

InputsMIC2

22

MIC121

CD

InputCD_GND

19CD_L

18

CD_R20

Video

Input VIDEO_R17

VIDEO_L16

Auxiliary

Input AUX_R15

AUX_L14

Mono

InputsPHONE

13

PC_BEEP12

BIT_CLK6

SDATA_OUT5

SDATA_IN8

SYNC10

RESET#11

XTAL_IN2

XTAL_OUT3

33 pF

33 pF1 M:

Z97

Digital

Controller

24.576 MHz

Analog

Ground

Digital

Ground

Connect Grounds at a single point

underneath or close to the package

+

LINE_OUT_R1.0 PF36 +

LNLVL_OUT_L1.0 PF39 +

LNLVL_OUT_R1.0 PF41 +

True Line Level

Output

1.0 PF37 +

MONO_OUT

VREF

3DN

VREF_OUT

+

0.1 PF 3.3 PF

27

28

3DP

33

340.022 PFOptional: for National 3D Sound

ID0#

ID1#

45

46

NC

NC

NC

NC

NC

NC

NC

NC

444342

38323130

NC

NC

NC

NC

NC

NC

NC

NC

26 4 7

NC

EAPD47

NC

NC Default setting: Primary

Codec (ID 00)

External Amplifier

Power Down

NC

Mono

Output

1 PF

25

+

0.1 PF

5V Analog Supply

1 9

All NC pins should normally

be left floating.

See Pin Descriptions for

details

VREF Output(For external microphone bias)

1.0 PF

1.0 PF

1.0 PF

1.0 PF

1.0 PF

1.0 PF

1.0 PF

1.0 PF

1.0 PF

1.0 PF

1.0 PF

1.0 PF

1.0 PF

++

++

++

++

++

++

+

AVDD

48

29NC NC

40

3.3V or 5V Digital Supply

1 PF

+

0.1 PF

See text for cap values


9 Application and Implementation

NOTEInformation in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.

9.1 Application InformationThe LM4549B is an audio codec used for PC systems. It is typically used in systems which are fully PC99-compliant and performs analog functions of the AC '97 Rev 2.1 architecture.

9.2 Typical Application

Figure 21. LM4549B Typical Application Circuit, Single Codec, 1-Vrms Inputs




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Typical Application (continued)9.2.1 Design RequirementsFor this example the following application parameters exist:• Single Codec Output• 1-Vrms input

This design is provided for a high-quality audio path and provides all analog functionality for a PC audio system.

The design has a single codec output with 1-Vrms input.

9.2.2 Detailed Design ProcedureFor all analog inputs a 1-uF capacitor should be tied to the input for proper decoupling. If the pin is unused thena 1-uF capacitor should be used and tied to ground.

For analog input pins, a proper lowpass filter will be needed to filter out any high frequencies depending on theapplication. Please see Figure 22.

Digital and Analog voltage supplies should have proper decoupling capacitors that cover low- and high-frequencyspikes. In this application, the user chooses to go with 1-uF and 0.1-uF capacitors.




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12

LM4549B

NC32

VREF_OUT

SYNC

SDATA_OUT

BIT_CLK

RESET#

SDATA_IN

12534

R5

6.81k

R24

47k

LNLVL_OUT_L

LNLVL_OUT_R

RESET#

3941

11

AVDD

25

+C16

1 PFC9

0.1 PF

AVSS

12534

J5

TRUE LINE LEVEL

JACK

J6

NC

R23

10k

C6

220 pF

C5

220 pF

R22

10k

++

C28

C29

1 PF

C7

220 pF

R4

2.2k

R2

47

SYNC10

SDATA_IN8

SDATA_OUT5

BIT_CLK6

26

31

EAPDMONO_OUT

4737

DVDD1

1

DVDD2

9

DVSS1DVSS2

PC_BEEP

LINE_IN_L

LINE_IN_R

CD_L

CD_GND

CD_R

AUX_L

AUX_R

MIC1

MIC2

VIDEO_R

VIDEO_L

PHONE

ID0#

ID1#

VREF

3DN 3DP XTAL_OUTXTAL_IN

+

33 34

C8 0.022 PF

2 3Y1

33 pF

R25

24.576 MHz

1 PF

LINE_OUT_LLINE_OUT_R

3536

NC

NC4038

NC42

1 M:

33 pFC1 C2

R1

0:AGNDDGND

+

15

28232418192014

161722

4645

13

27

21

74

NC43

C4

220 pF

R21

10k

+

C27

1 PF

C3

220 pF

R20

10k

+

C26

1 PF

0.1 PFC12

C13

3.3 PFC31

0.1 PF

12534

+

C18

1 PF

R6

6.81k

12534

+

C30

2.2 PF

R3

1k

+

C17

1 PF

R7

6.81k

+

C19

1 PF

R8

6.81k

J2

MICROPHONE

JACK

LINE INPUT JACK

J1

LINE_IN

LINE OUTPUT JACK

1234

J3

CD INPUT HEADER

1234

AUXILIARY INPUT

HEADER

R15

6.81k

+

C23

1 PF

R16

6.81k

R17

6.81k+

C24

1 PF

R18

6.81k

R11

6.81k

+

C21

1 PF

R12

6.81k

R13

6.81k

+

C22

1 PF

R14

6.81k

R9

6.81k

+

C20

1 PF

R10

6.81k

CD_IN

MIC1

LINE_OUT

LNLVL_OUT

J4

AUX_IN

PC_BEEP

U1

+3.3V

3VIN VOUT

1

2

U2

GNDC32C33

AVDDDigital

Supply

NC44

NC48

NC30

NC29

+7.5V - +20VLM78M05

0.33 PF

0.1 PF

Optional for LM4549B. Will improve transient response

Optional. Not required if LM78M05 is < 4 in. from an input

filtering capacitor

+

C25

1 PF

C141 PF

C11

0.1 PF

+


9.3 System ExampleIn Figure 22, the LM4549B is integrated into a system with a single code, 1-Vrms and 2-Vrms inputs, and EMCoutput filters.

Figure 22. LM4549B Reference Design, Typical Application

9.3.1 Improving System PerformanceThe audio codec is capable of dynamic range performance in excess of 90 db, but the user must pay carefulattention to several factors to achieve this. A primary consideration is keeping analog and digital groundsseparate, and connecting them together in only one place. Some designers show the connection as a 0-Ωresistor, which allows naming the nets separately. Although it is possible to use a 2-layer board, TI recommendsthat a minimum of four layers be used, with the two inside layers being analog ground and digital ground. If EMIis a system consideration, then as many as eight layers have been successfully used. The 12- and 25-MHz.clocks can have significant harmonic content depending on the rise and fall times. Bypass capacitors should bevery close to the package. The analog VDD pins should be supplied from a separate regulator to reduce noise.By operating the digital portion on 3.3 V instead of 5 V, an additional 0.5- to 0.7-db improvement can beobtained.




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System Example (continued)The bandgap reference and the anti-pop slow turnon circuit were improved in the LM4549B. A pullup resistor isnot required on VREF, pin 27. For an existing design, the 10-kΩ resistor can be left on the PCB, but thetemperature coefficient will improve with no resistor on this pin. In addition, the THD will improve by 0.2–0.5 dB.The external capacitor is charged by an internal current source, ramping the voltage slowly. This results in slowturn-on of the audio stages, eliminating “pops and clicks”. Thus, turn-on performance is also improved. Thepullup resistor, in conjunction with the internal impedance and the external capacitor, form a frequencydependent divider from the analog supply. Noise on the analog supply will be coupled into the audio path, withapproximately 30 dB. of attenuation. Although this is not a large amount if the noise on the supply is tens ofmillivolts, it will prevent SNR from exceeding 80 dB.

In Figure 21 and Figure 22, the input coupling capacitors are shown as 1-µF capacitors. This is only necessaryfor extending the response down to 20 Hz. for music applications. For telematics or voice applications, the lower3-dB point can be much higher. Using a specified input resistance of 10 kΩ, (40 kΩ typical), a 0.1-µF capacitormay be used. The lower 3-dB point will still be below 300 Hz. By using a smaller capacitor, the package size maybe reduced, leading to a lower system cost.

10 Power Supply RecommendationsThe LM4549B is designed to operate from an analog input voltage supply range between 4.2 V and 5.5 V.

The digital input voltage supply range is between 3 V and 5.5 V.

TI recommends connecting 1-µF and 0.1-µF decoupling capacitors in series on both the analog and digitalsupply pins.

11 Layout

11.1 Layout Guidelines• The LM4549B must be initialized by using RESET# to perform a Power-On Reset.• Don't leave unused Analog inputs floating. Tie all unused inputs together and connect to Analog Ground

through a capacitor (that is, 0.1-µF).• Do not leave CD_GND floating when using the CD stereo input. CD_GND is the AC signal reference for the

CD channels and should be connected to the CD source ground (Analog Ground may also be acceptable)through a 1-µF capacitor.

• If using a non-standard AC Link controller take care to keep the SYNC and SDATA_IN signals low duringCold Reset to avoid entering the ATE or Vendor test modes by mistake.

• The PC_Beep input should be muted if not used since it defaults to 0-dB gain on reset, unlike the mutedefault of the other analog inputs.




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12 Device and Documentation Support

12.1 Community ResourcesThe following links connect to TI community resources. Linked contents are provided "AS IS" by the respectivecontributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms ofUse.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaborationamong engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and helpsolve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools andcontact information for technical support.

12.2 TrademarksE2E is a trademark of Texas Instruments.All other trademarks are the property of their respective owners.

12.3 Electrostatic Discharge CautionThese devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.

12.4 GlossarySLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.




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PACKAGE OPTION ADDENDUM

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Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead finish/Ball material

(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

LM4549BVH/NOPB ACTIVE LQFP PT 48 250 RoHS & Green SN Level-3-260C-168 HR -40 to 85 LM4549BVH

LM4549BVHX/NOPB ACTIVE LQFP PT 48 1000 RoHS & Green SN Level-3-260C-168 HR -40 to 85 LM4549BVH

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide basedflame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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PACKAGE OPTION ADDENDUM

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Addendum-Page 2

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

LM4549BVHX/NOPB LQFP PT 48 1000 330.0 16.4 9.3 9.3 2.2 12.0 16.0 Q2

PACKAGE MATERIALS INFORMATION

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Pack Materials-Page 1


Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LM4549BVHX/NOPB LQFP PT 48 1000 853.0 449.0 35.0




TRAY

Chamfer on Tray corner indicates Pin 1 orientation of packed units.


Device PackageName

PackageType

Pins SPQ Unit arraymatrix

Maxtemperature

(°C)

L (mm) W(mm)

K0(µm)

P1(mm)

CL(mm)

CW(mm)

LM4549BVH/NOPB PT LQFP 48 250 10 x 25 150 315 135.9 7620 12.2 11.1 11.25




MECHANICAL DATA

MTQF003A – OCTOBER 1994 – REVISED DECEMBER 1996

1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PT (S-PQFP-G48) PLASTIC QUAD FLATPACK

4040052/C 11/96

0,13 NOM

0,170,27

25

24

SQ

12

13

36

37

6,807,20

1

48

5,50 TYP

0,25

0,450,75

0,05 MIN

SQ9,208,80

1,351,45

1,60 MAX

Gage Plane

Seating Plane

0,10

0°–7°

0,50 M0,08

NOTES: A. All linear dimensions are in millimeters.B. This drawing is subject to change without notice.C. Falls within JEDEC MS-026D. This may also be a thermally enhanced plastic package with leads conected to the die pads.

IMPORTANT NOTICE AND DISCLAIMERTI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements.These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources.TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products.TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2022, Texas Instruments Incorporated

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