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Linac 4 – LLRF electronics

BCC-35A.K. Bhattacharyya, A. Butterworth, F. Dubouchet,

J. Molendijk, T. Mastoridis, J. Noirjean(reporter), S. Rey,D. Stellfeld, D. Valuch, P.Baudrenghien

J.Noirjean /12.05.2011

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LLRF Cavity controller Servo loops Reference line Clocks Distributor module Tuner Loop module Cavity Loop module Switch and Limit module

Outline

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LLRF Cavity controllerEach Klystron driving one or more cavities has its own electronic system (one VME crate) in phase with its RF signal reference

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Servo loops – Tuner Loop

Tuner Loop keeps the structure on resonance

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Servo loops – Feedforward & Feedback loops

RF Feedback and Feedforward keep the accelerating voltage at the desired value in the presence of beam transient

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Servo loops – Klystron drive limiter

Klystron Drive Limiter prevents driving the klystron over the saturation limit during loop transients

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Servo loops – Klystron polar loop

Klystron Polar Loop compensates the variation gain across klystron/circulator and phase shift caused by High Voltage (HV) supply fluctuations and droop

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Reference line

Antenna

I

Q

Ref LinePhi Ref

Antenna'

RF Measurements relative to Phi Ref.

Cav Fwd

Cav Fwd'

Reference line

Return lineLoopback

Coupler

Reference and antenna cables to LL

Pha

se

dete

ctor

200W

am

plifi

er

Load

Tem

pera

ture

m

easu

rem

ent

LL c

rate

LL c

rate

LL c

rate

Reference phase correction distributed by the control system

1

1-5/8" cable7/8" stabilized cable7/8" cable

2 3 4 5

Thermometer

Legend:

Sur

face

L4 t

unne

l

thermometer busPhase shifter

Reference oscillator

Designer D.Valuch Some coupler properties- Coupling ~30 dB- Output RF level ~20 dBm

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Clocks Distributor module

Clock Generation

Designer

Date Version

PageTitle

John C. Molendijk BE/RF/cs

2010/03/26

EDA-0xxxx 1/4Overview

3.0source: G:\Departments\AB\Groups\RF\Machines\Linac4\LowLevel\Diagrams\ClockGenDistriv3.dsf

352MHz

999

9 10MHz to Cavity Controllers

Ref RF IN

RF OUTRF OUT Splitter

Front Panel

f/KADClk OUT ADClk OUT

ADClk / 4 OUT

LL RF Backplane

Splitter Fc OUT10 kHz

Fc OUT

10MHz IN 10MHz OUT

LO OUTLO OUTto Fdbk

LO OUTto TunerLO OUTto SwAp

50

50

50

Nim Distribution

f/4

DividersLinac4:SPL: N=32, M=31, K=8

N=16, M=15, K=4

Splitter

Frequencies:IF = 22.0125 MHzLinac4 LO = 330.1875 MHz SPL LO = 682.3875 MHzADClk = 88.05 MHz

Linac4 RF = 352.2 MHz SPL RF = 704.4 MHz

For LegacyCompatibility.

Via FrevBackplane

Count = 3once per 2048

14.3 ns

Via MHz40Backplane

Via MHz10Backplane

10MHz

352MHz 50 dBmReference line 50

Att

50

50

PhaseDetector

Ref. Phase Serial OUT

LO OUTVCOf/N

f/M22MHzLO

1 dc / CavityController

LO

ClockDistri Principle

SN65EPT20? (single)SN65EPT22 (double)

0 dBm

0 to 1 dBm4 way

0 dBm

0 to 1 dBm

100-800MHz

100-800MHz

Concept J.Molendijk ,Designer J.Noirjean/J.Lolleriou- Generates harmonically related clocks for the Digital

Demodulators- We have different versions for different systems (SPS

TWC800MHz, SPS TWC 200MHz, Linac4) LO Phase noise = 167 fs jitter(= 0.02 degree)

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Tuner Loop module

Designer J.NoirjeanMain electronics components:- Xilinx Virtex-5- ADI SHARC DSP, 400 MHz- 2 x 72 Mbit SRAM- 4 x Dual ADI ADC, 125 MSPS, 14 bit- 2 x SerDes transceivres, 1.5 GBps- Dual DAC, 125 MSPS, 14 bits- 8 x RF Front-end channels, ENOB 11.04 bits

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Tuner loop control / DTL2-3

Tuner Loop control acts on:- The tuner position- The phase shifter

(communication over Ethernet)

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Tuner loop control / DTL2-3

Tuner Loop control acts on:- The tuner position- The phase shifter

(communication over Ethernet)

Courtesy:N.Schwerg

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Cavity Loop moduleDesigner G.Hagmann- Module being designed for SPS

800MHz- Will be adapted for Linac4:

• Low latency digital chips(ADC’s,and DAC’s)

• Redesigned analog filters

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Cavity Loop control/PIM5-12

Cavity loop acts on:- The RF drive to regulate the field in the cavities- The phaseshifter to balance the hybrid, compensating for its asymmetry

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Cavity Loop control/PIM5-12

Cavity loop acts on:- The RF drive to regulate the field in the cavities- The phaseshifter to balance the hybrid, compensating for its asymmetry

Courtesy:N.Schwerg

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Switch & Limit module

Desiger G.Hagmann- Prevents from driving the klystron in

saturation- Entry point for the High power RF interlock- Adapted from SPS TWC 800MHz system

for Linac4 purposes

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Thank you for your attention