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pp. 617-624 617

Pietro BRAMBILLA ** Fausto FANTINI * Fabrizio MAGISTRALI ** Marco SANGALLI **

Life tests and field results of GaAs FETs

Abstract

The overall workplan for assuring the reliability of GaAs M~S~TS is presented, as a result of 10 years of industrial experience. The importance of an accurate evaluation of failure mechanisms and acceleration factors is pointed out, describing problems and criticalities related to the reliability testing and the failure analysis of this kind of devices. Finally, field data coming from our dynamic data base for system monitoring and surveillance are presented and discussed, demonstrating the satisfactory level of field reliability achieved during last years.

Key words : Metal semiconductor, Field effect transistor, Gallium arsenide, Lifetime, Reliability, Accelerated test, Failures.

en exploitation sont pr~sent~es et discut~es, d~montrant le niveau de satisfaction obtenu pendant ces dernidres ann~es.

Mots tits : Transistor effet champ, Barri&e Schottky, Gallium arstniure, Durte vie, Fiabilitt, Essai acctltrt, I~faillance.

Contents

I. Introduction. II. Samples and tests.

III. Failure mechanisms. IV. Accelerated test results. V. Conclusion.

References (18 ref.).

ESSAIS DE DURI~E DE VIE ET RI~SULTATS EN EXPLOITATION

POUR LES TRANSISTORS EFFET DE CHAMP AU GaAs

R6sum6

Cet article pr~sente un programme d'assurance de la fiabilit~ des transistors d effet de champ dt barridre de Schottky (MESFET) au GaAs, (labor( d partir d'une experience industrielle sup3rieure d dix ans. II souligne l'importance d'une ~valuation exhaustive des m~canismes de d~faillance et des facteurs d'acc~13ration des essais, et d(crit les probldmes critiques associ(s aux essais de fiabilit~ ainsi qu'dt r analyse des d3faillances sur ce type de dispositifs. En conclusion, les donn~es de jiabilit~ provenant de la banque de donn3es constitute

I. INTRODUCTION

GaAs microwave devices have strategic applications in telecommunication systems due to their well known advantages over silicon devices; during these last years, the better knowledge of the possible failure mechanisms, coming from the accelerated life tests, has led to substantial technological improvements, but the impact of these improvements on the operating reliability is not yet clear, owing to the lack of reports on field results.

This is a common problem for all semiconductor components; however the much larger quantity of silicon devices in field application makes the collection of data on their reliability more successful. In fact, a sound experience enables us to make realistic predictions on Si in-

* TELETrRA S.p.A. Quality and Reliability Dept., Via Trento, 30, 1-20059 Vimercate (Milano), Italy. ** Scuola Superiore di Studi Universitari e di Perfezionamento S. Anna, Via G. Carducci, 40, 1-56100 Pisa, Italy, also with University of Parma, Faculty of Engineering, Viale deUe Scienze, 1-43100 Parma, Italy.

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tegrated circuit reliability, based on accelerated life tests and established models, like those found in the MIL-HDBK 217E or in the CNET recueil des donndes de fiabilit&

The lack of a sound basis is of particular concern, because the activation energies, that are usually obtained in accelerated tests on GaAs rC~S~T devices, are quite high and enable extrapolation of very long lives, which can be over-optimistic. On the contrary, the sus- ceptibility of the devices to external stresses can cause many failures due to inaccurate applications, leading to pessimistic considerations on their reliability.

This paper reports the results of a comprehensive reliability evaluation of medium and high power MES~T devices, carried out during the last 10 years, that enables us to employ these devices with confidence also in high reliability applications. The phases of the evaluation may be summarized as follow :

1) in the first phase, only accelerated RF tests were performed; unfortunately, this approach did not enable us to reach clear conclusions because of difficulties in the test system, and therefore we had to widen the number and the type of tests;

2) in this second phase we started from the definition of the expected failure mechanisms on the basis of the previous experiences, of the existing literature and of the characterization of the samples, performed according to an internal specification. From these bases we prepared a test matrix designed to stress separately the various parts of the devices, in order to induce different degradations, This matrix was also used to assess the reliability of the captive production line of GaAs MESFET'S, which had been started in the meantime;

3) the third phase includes the reliability evaluation based on the tests performed according to the established programme. The data analysis was based on the lognormal distribution of the times to failure (TTF), in accordance with our experience on accelerated tests; the failure analyses of all the failed devices were performed;

4) the last phase was started at the same time of the beginning of the overall programme and comprehends data collection from the field and failure analysis of the field failures.

This collection of data is not limited to this specific class of devices but contains all the devices used in the company; a monthly-based summary shows the situation in the last time-interval and the progressive one; from these data the failure analysis of specific devices is decided and performed.

In the following the various phases will be described and main results highlighted.

II. SAMPLES AND TESTS

The examined devices were medium (0.25 W) to high (2 W) power MESFET'S, representative of the up-to-date technologies [1].

E BRAMBILLA. - LIFE TESTS AND FIELD RESULTS OF GaAs FETS

All the devices were produced by vapor phase epi- t a x y (VPE) Oil undoped GaAs substrates. Typical channel doping is about 1017/cm3 ; the channel thickness is ad- justed by a recess, obtained by chemical etch, in order to increase the breakdown voltage.

All the ohmic contacts are made by allowing Au- Ge-Ni, in general deposited by evaporation. Different metal systems for the Schottky-contacts are employed by the various manufacturers : the majority are gold- based, although aluminium also gave good results.

Also passivation varies : at the beginning various passivations or no passivation at all were employed; more recently mainly only silicon nitride (SIN) deposited at low temperature by plasma enhanced chemical vapour deposition (PECVD) has been used.

All the devices were packaged in standard metal- ceramic packages.

Much concem about the thermal stability of Schottky and ohmic contacts was found in the literature [2], therefore thermal-storage tests were designed up to the temperature of 250~ Higher temperatures were excluded due to the risk of inducing non-significative failure modes. An accurate evaluation of the actual channel temperature was also performed in order to correctly accelerate the different failure mechanisms. It was therefore neces- sary to know the thermal resistance of the devices : the electrical method, based on the temperature dependance of the forward I-V characteristics of the Schottky diode enables a mean channel temperature to be calculated and was used as a first tentative step. However, in operating conditions, or during accelerated life tests, the power dis- sipated in the active area leads to a non-uniform increase of the temperature. Unfortunately, the electrical method gives an unknown weighted average of the temperature distribution on the device and can be very inaccurate, in particular if a small area at high temperature exists within the structure [3]. The actual temperature distribution on the chip can be measured by liquid crystal techniques or directly observed by means of high late- ral resolution infrared (IR) thermography, which enables detection of thermal gradients due to local differences in the heat dissipation or to structural inhomogeneities [4]. From Figure l, that shows a device with thermal ano- malies due to gate misalignments, we can observe that temperature distribution is markedly non-uniform with a large temperature increase corresponding to each gate finger, while drain and source regions are much col- der. It appears that the electrical method underestimates (AT -- 10~ in the Figure) the actual temperature of

the active area. A second serious problem with III-V devices is the

lack of a good native passivation, that compels the use of various dielectrics, whose stability in contact with the GaAs surface is largely unknown. Besides the thermal stress humidity has also been employed to check surface stability; two kinds of tests are used : the standard 85~ RH with bias (TUB) and the more accelerated test performed in pressurized ovens at 130~ RH known as HAST (highly accelerated stress test).

The most delicate problems in performing these tests arised from the high temperature operating life (HTOL)

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P. B R A M B I L L A . - L I F E T E S T S A N D F I E L D R E S U L T S O F G a A s F E T S

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I-- < n,. u.J

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9 0

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operating in DC conditions, it is possible to develop tests addressed to single failure mechanisms, while both re- suits and acceleration factors are easier to analyze and to monitor. On the contrary, dynamic life tests normally involve different failure mechanisms occurring at the same time and leading to complete burn-out of the devices.

The control of stress conditions in order to avoid burn-out represents the most critical aspect also for DC tests and to this end our set-up features :

- - control of the stability of the operating point; - - protection against spikes during on/off switching

sequences; - - limitation of extra-currents; - - precaution against the possibility of forward gate

conduction; - - oscillation quelling at high as well as low frequen-

cies. Furthermore the set-up enables one to explore a wide

range of temperatures (up to Tamb = 200~ and to measure different type of MESFETS [5].

Figure 3 shows the test-fixture used for medium power devices.

FIG. 1. - - Example of a non-uniform temperature distribution in a MESFET.

Exemple de distrtbution non umforme dans un MESFET

tests. As mentioned, the first set of tests were performed using an RF signal superimposed on the bias; however, only RF power monitoring was possible and catastrophic failures (burn-out) were experienced, as shown in Figure 2 without any correlation to the stress conditions. Therefore we designed a test-fixture, which enabled us to perform DC biased tests, by simultaneously monitoring a series of parameters, that can give an early indication of the failure mechanisms.

We decided to use DC stress only, because RF operation does not seem to introduce further failure mechanisms, apart from catastrophic destruction induced by spurious RF spikes; this last, however, is more a problem of robustness than of reliability. Furthermore, by

FIG 2. - - SEM photograph of a device failed by bum-out.

Photographie obtenue par microscopie Electronique ~ balayage d'un dispositif dEMriorE par Echauffement destructif.

FIG. 3. - - Test-fixture for the biased life tests (HTOL).

Montage pour tests d'endurance sous polartsation (tests d'endurance de fonctionnement d haute temperature).

Together with the test-fixture, we developed an auto- matic measurement set-up, which enables the degradations of the following parameters to be followed :

a) Idss, 9rn and Vp ; where Idss is the saturation current measured with Vgs = 0, 9rn and Vp are transconductance and pinch-off voltage, respectively, to be calculated from device trans-characteristics.

b) Ideality factor (n) and saturation current (Is) extracted from the I-V curve of the gate-source diode under forward bias (to study interfacial degradation of Schottky contacts).

c) Breakdown voltages of the gate-source (and gate- drain) junctions (to observe surface degradations).

d) Resistance of the active device channel (R0) and those in series with the source (Rs), drain (Rd) and gate (Rg). Rs and Ro allow to monitor the degradation of ohmic contacts, R0 is used to characterize the interaction between the gate and the semiconductor in the channel region, while Rg provides information about electromigration of the gate metal stripes.

The determination of the resistances mentioned above is not trivial, particularly in power devices where they

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620 E B R A M B 1 L L A . - L I F E T E S T S A N D F I E L D R E S U L T S O F G a A s F E T S

can be as low as 0.2-0.4 Q. The main difficulties arise when trying to separate out the various contributions from the measured total resistance : Ron -- Re + R~ + Rd. To this end, the Fukui method [6] was used for device characterization, altogether is hard to apply to monitor device aging because critically dependent on fitting parameters that change considerably with device degradation.

The repeatibility of the measurements of all parameters (except R0) is better than 1%, thus ruling out any possibility of data misinterpretation.

In summary, the accelerated tests used in this study a r e :

a) High temperature storage (re's) without applied bias. For these tests ony one reference value of temperature (250~ was generally applied because the experiments do not give specific answers, although they are useful for accelerating diffusion processes active at the metal/semiconductor and dielectric/semiconductor inter- faces. In fact, this test can be mostly used to distinguish the pure thermal contribution to the failures.

b) High temperature operating life (nToe) : different temperatures are considered in conjunction, with electrical conditions similar to those experienced by the device during normal operations, with the purpose of studying the combined effects of thermal and electrical stresses.

c) High forward gate current (nFGC) : the gate junction is forward-biased in order to investigate the effects of high current densities (at high temperatures).

d) High temperature reverse bias (HTRB) : the gate junction is biased close to breakdown, to observe the cumulative effects of high electric fields and temperatures.

e) Temperature humidity bias (THB) and highly accelerated stress tests (HAST) : in these type of experiments the gate is reverse-biased to analyse the effects of humidity directly on the chip and the protection capability of the package.

The effectiveness of these tests in characterizing the various failure mechanisms are schematically indicated in Table I.

HI. FAILURE MECHANISMS

In operating conditions the most frequent failure mode is a complete destruction of the device known

as bum-out. Different reasons were found for the oc- currence of this phenomenon, including GaAs surface degradation [7], ohmic metal electromigration accross the surface between drain and gate [8], or hot-electron injection [9].

We tried to separate the various failure mechanisms, avoiding catastrophic degradation, in order to study them separately; however, we have to point out that we were not able to generate some of the expected failure mechanisms, in particular the degradation of ohmic contacts.

Indeed, despite the fact that many authors in the past have reported decreases in saturation current and increase in contact resistance after thermal treatment or operating life tests [10], we observed these degradations very rarely. As a representative example, during an operating life test at Tch = 260~ on 21 devices, we experienced series resistances degradation limited to less than 5%, ruling out both interdiffusion and electromigration effects. Only in one case we did observe clear electromigration effects in the drain contact, due to a poor Au thickness [11].

On the contrary, electromigration seems to be the main failure mechanism in the case of Al-gate devices; in fact current densities of the order of 105 A/cm 2 can be reached by the gate current during normal operation in power devices, when RF signal drives the gate junction on. In order to study this phenomenon we used a very accelerated test, where a forward current up to l0 s A/cm 2 was forced through the Schottky junction at high temperature (200~ [12].

The degradation can be followed during the test by measuring the minimum drain current, Idso, which can be achieved by increasing the reverse gate bias at a fixed drain voltage (Vds = 3 V in this case). Figure 4 reports Idso as a function of the test time for two typical sam- pies. The loss of control on the drain current is due to the opening of the device gate fingers caused by electromigration. Gate interruptions can be easily identified in SEM-EBIC (electron beam induced current) images of the Schottky gate junction, obtained by collecting the signal between gate and source/drain. Figure 5c reports the EmC image of a failed device after 2000 hours of forward gate current test. Electron beam induced current cannot be collected from those parts of the gate Schottky diode which are beyond the metal interruption, and therefore appear dark in Figure 5c. The SEM micrographs of

TABL. I. - - E f f e c t i v e n e s s o f the accelerated test for studying the different failure mechanisms. EfficaciM des tests acc~l~r~s pour l'(tude des m(canismes de d~faillance.

Test Surface Ohmic contact Schottky junction Gate Corrosion degradation degradation degradation electromigration

HTS "k * -k "k -k

HTOL * * * "k *

HTRB * * * *

THB/HAST -k -k * -k

ANN TI~LI~COMMUN., 45, n ~ 11-12,-1990 4/8

P. BRAMBILLA. - LIFE TESTS AND FIELD RESULTS OF GaAs FETS 621

FIG. 4. - - Degradation of Idso during the H~6C test; the inserts demonstrate the incapability of the device to pinch-off.

DEgradation de Idso au cours des essais sous courant de grille direct intense; les insertions dErnontrent que le dispositif ne peut Etre pinch.

SUPPLIER A Tch = 185 ~ Au 0 43

�9 B, Tch = 208 ~ A u o

-~O " C T c h = 215~ A t

- 2 0

- 3 0

"o D Tch = 171 ~ Au - 4 0

- 5 0

60 "% LIFE TEST

70 Tcase = 150~

I I I I I r I I

] 2 3 4 5 6 7 8 9 10

T I M E ( 1 0 3 h o u r s )

FIG. 6. - - Summary of the ldss degradation during HTOL tests for devices with different gate technologies.

REsumE des degradations de ldss au cours des essais d'endurance de fonctionnement d haute temperature pour des dispositifs dt technologies

de grille diffErentes.

R0. The main failure mechanism was the interdiffusion of Au into GaAs. The phenomenon seems to be pu- rely thermally activated and to affect channel proper- ties through two mechanisms : one is the advancement of the metal/semiconductor interface into the channel, thereby decreasing the effective channel thickness (ga te s i nk ing ) ; the other is the doping of the semiconductor by the diffused metal atoms, with alteration of the net donor density in the channel : Au and Ti are reported to compensate donor density in the channel.

In order to confirm the first hypothesis, that was originally derived from analysis of the in-depth Auger profiles o f failed devices [ 13], we used an original failure analysis technique, that we called back-etch [14].

This technique enables us to expose the metal semiconductor interface by means of the chemical etch of the semiconductor substrate; Figure 7 compares the ap-

FI~ 5. - - Comparison of the EalC signals before (b) and after the test (c) for the MESFET shown

in the SEM photograph (a).

Comparaison du signal de courant induit par faisceau d'Electrons avant (b) et aprds (c) test pour le MESFET montrE sur la photographie

obtenue par microscopie Electronique d balayage (a).

the gates corresponding to the dark areas, confirm the presence of voids in the A1 fingers.

During the same kind of test a variation in the Schottky barrier height was also experienced in the first test hours. However this variation does not seem to affect the long term stability of the devices [12].

By comparing A1 and Au-based gates, we can see in Figure 6 that in accelerated life tests the first compare quite favourably : a large spread of results was obtained on Au-based devices due to the large differences in the used technology, and in particular the kind of barrier metals employed between Au and GaAs.

In the Au-based devices the dominant failure mode was the decrease of /ass and Vp and the increase of

FIG. 7. - - Comparison of a virgin (a) and a degraded (b) device, obtained by the back-etch technique.

Comparaison entre un dispoMtif vierge (a) et un dispositif dEgradd (b) aprds attaque en retour.

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pearance of a virgin (a) and a failed (b) device, where large Au grains. 300-500 #m wide, can be observed. Au grain formation takes place because of the solid state diffusion of Au through the Ti barrier layer, thus redu- cing the effective channel height, that causes Ids8 and Vp to diminish and R0 to increase.

The effectiveness, of the interdiffusion barrier de- pends on the choice of materials, their thickness and their impurity content (in particular oxygen and nitro- gen), but owing to the small dimensions of gate fingers, defects and inhomogeneities can play a major role in de- termining of the long-term stability of the contacts [15].

In particular, thermal gradients along gate fingers enhance interdiffusion effects in localized device areas, and structural inhomogeneities at the borders of the gate can reduce the effectiveness of the barrier.

Surface effects include the ga te - lag effect, metal migration and semiconductor erosion, the last two being particularly enhanced in high humidity conditions.

The ga t e - l ag effect limits high frequency perfor- mances and is associated with the presence of slow surface states in the region between gate and ohmic contacts [16] : a standard technique to reveal these effects is to measure drain current response to a large square wave modulation applied to the gate. Also transconductance dispersion and breakdown voltage are indicators of the presence of slow states, although their effect is not fully understood.

A more serious concern appears to be the metal migration accross the GaAs surface (under the passivation), induced by the high field present between gate and drain electrodes [8] ; usually migration is from positively (drain) to negatively (gate) biased metals, is strongly temperature-dependent and causes breakdown reduction finally leading to short-circuit, as shown in Figure 8.

In the case of very high humidity we observed also GaAs dissolution, with loss of material; the phenomenon was detectable by EDS (energy dispersive spectroscopy) in the SEM and this indicates that the chemical reaction is deeply extended [17].

FIG. 8. - - SEM photograph of a localized short circuit.

Photographie obtenue par microscopte (lectronique dt balayage d' un court-circuit localisL


IV. ACCELERATED TEST RESULTS

The most effective test for lifetime prediction is the HTOL, essentially because it involves conditions close to those experienced by the device during its life.

As for data analysis, the most widely used lognormal distribution is supported by substantial experimental evi- dence in the case of GaAs MESFETS. For this reason, our analysis is based on the assumpion of lognormal distribution, checked by means of experiments continued until failure of all the devices is reached. The results reported here refer to medium-power MESFETS manufactured with standard gold-based technology; all the samples came from the same production lot. Figure 9 shows the cumulative failure distribution obtained in 4 life tests performed at ambient temperature in the range 70~ - 125~ for nearly 20,000 hours.

98 - %Failures

T=230"C T=210"C

~ 0 7O

T=195"C 0 / / / > Q

zo T=175"C

IO * / +~/^ ^/

i I I I I I 10 100 IK 10K 100K 1M

Time [h] FIG. 9. - - Lognormal plot of the TTFS for HTOL performed at 4 temperatures (values refer to channel temperature).

Courbe en lognormal du temps de fonctionnement sans panne au cours des tests d'endurance de fonctionnement dl haute tempHature

pour 4 tempHatures.

The choice of the test temperatures comes from a trade-off between the need to have, simultaneously, results in reasonable time and small uncertainties when extrapolating the data at real operating conditions.

To deal with these problems, we selected a temperature range close to real operating conditions, even though this inevitably leads to longer test time.

By means of electrical measurements and physical examination, the failure mode was found to be an increase in the gate leakage current eventually leading to a localized short circuit similar to that shown in Figure 8. The origin of the leakage is probably in the defective areas at the semiconductor surface (passivated with PECVD SiN) or in protrusions in the metallizations (possibly due to the lift-off process). The presence of a detect-related phenomenon is also confirmed by the large dispersion (~r = 2) of the lifetimes found in all tests, that contrasts with the narrower value typical of wearout mechanisms in homogeneous samples; the failure analysis enabled us to rule out the possibility that

ANN. TF~I~!COMMUN. 45, n ~ 11-12, 1990 6/8

E BRAMBILLA. - LIFE TESTS AND FIELD RESULTS OF GaAs FETS 623

" lam b

[1000/K]

26

2.8

3.0

3.2

3.4

n

\

16eV

10 I K 100K 10M 1G

Time [h] FIG. 10. - - Arrhrenius plots from the data of Figure 9.

Courbes d'Arrh~nius trac~es ~ partir des donn~es de la figure 9.

['C]

_ 125

_ 105

_ 90

_ 70

30

10013

the large value of ~r is due to the cumulative effects of different failure mechanisms.

As shown in Figure 10, our data allow to extrapolate a value of the median time to failure, MTF = 1.8 • 108 h at Tamb = 30~ with an activation energy Ea : 1.6 eV, in excellent agreement with recent results [18], even though the failure mechanisms seem to be different.

The rather high value of Ea is not unexpected in GaAs devices and it is also important that it has been obtained from experiments performed at lower temperatures than in previous works, which makes it particularly reliable.

In spite of all these precautions, the possibility that the real activation energy at room temperature is lower than 1.6 eV carmot be completely ruled out. In fact, as shown in Figure 10, the Arrhenius plot might present two different slopes, with the part at lower temperatures exhibiting an activation energy of 0.5 eV. If this were the case, a conservative prediction of MTF at 30~ could be obtained in the range of 9 • 10 n h.

From these extrapolations, the expected failure rate under normal operating conditions can be easily calculated. As shown in Figure 11, we obtain a maximum value A < 10 fit in 25 years using Ea = 1.6 eV and A < 2,000 fit for the most conservative case featuring two activation energies.

These estimates can be compared with the data obtained from field repairs by means of a dynamic data base for system reliability monitoring.

The results of this analysis on MESFET failure rates, updated at the end of 1989, are reported in Figure 12, where the points represents the 90% UCL (upper confidence level) for the estimates of the failure rate, calculated on a yearly basis. These data refer indeed to all the removed parts, and are therefore a r e m o v a l rate , however extensive failure analyses were performed in order to discriminate intrinsic from systematic failures induced by design or manufacturing of the equipment; the results of the failure analyses show that more than 90% of the

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100

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PIG 11. - - Failure rate at 30~ obtained from the data of Figures 9 and 10.

Taux de d~faillances ?t 30~ obtenus d partir des donn~es des figures 9 et 10.

x 10 -9 h

400

200 i I

1984 1985 1986 1987 1988 1 9 8 9

FIG 12. - - Removal rate in field of MESFET devices during last 6 years.

Taux de retrait de dispositifs MESFET au cours des 10 dernidres ann~es.

removals were real failures, the only failure mechanism being destructive bum-out; it should be noted anyway that RF operation p e r se leads to burn-out, whatever the real failure mechanism, and that, as already mentioned, external causes may lead to burn-out too.

V. C O N C L U S I O N

Our 10 years experience in the application of dis- crete GaAs MESFETS devices enables us to conclude that their field reliability, even though worse than that of silicon devices, can satisfy the requirements for telecom systems; this fact is of particular importance, especially considering that our results take into account both internal and external causes and that the total quantity of high power devices, more critical for the reliability, has been rapidly increasing in the last years.

Even if burn-out is much the most common failure mechanism experienced during real operating conditions, the accurate reliability program, with the aim

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of defining appropriate technological improvements and screening techniques, showed itself of the highest importance; besides, knowledge of the effects of the different stresses gives more confidence in the possibility of extrapolating lifetimes from accelerated tests.

From our experience, and from the literature, quite high activation energies are expected, thus avoiding the need for very high stresses, which can induce spurious failures. From the comparison between the failures obtained in field and from accelerated tests, we can conclude that GaAs surface is the most critical aspect for reliability, so that efforts should be addressed towards impro- ving surface preparation and composition, and definition of the passivation layer.

ACKNOWLEDGMENTS

The authors want to acknowledge the colleagues of the Quality and Reliability Dept., and in particular G. Muzzin, D. Ogliari, L. Umena and M. Vanzi. Part of this work was supported by the Italian CNR under the Project Madess.

Manuscrit refu le 24 juillet 1990, accept~ le 6 septembre 1990.

REFERENCES

[1] BRAMBILLA (P.), FANTIN~ (E), GUARINI (G.), MATTANA (G.), PIACErZnNI (G. E). GaAs MESFET technology and reliability aspects. Alta Frequenza (1986), 55, n ~ 3, pp. 81-93.

[2] PALMSTROM (C. J.), MORGAN (D. V.). Metallizations for GaAs devices and circuits. Gallium arsenide. Materials, devices and circuits, edited by M. J. Howes and D. V. Morgan, John Wiley & Sons (1985), pp. 195-261.

[3] WEBB (E W.). Measurements of thermal resistance using electrical methods. IEEE Proceedings-Part I (1987), 34, n ~ 2, pp. 51-56.

[4] CANALI (C.), CHIUSSI (E), DONZELLI (G.), MAGISTRALI (F.), ZANOM (E.). Correlation between thermal resistance, channel temperature, infrared thermal maps and failure mechanisms in low power MESFET devices. Microelectronics and Reliability (1989), 29, n ~ 2, pp. 117-124.

[5] CANALI (C.), CrmJssi (E), FANTIM (E), MUZZ~ (G.), UMENA (L.). Test fixture for MESFET reliability life tests. Microelectronics and Reliability (1987), 27, n ~ 5, pp.897-911.

[6] FuKta (H.). Determination of the basic device of a GaAs MESFET. Bell System Technical Journal (1979), 58, pp. 771-797.

[7] WEMPLE (S. H.), NmHAUS (W. C.), ~ L q (H.), IRVIN (J. C.), Cox (H. M.), HWANG (J. C. M.), DI LORENZO (J. V.), ScrEos- SER (W. O.). Long term and instantaneous bum-out in GaAs power FET'S : mechanisms and solutions. IEEE Trans. Electron Devices (1981), 28, n ~ 7, pp. 843-840.

[8] KR~TSCHMER~ (K. H.), HARTNAOEL (H. L.). Interelectrode metal migration on GaAs. IEEE Proceedings Reliability Physics (1987), 25, pp. 102-106.

[9] BUOT (F. A.), ANDERSON Jr (W. T.), CHRISTOU (A.), CAMP- BELL (A. B.), KmrosoN (A. R.). A mechanism for radiation- induced degradation in GaAs field-effect transistors. J. Applied Physics (1985), 57, n ~ 2, pp. 581-593.

[10] DRUrmR (I.), SrLCOX Jr (J. E). On the reliability of power GaAs FETS. IEEE Proc. Reliability Physics (1979), 17, pp. 150-155.

[11] CANALI (C.), CHIUSSI (F.), FAN'n~ (E), UMENA (L.), VANZI (M.). Electromigration effects in power MESFET rectifying and ohmic contacts. Electronics Letters (1987), 23, n ~ 8, pp. 364-365.


[12] CANALI (C.), FANT~ (E), SCORZONI (A.), UMENA (L.), ZANONI (E.). Degradation mechanisms induced by high current density in Al-gate GaAs MESF~TS. IEEE Trans. Electron Devices (1987), 34, n ~ 2, pp. 205-211.

[13] CANALI (C.), CASTALDO (F.), FArCrINl (E), OGLIARI (D.), UMENA (L.), ZANONI (E.). Gate metallization sinking into the active channel in Ti/W/Au metallized power MESFET'S. 1EEE Trans. Electron Device Letters (1986), 7, n ~ 3, pp. 185-187.

[14] FANTE~ (E), MAGISTRALI (E), OGLIARI (D.), SANGALLI (M.), VANZI (M.). Back-etch : an effective tool for characterization and failure analysis of MESFET devices. Proceedings of the In- ternational Symposium on testing and failure analysis (1988), pp. 235-241.

[15] CANALI (C.), DONZELLI (G.), FANTINI (F.), VANZI (M.), PACCA- GNELLA (A.). Gold-based gate-sinking enhanced by inhomogeneities in power MESFETS. Electronics Letters (1987), 23, n ~ 2, pp. 83-84.

[16] DUMAS (J.-M.). Parasitic effects and degradation mechanisms of GaAs integrated circuits. Proceedings of the 4th International Conference quality in electronic components (1989), pp. 120-127.

[17] MAGISTRALI (E), OGLIARI (D.), SANGALLI (M.), VANZI (M.). De- gradation mechanisms of GaAs MESFET devices in high humidity conditions. Proceedings of the International Symposium on testing and failure analysis (1989), pp. 141-151.

[18] PETERS (M. E), ROESCH (W. J.), RUnALCAVA (A. L.). Studying lifetimes and failure rates of GaAs MMICS. Microwaves and RF (1988), n ~ 7, pp. 99-107.

BIOGRAPHY

Pietro BRAMBILLA received the degree in Electronic Physics in 1970 from the University of Milano, Milano, Italy. In the same year he joined the Component Laboratories of Telettra SpA in Vimercate (Milano), working on thin film deposition and Ta capacitor design and manufacturing. In 1975 he moved to the Quality and Reliability Department, working on passive component reliability; in 1980 he become responsible for semiconductor device reliability and, since 1987, he is responsible for all Q and R activities on components and processes. He is a member of IEEE.

Fausto FANTINI graduated in Electronic Engineering in 1971 from the University of Bologna, Bologna, Italy. In 1973 he joined the Quality and Reliability Department of Telettra SpA in Vimercate (Milano), where he worked on the reliability of semiconductor devices and established the laboratory of failure analysis; from 1979 to 1987 he was responsible for the Q and R of the plant in Bologna. In 1987 he was appointed Associate Professor of Electronics at the Scuola Superiore di Studi Universitari e di Perfezionamento S. Anna in Pisa and, since then, he is teaching a course of Technology of Solid- State Devices. In 1990 he became Full Professor of Electronics and has been called to cover the chair of Microelectronics at the University of Parma. His research interests include various aspects of semiconductor-device physics and reliability. He has authored or co-authored 2 books and over 80 research articles and international-conference papers and organized two summer schools on failure physics (1980 and 1987). He is a member of IEEE, ISHM, AICQ (Italian Association for Quality) and SIF (Italian Physical Society), and of the Technical Committee of various International Conferences.

Fabrizio MAGISTRALI graduated in Electronic Engineering from the University of Pavia, Pavia, Italy, in 1983. In 1984 he joined the Quality and Reliability Depaaanent of Telettra SpA in Vimercate (Milano), being involved firstly on the reliability assurance of fiber- optic active devices; in 1986 he became responsible of the group working on the reliability of compound semiconductor devices, including both fiber-optic and microwave components. His main interests are in the field of degradation phenomena of active devices; he is also active in international standardization activities on fiber-optic devices and is a member of the IEEE and of the Italian Electrotechnical Association (AEI).

Marco SANGALLI graduated in Physics from the University of Milano, Milano, Italy, in 1987, with an external thesis at the Electrochemical Institute of the National Research Council (CNR) on electrolythic cells with solid/liquid interface. He joined firstly SGS-Thomson Microelectronics in Agrate B. (Milano), Italy, working on resist processes and then, in 1988, the Quality and Reliability Department of Telettra SpA in Vimercate, where he is presently involved in the reliability evaluation of GaAs microwave devices. His main interests are in the development of computerized testing systems and failure analysis techniques.

ANN. T~EL~COMMUN., 45, n ~ 11-12, 1990 8/8

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