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ECE 271 Electronics Lecture Notes, Lesson Four

Key Lecture Concepts for CoE225/EE 271 (Mostly Digital Electronics) by R.H.Cornely,

Sept. 27, 2005 All Copyrights Reserved

LESSON FOUR: The MOS Field-Effect Transistor (MOSFET); MOSFET

Circuit Analysis Examples; Logic Circuit Concepts: Voltage Transfer

Characteristics, Noise Margins and Digital Gain; Introduction to theDynamic Response of Logic Gates. Appendices: Characteristics of other FET

Devices; Introduction to the Properties of Semiconductor Materials; the MOS

Transistor (MOSFET); Review of the Historical Development of Computer

Hardware and the Need for Three-Terminal Devices.

Lesson Overview: A major goal of this course is to develop an understanding of how

computers work from a hardware point of view. Digital signals lose amplitude and their riseand fall times become worse, as they propagate from the inputs to the outputs of a digital

system on the conductors between devices that perform logic and memory operations.

Therefore it is necessary to regenerate the signals by providing digital signal

amplification, or digital gain. It is also necessary to prevent signals intended to propagate

towards an output of a digital system from propagating back and influencing other signals,

introducing errors. A three-terminal device is necessary to provide this isolation of input and

output signals, ordirectionality of signal propagation. The MOS transistor has proven to

be an outstanding device for providing these two requirements of digital logic circuits,

digital gain and signal directionality. Of great significance is that the millions ofMOS

transistors required for computer logic and memory can be mass-fabricated on the

surface of low cost silicon material.

A major learning objective of the lesson, presented in section A, is to be able to

understand the I/V characteristics of the MOS field-effect transistor {MOSFET). The

MOSFET is a three-terminal device consisting of a control gate terminal whose voltagecontrols the flow of current between the two other terminals, the source and the drain .

Two current-voltage (I/V) characteristics are necessary to describe the operation of the FET.

One is the dependence of the output current as a function of the voltage difference between theinput gate and the source. The second is the dependence of the output current on the voltage

between the two terminals that the output current flows between (the drain and the source).

The junction field-effect transistor is a device with similar I/V characteristics of the

MOSFET. It is described in Appendix 4.1. To further understand the objective of the

lesson the first paragraph of the Summary in Section G should be read.

The lesson objective of section B is to introduce basic MOSFET circuits with a resistor as

the load for either p or n-channel MOSFET. For digital circuits the MOSFET serves as a

switch and for analog circuits it amplifies small ac signals between the gate input and thesource. The load serves to isolate the output terminal from the power supply used for the

source drain voltage drop necessary to obtain current. Actual MOSFET circuits used

MOSFET loads; the resistor load in this lesson is used for tutorial purposes only. Amathematical as well as a graphical, or load line, approach for finding the Q points of these

basic circuits will be shown. Then the important logic circuit concepts of the voltage

transfer characteristic (output circuit voltage versus input voltage), digital gain (the

change in output voltage for a change in input voltage), fan-out and fan-in capability,

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propagation and pair signal delay times, and the power-delay time product will be

introduced.

The lesson concludes with a concise description of noise, i.e. undesirable coupling of

voltages and currents from one wire to another nearby wire. The electromagnetic

phenomena causing the signal coupling will be described by sketches that show that the complexelectromagnetic pickup of noise signals onto wires and device terminals can be accounted for

by capacitance and inductance that provide a simple model for the electromagnetic phenomena.

The lesson explains how the effects of the unwanted noise can be minimized by designing a

digital circuit so that the output versus input voltage transfer characteristic will have a

noise margin that protects against the noise signal causing an error, e.g. the output

becoming a one when it should be a zero. Some discussion of the minimization of noise by

optimizing the layout of wires connecting the devices is given.

There are three appendices at the end of the lesson that would be nice to study in ECE 271, except

that study time for many students is limited. Appendix 4.1 presentsthe terminal current/voltage

characteristics for other types of FET devices such as the JFET and MESFET. They arepractically the same as those for the MOSFET. You will need the JFET equations for other

courses. Appendix 4.2 offers a review of the basic properties of semiconductors as

background to understand how the MOSFET characteristics depend on material properties

and FET structure and dimensions. However, it is possible to learn how to design and

analyze digital circuits starting with the FET characteristics without learning the device

physics, material science, and manufacturing techniques on which the characteristics

depend. Therefore it is optional during this course to learn the basic subjects presented in

appendix 4.2. You are encouraged to read appendix 4.2 at least once to get a feeling for the

subject and to study the concepts in A-4.2 in the near future. The knowledge of semiconductordevices will enable you to follow and anticipate the exciting developments of the components and

systems that will be the heart of future generations of not only computers but also many otherimportant solid state products such as sensors, displays, miniature robots, laser beam switches, and

novel every-day products as watches, vehicle components, and medicines whose low-costproduction is based on solid state technology.

Appendix 4.3 expands on the first paragraph of this overview by presenting a brief review

of the history of computer hardware. This historical overview outlines how electronics

technology evolved over the last 6 decades. It should be read as a news article and not studiedbecause of your limited time. The section aims to give you an appreciation of the microelectronic

devices and circuits that will be studied in the upcoming lessons and those that will be part of

technology in the coming decades.

A) Basic Concepts for the Metal-Oxide-Semiconductor Transistor (MOST)

There are four basic types of MOS transistors: N-type EMOS; P-type EMOS; N-type

DMOS; and P-type DMOS. Column one offig4.1 lists the four transistor types. Also inthis column are the key parameters for each device, the threshold voltage, VT, the gain factor,

K, and the width to length ratio, W/L. Typical values for 2005 for each parameter also are

given under each name. These parameters completely determine the device I/V characteristic,just as IS and nVT did for the diode. Unlike the diode, which has a single I/V curve, the three-

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terminal MOST is described by two I/V characteristics. The transfer characteristic, which is

sketched in column 3, and the drain characteristic, sketched in column 4. Before discussing in

more detail these important characteristics, we will review basic concepts for electricalconduction, usingfig4.2 and then look at the structure of a transistor as presented infig4.3 and

discuss briefly the physical operation of the device.

The basic concepts for conduction in semiconductors are presented infig4.2.As listed in the

bottom half of the page, there are 4 types of charges in semiconductors. The mobile

negative charge (electrons) and the mobile positive charge (holes) provide the carriers for

current due to applied voltage. The two other charges are fixed, i.e. immobile. They are

the doping atoms that provide the mobile carriers. Donor doping atoms provide (or

donate) mobile electrons. Acceptor doping atoms provide the mobile plus-charge holes.

The symbols for the four charges are used in e.g.fig4.4 to explain the structure and operationof MOSFETs. Appendix 4.2 presents in more detail the generation and conduction processes in

semiconductors. A brief summary is the following and does not have to be learned until the

other concepts of this lesson are mastered. {Holes actually are due to electrons that jump

between vacancies in the electronic bonding structure of the acceptor atoms. An electronwill jump from a position in the bond structure towards the right into a vacancy in the bonding

structure if an electric field points to the left. When the electron jumps to the right, it leavesbehind a vacancy on the left. Thus the motion of the electron to the right, opposite the electric

field, results in the vacancy moving to the left. This vacancy motion to the left is equivalent to

positive charge moving to the left. Thus the motion of the electrons appears as a positivecharge moving in the direction of the electric field. (Actually doping atoms (dopants) at very

high temperatures, e.g.1000 degrees centigrade, do move from a high concentration to a lower

concentration of dopants; this high temperature diffusion motion is necessary to put them into

the silicon material! However, for understanding the operation of transistors at normal it isconvenient to consider the dopants to be immobile.)}

Silicon that has mainly donor atoms added to pure silicon material is called N-type silicon.

Silicon that mainly has acceptor atoms added to the host silicon atoms is called P-type

silicon. P refers to the resultant mobile positive charge and N to the resultant mobile negative

charge. Equation one infig4.2, presented also below, gives the dependence of the resistance(R) of a sample of semiconductor material on its resistivity and dimensions {width W,

thickness t, and length L}. Fig4.2 also shows the current and electric field directions inresponse to a voltage, V, across the material and the motion of any holes or electrons in the

material. The equations that relate the mobility of carriers and their concentration in

either N or P type semiconductor material to the conductivity of the material, , are next toequation. Note that = 1/ and q is the electron charge, 1.6 10 19 [coul].1) R = [ohm-cm]L[cm] W [cm] t [cm] { = q N n = 1/ P = q P p = 1/P }Table 4.1, afterfig4.2, is provided to give the reader a feeling for the resistivity values forcommonly used metals, semiconductors and insulators. Equation 1 applies to all

materials, of course. This amazing wide range of resistivity, 1023, is very helpful in the

design of devices and circuits for the microelectronics, power/energy, microwave etc.

industries.

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Besides N and P type semiconductor material there is intrinsic material which has basically

only the host atoms, e.g. silicon, and is relatively non-conductive. It has a large resistivity,

, of about 1000 ohm-cm. at room temperature (2930K).Table 4.2 lists the types of charges, typical doping concentration ranges, and corresponding

resistivity and conductivity values for the 3 types of silicon material. The typicalconcentration values for doping atoms are much smaller than the concentration of the host

atoms in silicon, 5 times 1022 [cm 3]. Also given are values for the mobility of electrons and

holes, andP. The units for mobility by dimensional analysis are cm2 per volt-sec.Fig4.3 shows the major features of the structure of an N-MOST transistor. As shown infig4.3a, a MOSFET is composed of a MOS capacitor-like sandwich which has a highlyconducting metal gate (G) serving as the top plate. This metal plate is typically 1000 to

10,000 Angstroms (A) thick. Under the top plate, is a very thin insulating oxide layer (from

20 to 500A thick). The relatively thick semiconductor silicon substrate (typically about 200

to 500 m) serves as the bottom plate. [Recall that 3 to 4 A is the distance between atoms,that one micron is 10,000 A, and that a human hair is 50 to 100 microns thick. It issuggested that colored pens be used to color the metal regions e.g. blue and the more

conducting semiconductor source and drain regions in the semiconductor red so that they

stand out.] Looking at the cross-section, note that charge or current can not go from the

gate terminal to the semiconductor because the gate metallization is separated from the

silicon substrate by the highly insulating, non-conducting oxide. The two conducting

regions, the metal gate and the semiconductor substrate serve as the plates of a

capacitor, with the highly insulating region between the plates usually an oxide, grown by

heating a silicon substrate in oxygen at e.g. 1000 C.

A channel of negative charge can be formed at the oxide interface by applying positive

voltage to the gate, as shown infig4.3b. The channel then serves as the lower plate that canbe contacted by voltage applied to the highly conducting source and drain regions shown

crosshatched below the oxide. These are the regions that are contacted from the S and D

metal connections at the top by the metallization that continues through the openings made

in the oxide. The region on the left is labeled arbitrarily S (D) and the region on the right

labeled D(S). Each region can serve as the source and the other the drain depending on the

polarity of the voltage applied between these terminals and thus the direction of current

flow through the channel. They have a depth ld that is relatively shallow.

Voltage between the plates of a capacitor controls the equal and opposite charge on the

plates. For example, positive voltage and charge on the upper plate (the gate) will induce

negative charge in the bottom plate. This charge can be in the form of mobile electrons oras fixed ionized acceptors without the holes they created present. The crosshatched

regions, with depth ld, can serve as the source of mobile electrons that can flow in the

channel from the source to the drain when positive voltage is applied to the drain with

respect to the source. Current for this n-channel device with electrons in the channel will flowfrom the drain to the source, since current flows opposite to the flow of electrons.

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The sketches in Fig4.4 explain in more detail the nature of the charge induced in thesemiconductor for both positive and negative voltage applied to the gate. When positive

voltage is applied, negative charge is induced in the channel as in fig4.4a. For small valuesof voltage, this induced charge is in the form of immobile negatively-charged ionized atoms;

the holes originally with the ionized atoms are driven away by an electric field so that region

can provide the negative charge to balance the positive charge on the gate. However, when thevoltage between the gate and the source exceeds the threshold voltage, mobile electrons

are induced in the channel, as shown infig4.4b. The channel consists of a so-calledelectron inversion layer because the p-type semiconductor has been inverted from a

region containing mainly holes to one containing mainly electrons. The inversion layer is

only several atoms thick; however, there is enough mobile charge in the channel to

provide the current that must flow between the drain and source regions when voltage is

applied between the drain and source. As the gate voltage increases further the mobile

electron charge in the channel increases, as shown infig4.4c, and the current thereforealso increases.

Basically the MOST structure allows an input voltage applied at the gate terminal to cause anoutput current flowing between the source and the drain terminals and also through the

external circuitry connected to the device. This is the basic function of all transistors:

provide a change in output current, which can pass through a load and produce an

output voltage change, with a change in input voltage. The change in output current

with a change in input voltage is the key performance parameter of a transistor. It is

called the transconductance. Refer again tofigs4.3b for the location of these regions and

typical dimensions.).

If VGS is less than the threshold value, VT, and is also negative, positively charged mobileholes would be induced in the channel, as shown infig4.3d. The source and drain n-type

regions have a large number of electrons and these regions are now separated by positive

mobile holes. Thus there are essentially two back to back diodes. One between the sourceand the channel and the other between the channel and the drain. For any polarity of voltage

between the source and drain, one of these diodes would be reversed biased, preventing

current flow between the drain and the source. {Current flow would occur if one of thediodes had Zener breakdown but the MOSFET is designed so that this does not occur under

normal operating conditions.} Only when the carriers in the channel are of the same type as

the free carriers in the source and drain diffusion wells is conduction between the source and

drain contacts possible.

Summarizing, the n-type transistor operation is based on the motion of the induced

channel electrons (or holes) that flow from the source to the drain. The electrons are

actually provided by the electron-rich source (S) region. Electrons flow to the drain (D)

terminal and out to the external circuit because of a voltage applied externally to the

MOST. (To visualize these concepts think of the kitchen faucet being the source of water

particles [either holes or electrons] and the drain as the collector of the carriers.) The

motion of the electrons is in the opposite direction to the current for the n-type MOST

but in the same direction as the holes for the p-type MOST. The electron concentration

(and therefore the current flowing in the channel region from the D to the S) can be

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changed by a voltage applied between the third terminal, the gate, and the source

terminal. The voltage between the gate and the source, VGS, has to be more positive than

the threshold voltage to induce electrons in the channel. If it is not, no current between

the S and the D, no matter what the potential difference, VDS, is between the D and S

terminals. This is because without electrons in the region, the conductivity is zero.

Return tofig.4.1 and study the E-MOST device with a threshold voltage, VT, of 1.0 [v].)

Because the threshold voltage, VT,has a positive value, this N-MOST is called an

enhancement mode MOST, or E-MOST.If an n channel MOST has a negative threshold

voltage, it is called a depletion-mode MOSFET, as the third MOST device in fig4.1.For the transfer curve in column three VDS is greater than VGS VT; the transfer curves are

always given for the MOST in its saturation region. Note that there is a current even when VGS

is zero. Current can flow even when VGS is zero because VGS is more positive than VT. Noteagain that for the transfer curve for device 1, the drain current is zero when VGS is zero. The

gate to source voltage, VGS, must exceed VT = 1 [v] for the transistor to conduct.

Let us compare the structures for the four types of transistors as presented in column 2. Noticethat the two n-type transistors are both made with p-type substrates and have N+sourceand drain diffusion wells. {The plus sign means that the region has a high concentration ofelectrons, e.g. about one out of 100 Silicon atoms is replaced by a column 5 donor atom (e.g.

Arsenic, Phosphorus, or Antimony) and provides a free electron.}The difference between the

devices is that the D-MOST device has an inversion region with no voltages applied. {Tounderstand the reason for this requires a background in device physics. However, a simple

explanation is that MOSTs can be made with fixed positive charge appears at the interface

between the oxide and the channel. The positive charge induces conducting electrons in the

channel even without voltages applied.}The device symbols with the broken line for the E-MOST and the solid line for the D-MOST device emphasize that the E-MOST source and drain

are disconnected when VGS is zero. Note again that the D and S terminals areinterchangeable, depending on the direction of current flowing through the transistor. Also

note again that the distance between the diffusion wells is L and that the width of the device

[into the paper] is W. W/L is the parameter that engineers use when designing FET

circuits.

P-channel devices are identical to n-channel MOSTs except that their substrate is made of

N-type material and holes flow between source and drain when VGS becomes more negative

than VT. The mobile carriers that conduct current, ID, are holes rather than electrons. Notethat the source and drain wells are made of heavily doped p-type material, which is symbolized

by the + sign on the P symbol in the source and drain regions. Compare the transfer

characteristics for the two p-channel transistors with the two n-channel transistors. Note that theonly difference is that the curves sweep up to the left for the p-channel devices, as VGSbecomes

more negative, and sweep up to the right for the n-channel transistors. Notethat for P-MOSTs

holes and current flows from source to drain. This causes a voltage drop such that the

drain voltage will be negative with respect to the source. Thus VSD will be positive. In

contrast, current flows from drain to source in the n-channel devices, which results in V DS

being positive. Since VDS is positive, it is used in the plots of the drain characteristic plots

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Exercise 4.2. Find the values of VDS and VGS for the transistors infig4.5and identify theregion of operation for the transistor in each of the circuits. First read the problem at

the top and then study the suggested step-by-step approach at the bottom of the figure.

A word of caution: Most errors in solving these types of problems occur because of errors in

the use or understanding of potential difference and Ohm's Law. As with the diode

problems, put voltage drop signs on the circuit BEFORE proceeding.

Exercise 4.3. Make a sketch to explain how when an electric field is applied, hole motion (due

to the motion of electrons jumping between the broken valence bonds of acceptor atoms)

acts as a positive charge. Review the top complete paragraph of the third page of this lesson.

B) Analysis of Basic MOSFET Circuits

A simple circuit with a MOSFET transistor attached to a resistor load is shown infig4.6a. The

device parameters VTN and K'n are specified and written next to the device. Since W/L is given to

be 1/1, the K value is 250 A/V2. The circuit will be analyzed by finding the Q-point of the

device, i.e. the dependent variables ID, VDS, and VGS. The four steps to solve the circuit are listedunderfig4.6 a so that you can look at the circuit while you read the steps. The additional commentsbelow on the four steps should be read while you have both this text and the figure in front of you.

1) Since the gate and source voltages are given, the difference in potential between the gate and

the source, VGS, is easily found to be 3 [v].

2) It is good practice to assume that the transistor is in the saturation region because the

current equation involves only two dependent variables and not VDS. Therefore in step 2 we

substitute VGS = 3[v] into the saturation equation and calculate ID = 0.5 mA.

3) Add the correct plus/minus sign across the resistor, along with the calculated 5 [v] voltage drop.

4) The last value for the Q point, VDS , is found by subtracting the resistor drop from 10 [v]

since the total voltage around the loop must be 10 [v] and the source is at ground.

5) The final step is to check the assumption that the MOST is in the saturation region. Wemust use the fact that the drain to source voltage for the border between the saturation

region and linear regions, VGS VT, is 3 1 or 2[v]. This value is less than the calculated

value of 5 [v] for VDS. Thus the transistor is in the saturation region as was assumed.

The same circuit is analyzed by graphical analysis using steps 1, 2, and 3 in fig4.6b. First,the characteristic of the N-channel MOST with VTN = 1[v}, K = 250 A/v

2, and VGS = 3 [v] is

plotted infig4.6b1. [The calculated values for the saturation current and boundary region

voltage, VDS are used to make the plot.] Second the circuit characteristic is added to the plot asinfig4.6b2. The circuit characteristic depends only on the total voltage applied and thevalue of the resistor and is not related at all to the device characteristic. The voltage across

the device must equal the total voltage applied minus the voltage across the resistor. Thereforethe resistor i/v characteristic is plotted backwards from the total voltage of 10 [v]. In step 3,

the Q-point is found at the intersection of the device and resistor characteristics.

The circuit infig4.7uses the same transistor as infig4.6abut has a resistor connected from the

MOST source terminal to the minus 5 [v] supply. The resistor connected to the source terminal

makes the analysis more difficult than for the circuit offig4.6a. Three equations must be

written to find the 3 unknowns, the dependent variables ID, VDS, and VGS. Equation one,

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written below, is the MOSFET equation for the saturation region. The two other equations are

those for the two loops, the gate-source loop and the drain-source loop. Note that VG is 0.5[v],

by voltage division of the 5 [v] applied to the gate biasing circuit. Also note that the totalvoltage for the gate loop, from the gate to 5 is 5.5 [v] and that voltage must equal VGS plus

the drop across the resistor. The total voltage dropped across the loop from the 5 [v] drain

supply to the minus 5 volt supply is 10 [v]. It is dropped across the two resistors (50K + 50K =100K) and across the transistor (drain to source voltage drop). The equation for this loop is 3.

1) ID = K/2 [VGS VT]2 2) 5.5 = VGS + I D50K 3) 10 = ID (100K) + VDS

The three equations can be solved for the three parameters that determine the Q point:

VGS, VDS, and ID. Equations 1 and 2 can be combined and the resulted quadratic equation

solved. An alternative method is by guessing the value forVGS and finding ID using equation 2.

Then one has to check if this pair of VGS and ID values satisfies equation one. If they do not, arevised guess forVGS must be made similarly as done for the trial and error procedure

presented in lesson 2. To save time, let us make a wild guess of 3 [v] forVGS. This results in IDbeing 50 A according to equation 2. Letting VGS equal 3 [v] in equation one yields 50 A, so

the guess ofVGS = 3[v] was a very lucky one. (smile) From equation 3, VDS is found to be 5[v].The graphical approach shown infig4.7b gives the same result and also clearly shows that the

MOST is in the saturation region as assumed. Of course, the device curve had to be sketchedby guessing that VGS was 3 [v]. [It is easier to make a lucky guess if you design the problem, as

the author did. Note that the procedure that the author followed would be the one that would be

used if the desired Q point values were known and the biasing circuit to obtain the Q point wasto be designed.]

The circuit infig4.7could be modified so that voltage from an ac analog signal generator could

be either amplified or applied to loads for the purpose of making the resistance of the generatorappear to be much less. Such an amplifier is shown infig4.7d. A capacitor connects the output

of the generator to the gate terminal of MOSFET circuit. The capacitor serves the purpose ofcoupling the ac voltage to the gate while blocking any DC current to the signal generator

circuit due to DC voltage on the gate. The generator circuit would be in parallel with the 9

M resistor and would cause a change in the DC gate voltage if the capacitor was not used.

The capacitor couples the ac voltage to the gate input by behaving as an effective short circuit

for the ac current as long as it is large enough to have low impedance for the frequency of theac input signal. Such analog circuits are studied EE 372. [This type of circuit could amplify a 1

mV signal voltage for example to a level of volts. As mentioned the capacitor is an open circuit

for DC current and thus allows the ac signal to reach the gate but isolates the DC bias circuitry

from the signal source. Because of the particular choice of 5 K resistors for both the drain andsource circuits, the voltage gain of the circuit (time varying output voltage divided by the time

varying input voltage provided by the signal generator) is actually less than one. However, thisamplifier has other useful properties as taught in electronics 2.]

Example Problems with Solutions Given

Study the following problems to develop your analysis skills for MOSFET circuits.

PROBLEM ONE: Select the value for VDD for the circuit infig4.8 that sets the Q-point 4 [v]

greater than the value of VDS at the intersection of the linear and saturation regions. In other

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words, the value of VDS should be four volts greater than the value of VDS that defines the

boundary of the linear and saturation regions.

Solution for Problem One:

a) By voltage division of the 10 [v] with the 40K and 60K, VG = 4 [v].

b) VGS is found to be 4 [v] because the source is grounded.c) The MOST saturation equation is used to find ID = 4 mA. Confirm that this is so. (Note

that the wording of the problem tells you that the FET should be in the saturation region.)

{The value of VDS that separates the saturation and linear regions is found by subtracting thethreshold voltage from VGS. (Confirm that it is 2 [v].)}

d) The actual value for VDS of 6 [v] is obtained by adding four volts to the value of VDS =

2[v], found in step d, so that the Q-point is 4 [v] into the saturation region as required.

e) Adding the drop across the resistor for ID = 4 [mA], 4 [v], to VDS = 6[v] gives the value of VDDthat should be selected, i.e.10 [v]. This value of VDD enables the Q-point of the FET to be at VDS

= 6{v] and ID = 4 [mA] as required in this design problem.

PROBLEM TWO:Find the Q-point for the circuit infig4.9. Note that the circuit and deviceare the same as for problem 1 except that the 1K resistor has been increased to 10 K.

Solution for Problem Two: If we assume that the transistor is saturated, the current wouldbe 4 [mA]. This current would cause a drop across the 10 K of 40 [v]. This is impossible

since only 10 [v] is applied to the drain/source loop. Therefore the assumption that the

MOST is in the saturation region is incorrect. The equation for the linear region must be usedto find ID.

Since there are 2 unknowns in the equation for the linear region, a second equation must be

used. This equation is Ohms Law for the resistor. It relates the current in the resistor to theunknown voltage, VDS, and VDD = 10 [v], as written below equation 1 in the figure. The two

equations can be equated to obtain equation 3, since the current in the resistor and MOST are

the same. {VGS = 4 [v] obtained as in problem 1 was substituted into equation 1.}

1) I D = 2 10-3 [(VGS VT)VDS (VDS)2 / 2 ] 2) IR = (10 VDS ) / 10K = ID

Equation 1 and 2 can be combined and then reduced to the quadratic equation:

3) (VDS)2 4.1VDS +1 = 0

Solving the equation using the quadratic formula leads to finding VDS is either 0.2605 or 3.84 [v].The larger value is rejected because it is greater than 2 [v] and therefore the MOST would be in the

saturation region, which is impossible. It was already determined that the MOST must be in thelinear region. The drain current can be found easily from equation 2 to be 0.974 [mA], using thevalue of 0.26 for VDS. Please check these results by inserting the values for VDS and VGS into the

linear region equation for current.

PROBLEM THREE: Find the Q-point for the circuit in Fig4.10. This problem is similar tothe previous one but there is less required math.

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Step by Step Solution for Problem Three: 1) First we find VGS is 4 [v] by voltage division 2)

Assuming that the MOST is in the saturation region, we can easily calculate the current to be 4

[mA]. However, the drop across the 4/3K resistor would be greater than 5 [v], and that is

impossible since only 5 [v] is applied to the drain loop. 3) Therefore the linear equation is

written for the MOST. 4) The device current is set equal to the current in the resistor, as done

in the previous problem, and as shown infig4.10 for convenience. Practice doing this. Theresultant equation for VDS is:

1) (VDS)2 19/4VDS + 15/4 = 0

Let us have some fun by solving this problem by trial and error, starting with a guess of 1 [v].

What a guess! It solves the equation and 1 [v] is a value less than 2 [v] so that the device is

in the linear region, as it must be since linear device equation was used. The current iseasily found to be 3 [mA] by applying Ohms law to the resistor.

PROBLEM FOUR: Find the value of the resistor infig4.11 so that VDS = 1 [v] and ID =

3 [mA]. This problem should look familiar!

Solution for Problem Four: We note that the required value of VDS compared with 2 [v] tellsus that the MOST is in the linear region. Since we are given all the Q-point values, a device

equation is not needed. The voltage across the resistor is 5 1 = 4 [v] and the current is 3[mA]. Therefore by Ohms Law the resistor value is 4/3 K.

PROBLEM FIVE: Given the circuit infig4.12. Find the Q-point for the transistor. Notethat the MOST is a P-type transistor (by the small circle on the gate of the transistor).

Also note that the magnitude of the values for the voltages and currents in the circuit and

the power supply voltages and threshold voltage are the same as for problem 3, the

circuit infig4.10, but the signs are different.

Solution to Problem Five. As a first step to finding the Q-point for the circuit in fig4.12, wenote that the current flows from ground to the minus five volt supply. Therefore since the

MOST is p-type, the source terminal is again at ground potential. The direction of current

flow from ground to the minus five volt supply and the voltage drops VSD and VGS are shown tothe right of the figure. It is good practice to show the current flow direction and add the drops to

the circuit infig4.12. [You could also sketch the circuit on a separate sheet of paper. As a first

step to solving the problem, add current flow and voltage drops with polarities.] As a second

step, the value of the voltage VGS can be easily found by voltage division on the gate circuit (V G

= VGS = 4 [v]). Then the current can be calculated, assuming that the device is saturated. This

current value (4 mA) times the 4/3K resistor will produce a voltage drop greater than the appliedvoltage. Thus we know that the equation for the linear region should be used. See equation 1under the figure. As a fourth step, the Ohms Law equation for the resistor is written as equation

2, also in the figure. Equations 1 and 2 can be solved simultaneously by the quadratic equation or

by trial and error to find VSD = 1[v] and ID = 3 [mA].The next section presents a general approach to solving the find the Q-point problems.

Section C does not have to be studied for the Electronics One course if you are

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comfortable doing the previous examples. It is written sothat you have an organized

approach at hand if you need to solve such problems in other courses or work.

C) General Guideline for Analysis to Find the Dependent Variables ID, VDS, and VGS in a

MOSFET Circuit

a) Find the gate voltage, VG, by voltage division. Since the MOST has no DC gate current,

this is a very simple task.

b) Write an equation for the gate-source loop that includes the key parameter, VGS,

which controls the drain current. [Determine first which terminal is the source by observing

the direction of the drain current and using the fact that the carriers, electrons for N-MOST

and holes for P-MOST, leave from the source and travel to the drain.] If the source isconnected to ground, VGS is given by equation 4.If the source is connected to a supply voltage

VSS through a resistor RS, equation 5 must be used.

4) VGS = VG - VS = VG5) VGS = VG IDRS VSS

c) Write one of the two MOST device equations.Unless it is obvious that the device is

in the linear region, choose the saturation region equation since it has only two

unknown parameters, ID and VGS.

d) Write an equation for the drain source loop, equating the total voltage applied to the

loop equal to VDS plus the IDR drops across the resistors in the source leg and in the

drain leg.

e) Use the three equations obtained in steps b, c, and d to solve for IDand V

GSand then V

DS.

This step will involve the use of either the quadratic equation or the trial and error method.

f) Compare the values for VDS with VGS - VT to see if the assumption of using the

saturation equation for the FET was correct. If it is not, use the linear equation for the

device and redo the steps starting with c to find the actual values for ID, VGS, and VDS.

D) REVIEW OF THE LOAD LINE CONCEPT.

It is important to visualize the analysis of these problems from a load line point of view.

Review again the graphical solutions for the circuits in figs4.6 and 4.7. Note that whenthere is a resistor connected between the source and ground, as infig4.7, the load line isdetermined by the sum of RS and the resistor connected to the drain, RD. [This resistor has

often the symbol RL because its function is to act as a "load" across which the small signal,

analog output voltage due to the current develops for use of a load device, for example a sixteenohm audio speaker.] The load line for the MOST depends only on the total voltage applied to

the "drain source loop" and the total resistance in the loop. Equation 6 can be used to plot the

load line by asking if questions as were done with the diode circuits, for example: a) If I D were

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zero, what would VDS be? b) If VDS werezero, what would IDbe? c) If VDS were two, what would

ID be? These values of VDS and ID will lie on a straight line, the load line.

6) VDS = (|VDD| + |VSS|) - ID(RD + RS)E) VOLTAGE TRANSFER CHARACTERISTICS OF LOGIC CIRCUITS and NOISEMARGINS.

The transfer characteristic of a logic gate is the plot of its output voltage versus its input

voltage. An example basic logic gate is shown infig4.13a. The N-channel MOST acts as a

switch while the resistor acts as a load, dropping voltage so that the output is not always

5[v]. When the input voltage is 5 [v] (as the boxed value at the gate) the output voltage is 0.25

[v]. This is because the switch conducts current when the input voltage is greater than VT. Thecurrent causes a 4.75 [v] drop across the load resistor. The value of the voltage drop is set by the

resistor and current values so that the output is the desired 0 logic value of 0.25 [v]. When the

input voltage is less than the threshold voltage, e.g.0.25 [v], the switch is open. The output rises

to the logic 1 value of 5 [v] because no current flows and there is no voltage drop across theload resistor.

The transfer characteristic, or transfer curve, for the gate is shown infig4.13b.The transfer

curve gives a value for the gate output, v0, for every possible input voltage, vI. For this gate, the

normal inputs are 5 [v] for a 1 and 0.25 [v] for a 0. Observe that the corresponding outputsas plotted on the transfer curve are 0.25 and 5 [v]. These pairs of values locate the normal

operating points of the gate on the transfer curve.

The input voltage to the logic gate can not change instantaneously from 5 to 0.25 [v] during thetransition from a 1 to a 0. During this input transition time, the output voltage switches

from 0.25 to 5 [v]. The time for the input and output to change is referred to as the switchingtime. Similarly, as the input changes from 0.25 to 5 [v], the output decreases from 5 to 0.25 [v].Fig4.14a shows typical input and output waveform changes when clock pulses are applied. The

rise and fall times of the input and output usually are different. The signals are clean because

the circuit is assumed to be in a noiseless environment.Fig4.14b shows that in a normalenvironment there is noise pickup on the waveforms caused by fast rise and fall times of the

input and output voltage. The waveforms sketched infig4.14b illustrate that actual voltage

signals are not clean but modified by the noise pickup. Even during the time when the input is

suppose to be at a steady value, e.g. 5 [v], it may fluctuate due to pickup from nearby gates.

What causes the pickup or noise that results in waveforms not being clean? The major cause

of noise is that the wires or conductors in the circuit act as tiny antennae, receivingelectromagnetic radiation from nearby wires due to rapid changes in the currents and

voltages in the surrounding conducting connections and gates, including power supply

lines. Seefig4.15 and study the comments presented under the sketch for your convenience.The comments point out that the wires connecting the devices and circuits in a logic system

can effectively be modeled as capacitors, resistors and inductors. The inductors can

represent coupling between two different wires, or mutual inductance, or the voltage drop

in a single wire due to the rate of change of current through the wire, self-inductance. The

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very rapid rise and fall times of the voltage and current signals (big dv/dt and di/dt) in

modern high-speed computers enhance these undesired effects.

One purpose of the transfer curve is to reveal how much protection a logic circuit has

against having its output being switched by noise from logic "1" to "0", or from "0" to

"1" without the input changing. The noise margin in volts indicates the protection againstunwanted noise pickup. Notice that when the input waveform infig4.14b dropped belowthe VIH level due to a large noise pickup during the time that the input was suppose to be

high, the output changed from a 0 to a 1. Thus a computer error was generated.

When the noise diminished and the input went above the VIH level, the output returned to

its correct value of 0. Similarly near the end of the waveform when the input in the low

state rose above the VIL for a short time, the output dropped to a low level creating a second

error. Thus VIL is the maximum low level that the input can increase to without causing theoutput to switch erroneously from a 1 signal to a 0 signal. Similarly VIH is the minimum

high level that the input can fall to without causing the output to switch erroneously from a 0

signal to a 1 signal. These levels infig4.14b can be found on transfer curves such as the one

infig4.18. However first we will discuss some basic concepts usingfigs4.16and 4.17.

Fig4.16shows the voltage transfer characteristic for an inverter logic circuit. There are twonormal operating points. An operating point is a pair of input and output values that are

associated with the normal 1 and 0 levels. The curve is ideal because the output does notchange with input except for the transition region where the output changes rapidly from a

high level to a low level with increasing input voltage. Ideally the digital gain, defined as the

change in output divided by change in input, is infinite as in the case of the vertical drop

versus the finite slope of a realistic transition region. Looking along the vertical scale, the

normal high-level output voltage that must serve as a high level input can be seen to be VOH =5[v]; and the normal low level output voltage that must serve as an input is VOL = 1 [v]. Note that

when the input voltage is at 5 [v] (the high level signal, VOH) the output is at the low signal level,

VOL= 1. Also, when the input is at a normal now level, VOL, the output is VOH. You shouldobserve this by following the arrow/path beginning at the input VOH (the "a" arrow). Then follow

the "b" arrow/path beginning at the input VOL to see the output is the high level, VOH.

The reason that the normal outputs VOH and VOL must be used as inputs is thatthe

inverters must drive identical inverters, as shown by a typical logic gate array in fig4.17..The circled normal output voltages correspond to signals levels observed during one clock

period. The squared voltages correspond to a different clock period. The load inverters in turndrive identical inverter gates, or perhaps NAND, OR etc, gates, which also must operate with the

same voltage levels for the "0" and "1" signals. For the array of gates to function without

error, there must be this input/output compatibility. The high-level output signal level,

VOH, must serve as the high-level input signal, VOH;the low-level output signal level VOLmust serve as the low-level input level signal, VOL.

A more realistic transfer curve is shown infig4.18a. Note that between the two signal inputs

where the slope of the curve is minus one, the output changes more rapidly than the input. That is

the slope of the curve is greater than one. For a particular input change, e.g. 0.1volt, the output

will change by more than 0.1volt. This region is said to have digital gain, i.e. the output

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changes more than the input. Increasing the digital gain is necessary to reduce the time for

the input and output to switch between high and low voltage levels. The more vertical the

transition region of the logic gate transfer curve, the higher the switching speed of the gate.

The symbols for the particular input signal values for the points on the curve where the

slope is minus one are VIH and VIL. The noise margin of the gate depends on having thelowest possible value for VIH and the highest possible value for VIL. Seefig4.18b which shows

an error in the output of inverter 2 created by the drop below the VIH level in the output voltage in

inverter 1 that drives inverter 2. Once the input falls below the value at which the slope of thetransfer curve is minus one it enters a region of digital gain where the output changes are large

and serve as large input change to gate 2 and produce wrong output for gate two, as shown in the

waveforms infig4.18b. If the reduction of the input signal were not enough to bring the input to

VIH, errors would not occur in the following gates. Thus the voltage difference between VOH

and VIH represents a safety factor, or high level input noise margin, NMH. Similarly, the

voltage difference between VILand the input VOL, NML, represents protection against the

input signal increasing from the normal signal input level VOL to beyond the value VIL where

there is gain. This voltage difference represents the low-level input noise margin.

Ideally, the transition region, where there is digital gain, is located in the center of the

transfer characteristics and has zero width so that the noise margins have the maximum

possible values. The noise margins also would be the same. This is preferred since the

quality of the noise protection is only as good as the smallest noise margin.

As stated, immunity against noise is only as good as the smallest noise margin. A large signal

swing, VOH VOL, tends to produce larger rate of change of voltage with time and therefore more

electromagnetic pickup by the gates in a logic array and therefore more errors. Therefore a noise

immunity figure of merit equal to the noise margin divided by the signal swing has been used

as an industrial standard to compare different logic gate circuit families, e.g. ECL, TTL,CMOS and DMOS.

F) DEFINITIONS OF PROPAGATION AND PAIR DELAYS, FAN-IN AND FAN-OUT,

AND THE POWER-DELAY PRODUCT; LOGIC CIRCUIT REQUIREMENTS.

Example switching waveforms for an inverter gate are shown infig4.19. The logic decision

speed of gates is compared using values for the propagation and pair delays. The propagation

delay on the high to low output transition, PHL, is shown in fig4.19 as the delay between the50% points of the rising input waveform versus the falling output waveform. Similarly the

propagation delay on the low to high output transition, PLH, is shown as the delay between the

50% points of the falling input versus the rising output. The two times will not necessarily be thesame. The average propagation delay, P, which is the sum of the two propagation delaytimes divided by two, is often used when comparing logic circuits.

The propagation times will depend on the number of gates driven by the output, or the fan-

out. [A major reason for this is that the capacitor loading changes with the number of MOSFETgates.] One type of logic gate might appear to be very fast for low fan-out but will slow up much

more than another type of gate when required to drive many other identical gates. The normal

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speed performance parameter is pair delay, the time for the input to reach the same 50%

value on the rising input waveform after passing through two identical gates.

Logic gates can be operated with shorter propagation delays by increasing the supply

voltages. The cost is that the standby power and switching power dissipation will increase.

Therefore to compare fairly circuit families and designs, a figure of merit (FOM) equalto the product of the average propagation delay time (e.g. in nanosec) and the average

power supplied to a gate (e.g. microwatt) is used. The unit for the FOM of logic gates

manufactured in 2005 is femto-joules. You will see that it is possible to decrease

switching speed if the power consumed by the gate is increased. Therefore for a given

logic gate technology the FOM tends to be constant. Ask your instructor to provide you

with the latest energy versus time (in years) for the various logic technologies. Sources

for information are the January issues of the IEEE Spectrum magazine.

The number of identical gates that a logic gate can drive effectively is defined as the fan-out

capability. Fan-out capability is sometimes just called fan-out. [However, this could be

confused with the total number of gates attached to a gate, which might be less than what it iscapable of.] In general, the fan-out capability will be different for high and low outputs.

Similarly, the fan-in capability is the number of inputs that can drive a single gate at a

specified clock rate, without errors being produced. Fan-out and fan-in depend on clock rate.

G) BRIEF SUMMARY OF LESSON FOUR

The major learning objective of section A is to be able to sketch the transfer and drain

curves of a MOSFET if the K and VT values are specified. Section A also focuses on

explaining why the MOSFET structure results in these characteristics. However, it was

pointed out that the design of circuits can be done with knowledge of the characteristics

infig4.1 only. On the other hand, knowing the device physics and material science behindthe characteristics is valuable knowledge for following developments in the many high

technology areas based on semiconductor technology. Section A provides this basic

knowledge. Additional material science information is given in Appendix 4.2.

The analysis of the basic circuits infigs4.6through 4.13 was used to exercise and developyour knowledge of the FET device characteristics and equations. The examples also exercise

your basic knowledge of circuit analysis principles as voltage division, potential difference,

multi-loop equation analysis and load line. However, the only new concept in these exercises

was the brief introduction to the MOSFET circuit as an amplifier of analog signals. The

subject of MOSFET and Op-amp analog circuits is covered extensively in EE372 and EE 373.

Another key learning objective of lesson 4 is to know the important applications of the logic

gate transfer curve. The concept of noise causing unwanted changes in output voltages

summarized infig4.18. The physical cause of noise and how the transfer curve providessome protection against noise and the propagation of errors (as indicated by the noise

margins) are summarized infigs4.15-4.17.Other figures are presented only to help youunderstand the information in those four figures. The bold statements in Section F andfig4.19summarize the important logic gate performance parameters of average propagation delay,

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pair delay, power-delay product (which has the units of energy) and their dependence on

fan-in and fan-out.

The key information in this lesson will be used in almost all the following lessons so you will bereviewing by using throughout the rest of the course.

Appendix 4.1 Basic Concepts for the Junction Field Effect Transistor (JFET)

The structure and physical operation of the junction field effect transistor is entirely

different than for a MOST and will not be discussed in detail. However, the I/V transfer

and drain characteristics are nearly the same. The JFET parameters that are given by

manufacturers of the transistor are IDSS, the saturation current for VGS is zero, and the

pinchoff voltage VP, which corresponds to the threshold voltage for the MOSFET. For

an n-channel JFET the pinchoff voltage is the value of VGS that reduces the current to

zero (or pinches off the channel). For the saturation region, equation 1 is used. The

equation is equivalent to the MOSFET saturation equation if K is set equal to 2IDSS / [VP]2. The linear equation for the MOSFET can be used for the JFET also. The transfer

curve for the JFET is identical to the DMOST except that it cannot be used in theregion where VGS is positive. [This is because current then flows from the gate into the

channel region and the gate is no longer isolated from the source and drain, as it should

be for a FET.] The transfer curve is shown in the margin. The equation for the linear

characteristic is equation 2.

1) ID = IDSS [1 VGS /VP ]2 {from ID = K /2 [VGS VP ]

2 where K = 2IDSS / [VP]2 and VDS VDS*

2) ID = K [(VGS - VT ) VDS /2] VDS ID = (2IDSS / [VP]2) [VGS - VP]VDS, for small values of VDS. AID = (2IDSS / [VP]

2) [(VGS - VT ) - VDS /2] VDS for values of VDS that are large enough to make the

subtractive term in the brackets significant.

Appendix 4-2 Review of Conduction Properties of Silicon and Other

Semiconductors.

This appendix presents in more detail the mobile charge generation and conduction

processes introduced briefly in the first paragraph in section A.

There are three types of silicon material: intrinsic, n-type and p-type. Intrinsic, or pure

silicon, with no deliberately added impurities is relatively non-conductive It has a large resistivity,

, of about 1000 ohm-cm. at room temperature (2930K). Equation one describes thedependence of the resistance (R) of a sample of semiconductor material of width W,

thickness t, and length L, with voltage (V) applied across L. The material parameter that

controls R is the resistivity, . The resistance is also dependent on W, L and t that make upthe geometry factor. Fig4.1 described the geometry factors (L, W, and t) and showed thecurrent and electric field directions in response to a voltage, V, across the material.

1) R = [ohm-cm]L[cm] / W [cm] t [cm]Bond and band energy models are useful for visualizing the complex phenomena that

occur at the atomic level in conductors, insulators and semiconductors. These simple

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models enable engineers to effectively design and even invent electronic devices, without

having to think in detail about the complex phenomena at the atomic level. FigA-1 shows thesimple bond model (the chemists view) which describes some of the electronic properties

of intrinsic material. Surrounding each host silicon atom are 4 valence electrons. These

electrons are shared between neighboring atoms and are the co-valence bonding which holds

the array of atoms, called a lattice, together. Notice that each atom, such as the central one inthe sketch shares eight electrons with the surrounding atoms.

The atoms can be thought of a connected by springs that represent the various forces that

the atoms exert on each other. Thus thermal energy of the atom array can be expected to

trigger coordinated motion, or vibration wavelike motion. The particles that carry the

energy of these vibrations are called phonons, just as photons are the particles carrying

the energy of electromagnetic radiation, or light. [For a very simple idea of the wavemotion of the phonons visualize the coordinated standing up and sitting of fans at sports

events, called the WAVE.] Because of the energy of the moving atoms, about 1010 el/cm3 of

the electrons in the co-valence bonding will be shook free from their mother atoms at

about 68 degrees Fahrenheit. They generate not only free electrons, ni, but also an equalnumber of holes, pi, in the covalent bonding. Only a small percentage of the bonds are

broken at room temperature (ni = pi =1010 el/cm3). This number is much less than the

number of host atoms, 51022 atoms/cm3.

A hole acts as a positive charge and moves in the opposite direction of an electron when

under the influence of an electric field.FigA-1a shows a broken bond first created at the

lower left (step a) by thermal energy. The broken bond, or hole, can move upwards by e.g. an

electron at the upper left randomly moving down from its valence bond position to fill the

broken bond at the bottom (step b). Thus the broken bond, or hole, has moved up as indicatedby c. Again this creation of the electron and hole pair occurs at random due to thermal energy

breaking the valence bonding.

FigA-1b shows the energy band model (the physicist view). The potential energy for anelectron in electron-volt units is plotted in the vertical direction. When an electron

receives energy, e.g. from heat (the atomic vibrations) or from sunlight, it moves up

from the valence band, representing its location in the bonding structure, to the

conduction band representing its ability to move through the material free of the

bonding forces. [Note that an eV unit of energy is 1.6 times 10 19joules. These small energy

units are convenient for measuring the potential and kinetic energies of electrons with theirvery small mass and small energies for separating them from their mother atoms.] The

model shows a band of electron energy levels that hold electrons involved in the co-valence

bonding. This lower group of energies is named the valence band, as shown in the figure.

Above the valence band there is a range of energy in which there are no energy levels,

and therefore no electrons can be in this energy range, called the forbidden gap.

The conduction band contains the generated electrons that are free to move in random

directions. The free electrons in the bond model occupy the lowest levels in the conduction

band, as shown in thefigA-1b. [The horizontal axis has no significance infigA-1b; however, inother energy-band figures it is used to show how the conduction band energy and potential

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energy barriers for electron flow vary with distance along a direction through the device

structure.] The band model shows clearly the amount of thermal energy required to break

the bond, generating the free electron and hole. This energy is 1.11 eV for Silicon and 1.43

eV for Gallium Arsenide. The difference in energy required to break bonds is significant

and the density of ni in GaAs is only 2106 pairs/cm3 because it has a wider bandgap than

Silicon.

If an electric field is applied, the free electrons although moving in all directions will have

a net component that moves opposite the direction of the electric field (i.e. provide

electrical current). When no voltage is applied to the silicon material, the holes and free

electrons are moving around in all directions so that there is no net charge motion and

therefore no current flow. However, when voltage is applied, the electrons jumping around

in all directions tend to move slightly more in the direction opposite the direction of the

electric field due to the voltage, and thus the holes move in the direction of the electric field

and thus act as positive charge. Again, hole motion is actually due to electrons that jump into

the broken bond from neighboring bonds creating a hole in their former location as shown in

figA-1a. It appears that the hole moves in the opposite direction to the jumping electrons andtherefore a hole acts as a positive charge when an electric field is applied. The field enhances

the motion of electrons in a direction opposite the field direction. Thus it enhances the motion ofelectrons jumping in the band structure to fill vacancies and thus enhances current due to holes.

When no voltage is applied to the silicon material, the holes and free electrons are moving

around in all directions so that there is no net charge motion and therefore no current flow.

N-type, or electron-rich, material is made by adding column 5 impurity atoms (such as

phosphorus, antimony, and arsenic) to intrinsic silicon to "dope" the material.FigA-2a

shows that the extra electron is not involved in the bonding process and is thus relativelyweakly attached to the impurity atom. Almost all the impurity atoms lose their fifth electron at

room temperature and thus are ionized. Thus doping by the impurity atoms increases the

free electron concentration due to the concentration level of the doping impurities, called

donor atoms, without generating any holes. The number of electrons generated can be

between 1015 to 1020 el/cm3 compared with the number of host silicon atoms, about 51022

atoms/cm3. The band model infigA-2b shows the electrons thermally excited into theconduction band by the addition of the donor atoms, along with the relatively small number of

thermally generated electrons across the relatively large energy of the gap. To show the small

amount of ionization energy required, energy levels representing the donor atoms are shown as

shallow energy states located e.g. 0.1 eV below the conduction band edge.

The addition of a large number of electrons greatly reduces the hole concentration

because the extra free electrons from the donor atoms fill in most of the broken bonds.

From the band model point of view the negatively charged electrons in the conduction

band, attracted to the positively charged holes, lose the extra energy that they have in the

conduction band by recombining with the holes in the valence band. [The recombinationoccurs directly across the gap in direct gap materials, e.g. the 3-5 compound GaAs. The

recombination time is short, about a nanosecond, and the loss of electron energy is converted

into the emission of a light particle, or photon. Silicon is an indirect gap semiconductor and

the holes and electrons recombine in a much slower process that involves a small number of

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impurities, e.g. 1013 /cm3, that are located in the forbidden gap and serve as recombination

centers. The recombination centers are energy levels in the forbidden gap that can capture e.g.

a hole so it cant move and but can still can attract and recombine with a free electron.] Theresult is that the number of holes in n-type material, pn, is reduced to the number of

holes/electrons pairs squared in intrinsic material, ni2, divided by the electron concentration in

the n-type material, nn. A doping concentration of 1015

/cm3

reduces the hole concentrationfrom 1010 to only 105 holes/cm3, as shown infigA-2b. The holes become what are called the

minority carriers. Nevertheless, the small minority carrier concentration plays an important

role in diodes, e.g. being responsible for the reverse saturation current in a p-n junction diode.

Besides increasing the number of free mobile electrons, donor doping introduces immobileions that are positively charged after they donate an electron to the conduction band.

These positive charges cause electric fields (and forces on charges). Electric fields due toimpurity atoms play an important role in the complex physical behavior at the junction of N-

type and p-type material and thus influence the I/V characteristics of diodes.

Intrinsic silicon can be made p-type by adding column three dopant atoms, creatingbroken covalent bonds, without adding electrons seefigsA-3a andA-3b.Note that theoriginal acceptor is neutral but will probably have its broken bond filled by electrons, from themore numerous silicon host atoms that surround it. Thus the acceptor atom becomes a

negatively charged fixed ion. The broken bond (hole) will randomly move around the crystal

unless an electric field is applied and then the broken bonds will behave as positive charge andadd to the current due to the applied E-field. Current that flows in n-type or p-type material

because of free charges, electrons or holes, which move under the influence of electric

fields is called drift current.The electric field could be due to applied voltage to the

material or due to the electric field generated by positive and negative impurity atoms at

the junction between P and N-type material. There is another cause for free charge motion

in semiconductors and that is diffusion due to carrier concentration gradients, e.g. due to added

impurity distributions that are not constant in space. At the boundary between P and N typematerial the sum of the diffusion current due to electrons and holes moving across the

boundary is cancelled out by the drift current due to the electric field due to the ionized donors

and acceptors.

The conductivity of n-type material depends on the number of free electrons, n, and a very

important semiconductor property, the electron mobility, n. Electron mobility indicates the

velocity response of an electron due to an electric field. The value of mobility is about1500 [cm2/volt sec] for silicon material doped at 1015 at/cm3. [The mobility decreases as the

doping level is increased. to obtain more free electrons to e.g. it is about 500 for added

impurities at the 10

19

at/cm

3

level. The motion of electrons due to an electric field, the driftvelocity, increases as the mobility times the electric field. However, at electric fields

corresponding to 10 [v] applied across a 1 micron distance, the drift velocity in siliconsaturates at about 105 cm/sec. and may decrease further with increasing electric field, which

corresponds to the interesting property of negative resistance, i.e. decreasing current with

increasing voltage.]

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Mobility is the most important property of semiconductor material and is the major

limitation on the speed of computers. Thus new materials are often proposed to replace

silicon for high-speed computers. [These materials are usually in the 3-5 material systemssuch as the tri-constituent compounds InGaAs and InGaP. Although some of these materials

have electron mobilities that are of the order of 100 times those for silicon, the mobility for

the high fields that are needed for short channel MOSFETs is much less, even being less thanfor Silicon. There are significant research efforts to synthesize high mobility semiconductors.

The efforts include looking at non-crystalline materials as well as using dimensions as small

as several atoms in order to change the band-structure of the semiconductor.]

The time for holes to recombine with excess electrons (added to p-type material, e.g.

by optical excitation or by injection of electrons due to forward bias in a p-n junction)

is defined as the minority carrier lifetime. The 3-5 compounds differ from silicon in thatthis time is of the order of a nanosecond in the 3-5 compounds versus a microsecond or

more in silicon. The minority carrier lifetime in semiconductors, or recombination

time, is the other important property of semiconductors. Mobility and lifetime are the

two properties that control the performance of electronic devices.

Theconductivity of p-type material is proportional to the hole concentration, p, and the

hole mobility, p. The hole mobility is about 40% of the electron mobility in silicon. Equations forthe conductivity and resistance of semiconductor material are

summarized below. Note that resistivity, , is the reciprocal of conductivity and that Lis the length, W, the width and t, the thickness of a rectangular region of material in

cm.

1) N [-cm] = q n n 2) P [cm] = q p p 3) R = L/Wt 4) = 1/To fabricate electronic devices and circuits materials with a wide-range of resistivities aredesirable. Mother Nature has provided electronic engineers with an amazing range from

106 to 1018 ohm-cm, as shown in Table 4.1.Table 4.2 showed calculated values, using theabove equations, for the conductivity and resistivity for the three types of semiconductors.

Reasonable values for the acceptor and donor impurity concentrations and corresponding

values for mobility were assumed. Note that for intrinsic material the conductivity due toelectrons and holes must be added together to find the total conductivity.

There is another cause for current due to free mobile charges besides their drift velocity dueto an electric field. Current can be due to diffusion, which results whenever there is carrier

concentration gradient. Carrier concentration gradients occur when there is a spatial change

in impurity concentration levels, as in a p-n junction. Diffusion current is important in theoperation of mainly semiconductor devices, e.g. forward biased diodes, photo-diodes, and

solar cells. Diffusion current can occur even without applied voltage.

Exercise A4.1.Calculate the resistance of a bar of intrinsic silicon ( = 1000 ohm cm) thatis ten m by ten m and 0.1 m thick. [Note that the distance between atoms is about 3 A andthat 10,000 A is equal to one micron. Recall also that 10,000 m is equal to one cm.]

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Exercise A4.2. Confirm the calculated value of 4.16 [ohm-cm} for the resistivity for n-type

silicon with ND = 1015 [at/cm3] in Table 4.2.

Appendix 4-3 Review of the Development of Computer Hardware.

The three-terminal devices that were used in the first manufactured computers (circa

1950) were vacuum tubes. The tubes were structures enclosed in glass cylinders about one

inch in diameter and two inches long that had the air within them largely pumped out, to form a

vacuum. The structures provided the essential requirements of a three-terminal electronic device

that could be used as a digital gate. One requirement of the device was to have electrons flowfrom a source terminal (called the cathode in the case of the vacuum tube) to an output terminal

(the anode) in response to voltage applied across these terminals. A second requirement was to

have a third terminal between the two terminals that could control (or increase and decrease) thecurrent flow between the first two terminals.

For a digital inverter circuit, a more negative or 0 signal input to a third terminal, the

control terminal, must be able to either cut off the current flow completely or reduce it

enough so that the voltage on the output terminal can rise to the level of a 1signal

voltage. In addition, a 1 signal voltage applied to the control, or input, terminal should allowenough current to flow to cause the voltage drop across a resistor load to be large enough that

the voltage at the output node is below a minimum value. Since the output node voltage serves

as an input to identical load inverters to be driven by inverter, the minimum value must be small

enough to shut off the current flow of these load inverters. [The vacuum was necessary so that atiny coil of metal wire, a filament, could be heated by passing current through it without

oxidizing. The hot filament caused electrons to boil out of a nearby metallic cathode. These

electrons were attracted to a metallic anode (about an inch or so away) by a voltage (typically50 to 100 [v]) applied between the anode and the cathode.

The anode/cathode structure essentially formed a diode. The vacuum diode was converted into athree-terminal triode by putting a metallic plate, with lots of holes for electrons to pass through,

in the path between the cathode and the anode. This grid-like structure was connected to the

control terminal. When the voltage between the grid and the cathode was small the structure

could repel the electrons trying to flow to the anode from the cathode. The structure, named agrid, therefore served as a valve to produce the desired effect of increasing and decreasing the

flow of current between the cathode and the anode.]

Several computer logic inverter components were held on printed circuit boards, which were

about ten inches by 5 inches. The boards had a socket that plugged into a rack of

equipment that was about ten feet high and two feet wide! On one side of the printedcircuit board were components such as the vacuum tubes held in sockets and discrete

resistors about 1/8th inch diameter and inch long. On the other side were electroplated

conductors that were connected through holes to the components. Electro-mechanical relaysabout the size of the vacuum tubes (making loud clicking noises) were added to the

components to perform logic switching operations that did not require digital gain. About

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ten racks of this hot, noisy equipment and a few magnetic memory drums and tape

machines, about the size and weight of the largest athletes, made up the computer,

which typically occupied a room about the size of NJITs theatre.

The first computers could keep track of about 10,000 airline and railroad reservations,

if the computer maintenance people were able to keep up with the many failures thatoften occurred in this non-microelectronic equipment. [If you have a chance, look at the

relatively few journals of the IRE/IEEE in the early 1950s to see some photographs of the

early large-scale computers. Experienced field service engineers often could tell fromchanges in the clicking sounds of the relays when the computer was making errors and

rushed in to make repairs which sometimes could take hours. Unlike the computers of today,

these computers were real machines that you could see, hear, smell, and even feel the heat

emanating from the large number of vacuum tubes. The computers served the useful purposeof providing warmth in a cold room in the winter.]

The first practical MOS transistors were made in the early sixties and prototype

integrated circuits began to be made around 1970. It took several decades of

engineering work by competing companies to make the present, inexpensive

computers, with millions of silent, reliable MOS logic gates and memories on the

surface of a piece of silicon about the size of a quarter. The tubes were replaced at first

by the semiconductor bipolar junction transistor, BJT. Computers were made mainly with

mass fabricated, BJT integrated circuits in the 60s and 70s. However, in the 80s MOS

digital circuits became increasingly preferred for large logic and memory arrays

because of their lower standby power consumption. This advantage is due to the

nearly infinite input resistance of the control-gate input terminal, which controls theflow of electrons between the source and drain output terminals, just as the grid controlled

the flow of electrons in the vacuum tube.

The MOS transistor device and the digital logic and memory circuits that can be made fromit are an outstanding technology achievement attributed to many engineers and material

scientists, with backgrounds similar to the students in this class. Therefore, it is a good ideato pay respect to their work by making a special effort to master the basic principles that

went into their inventions that gave us the computer technology of today. The many future

applications that engineers will work on in the 21st century, including the integrated

engineering systems within a silicon chip (called MEMS for micro-electromechanical

systems), could eventually exceed the impact of the computer. They are built on the

foundation of the computer engineers of the last five decades. The micron-sized

electromechanical structures are evolving so that they can be designed for functions

involving e.g. optical signals, fluid flow, and biological and chemical systems.

Examples are the high speed testing of drugs (Orchard Inc.) the reproduction andtesting of DNA molecules, and the manufacture of robots the size of dust mites. These

robots are able to travel within the body taking photographs, and fly through caves

with video and sound recording devices. A pre-requisite for this course is to be a

member of the IEEE so that you can keep up with these exciting developments.

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Table 4.1 Resistivity of Microelectronics Materials

Microelectronic Materials Resistivity [-cm]

Copper 1.7 * 10-6

Gold 2.3 * 10-6

Aluminum 2.67 * 10-6

Tungsten 5.4 * 10-6

Tantulum 13.5 * 10-6

Tungsten Silicide [WSi2] 12 < < 55 * 10-6

Polysilicon (used as a conductor) ~500 * 10-6

Platinum Silicide (PtSi) 30 * 10-6

Silicon (value depends on the concentration of the dopant) 10-4 < < 10+5

Intrinsic GaAs 4 * 108

Intrinsic CdTe 1010

SiC 1010

SiO2 (55% Relative Humidity) 1017

SiO2 (80% Relative Humidity) 1016

High Resitivity Glass (60% Relative Humanity) ~1018

Note that the range of resistivity available to the microelectronic engineers is from 10-6 to

~10+8-cm., a 1024 range

Table 4.2 Summary of the Properties of Intrinsic, N-type and P-type Silicon

Type Charges Concentration [cm] -1 [cm]

Intrinsic

mobileelectrons, ni

ni = 1010 2.4 * 10

-6(for n = 1500 [cm

2/v-sec])0.416 * 106

mobile

holes, pipi = 10

102.4 * 10-6

(for p = 500 [cm2/v-sec])

0.125 * 106

n-type

positivefixed

ionized

donors

1015 ND 1019

0.24

(n = 1500 [cm2/v-sec] for ND = 10

15)4.16

160(n = 100 [cm

2/v-sec] for ND = 1019)

6.25 * 10-3

p-type

negative

fixed

ionized

donors

1015 NA 1019

0.0768(p = 480 [cm

2/v-sec] for NA = 1015)

13

80

(p = 50 [cm2/v-sec] for NA = 10

19)0.0125

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Figure4.1SummaryoftheCh

aracteristicsandStructuresofMOSTransistors

Drain

Characteristics

TransferC

haracteristics

SymbolandStructure

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Name

1)N-EMOST

Electronsmovefromsourcetod

rain.

e.g.VT=+1[V]

K

=2[mA/V2]

/tox=250[A/V2]

W/L=8

2)P-EMOST

Holesmovefromsourcetod

rain.

e.g.VT=-1[V]

K=2[mA/V2]

/tox=100[A/V

2]

W/L=20

3)N-DMOST

e.g.VT=-2[V]

K=2[mA/V2]

/tox=250[A/V2]

W/L=8

4)P-DMOST

e.g.VT=+

1[V]

K=2[mA/V2]

/tox=100[A

/V2]

W/L=20

Fig 4.2 Basic Concepts for Current in Semiconductor Material

electrons

holest

LW

I

+V

I

[V/cm]26


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1)][][

][][][

cmtcmW

cmLcmR

=

2) [ohm cm] = n [cm 3] q [coul ] N [cm2 /volt-sec] + pqP= 1/ = conductivity = resistivity in inverse ohm cmP = hole mobility [cm2 /volt-sec] N = electron mobility [cm2 /volt-sec]p= hole concentration in number of holes per cubic centimeter.

n= electron concentration in number of electrons per cubic centimeter.

Four Types of Charges in Semiconductor Devices

----- mobile free electrons (negatively charged)

----- mobile free holes (positively charged) Essentially a hole is a vacancy

in the normal co-valence bonding between adjacent atoms.

----- Immobile positively charged donor atoms that have ionized and

donated a free electron to the surrounding semiconductor region.

Ionized atoms are immobile, i.e. they do not move under the

influence of an electric field, unless the temperature is extremely high.

----- Immobile negatively charged acceptor atoms that have acceptedan electron from their surroundings. Taking the electron effectively

creates a positive mobile hole that has some mobility, or will move,

under the influence of an electric field. A voltage applied across a

region with negatively charged acceptors and free holes will result in

current due to the motion of the mobile holes.

Fig 4.3 Structure of the MOS Transistor

Fig 4.3a The MOS Sandwich (Cross-section of the E-MOST)Metal plate

oxide

Semiconductor plate

ohmic contact to

lower plate

G

B

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Fig 4.3b Structure of the E-MOST (Enhancement Mode MOSFET)

LD

lm

tox

ld

1000 < lm

< 10,000

0.1 < ld< 1 m

50 < tox

< 1000

200 < LD

< 300 m

P- Substrate

S/D S/DG

channel

Low resistivity metal

e.g. aluminum, = 2.7 [cm]

Oxidized Silicone = SiO2

1010 < ox < 1012

Heavily doped N+-type

Silicone, e.g. n = 1019 [cm-3]

P- Substrate

e.g. NA = 10-15 [cm-3]

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Fig 4.4 Models Outlining the Physical Behavior of the MOS Capacitor

for Different Gate Voltages

Fig 4.4a

Fig 4.4b

Fig 4.4c

Fig 4.4d VG -1, -2, etc.

Metal

Oxide

P-typeMOS Capacitor

Depletion Region

(depleted of

mobile charge)

el elcurrrent

el

0.9 [V]< V

T= +1 [V]

Metal

Oxide

P-type

VG

+ 0.9 [V]

VG + 1.1 [V]

N+ N+

Metal

Oxide 1.1 [V]> V

T= +1 [V]

Source or

Drain Well

Mobile electrons that can

move between the source

and drain terminals

Induced electron charge in channel.

Channel thickness is only several atomic layers

N+

Metal

Oxide

VG

+ 2 [V]

2 [V]

> VT

= +1 [V]

The increase in the number of electrons increases

the conductivity of the channel.

More current flows from the drain to the source

for the same value of drain to source voltage, VDS

.

= mobile holes

= mobile electro

= fixed ionize

acceptors

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Fig 4.5 Exercises to Develop Understanding of the MOST Regions of

OperationGiven VDS = VGS VT and ID = 1 [mA]. Find the values for VDS and VGS for the

MOST circuits. Please identify the regions of operation, i.e. S, L, and CO, and the

reason for why the transistor is e.g. in the saturation region.

A step-by-step approach to do the exercise is suggested:a) Draw the direction of current flow and add the plus/minus sign for the

voltage drops across the resistors and show the values of the drops.

b) Write a small S and D at the source and drain terminals, taking into

account the current directions for the P and N transistors.c) Find the voltage at the source and dra

lesson 4 complete

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