leonardospectrum reference manual

LeonardoSpectrum for AlteraReference Manual

Software Version v2001.1

July 2001

Copyright © 2001 Exemplar Logic, Inc., A Mentor Graphics Company. All rights reserved.This document contains information that is proprietary to Exemplar Logic, Inc and may be duplicated inwhole or in part by the original recipient for internal business purposes only, provided that this entire noticeappears in all copies. In accepting this document, the recipient agrees to make every reasonable effort toprevent the unauthorized use of this information.

This document is for information and instruction purposes. Exemplar Logic reserves the right to makechanges in specifications and other information contained in this publication without prior notice, and thereader should, in all cases, consult Exemplar Logic to determine whether any changes have been made.

The terms and conditions governing the sale and licensing of Exemplar Logic products are set forth inwritten agreements between Exemplar Logic and its customers. No representation or other affirmationof fact contained in this publication shall be deemed to be a warranty or give rise to any liability ofExemplar Logic whatsoever.

DISCLAIMER

ALTHOUGH EXEMPLAR LOGIC, INC HAS TESTED THE SOFTWARE AND REVIEWED THEDOCUMENTATION, EXEMPLAR LOGIC, INC MAKES NO WARRANTY OR REPRESENTATION,EITHER EXPRESSED OR IMPLIED, WITH RESPECT TO THIS SOFTWARE AND DOCUMENTATION,ITS QUALITY, PERFORMANCE, MERCHANTABILITY, OR FITNESS FOR A PARTICULARPURPOSE.

EXEMPLAR LOGIC SHALL NOT BE LIABLE FOR ANY INCIDENTAL, INDIRECT, SPECIAL, ORCONSEQUENTIAL DAMAGES WHATSOEVER (INCLUDING BUT NOT LIMITED TO LOST PROFITS)ARISING OUT OF OR RELATED TO THIS PUBLICATION OR THE INFORMATION CONTAINED IN IT,EVEN IF EXEMPLAR LOGIC INC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

RESTRICTED RIGHTS LEGEND 03/97

U.S. Government Restricted Rights. The SOFTWARE and documentation have been developed entirelyat private expense and are commercial computer software provided with restricted rights. Use,duplication or disclosure by the U.S. Government or a U.S. Government subcontractor is subject to therestrictions set forth in the license agreement provided with the software pursuant to DFARS 227.7202-3(a) or as set forth in subparagraph (c)(1) and (2) of the Commercial Computer Software - RestrictedRights clause at FAR 52.227-19, as applicable.

Contractor/manufacturer is:Exemplar Logic Inc.

880 Ridder Park Drive, San Jose, CA 95131web site: http://www.exemplar.com

email: [email protected]

TRADEMARKS

Exemplar Logic™ and its Logo are trademarks of Exemplar Logic, Inc. LeonardoSpectrum™,LeonardoInsight™, TimeCloser™, FlowTabs™, HdlInventor™, SmartScripts™,P&RIntegrator™,DesktopASIC™, XlibCreator™, SynthesisWizard™, and MODGEN™ are trademarks of Exemplar Logic,Inc.; Model Sim/VHDL™, Model Sim™, and V-System/Verilog™ are trademarks of Model Technology,Inc.; Renoir™, Monet™, and PackagedPower™ are trademarks of Mentor Graphics Corporation.Verilog® and Verilog-XL® are registered trademarks of Cadence Design Systems, Inc. All othertrademarks remain the property of their respective owners.

http://www.exemplar.com

Table of Contents

...

........ 1-1.... 1-1..... 1-2...... 1-2..... 1-3...

... 1-3

..... 1-4.... 1-5..... 1.... 1-7..... 1.....

..... 2-2... 2-3... 2-3.... 2-4.... 2-... 2-5

..

.

... 2-10.

TABLE OF CONTENTS

Chapter 1Introduction ............................................................................................................................. 1-1

Shell-Level Commands......................................................................................................... 1-1Invoking the Graphical User Interface...............................................................................Invoking LeonardoSpectrum in Batch Mode.....................................................................

The Tcl Command Interface ................................................................................................Standard Tcl Commands..................................................................................................LeonardoSpectrum Tcl Commands ..................................................................................Setting Tcl Variables .......................................................................................................... 1-3Setting Attributes ................................................................................................................... 1-3Methods for Using Commands With a Tcl Script ..............................................................Commands Restricted to Level 3......................................................................................Command Line Description...............................................................................................Tcl Scripting Language.....................................................................................................-6Command Syntax Definitions............................................................................................

The Design Data Model .......................................................................................................-8Accessing Design Data ........................................................................................................ 1-9

Chapter 2Attributes .................................................................................................................................... 2-1

How to Set Attributes ............................................................................................................. 2-1(1) Using the VHDL attribute construct .............................................................................(2) Using a Verilog directive ..............................................................................................(3)Using the Interactive Command Line Shell ...................................................................(4) Using a LeonardoSpectrum Constraint File .................................................................

List of Pre-Defined Attributes ..............................................................................................5array_pin_number (VHDL only) ........................................................................................arrival_time............................................................................................................................ 2-5auto_dissolve ......................................................................................................................... 2-6buffer_sig ............................................................................................................................... 2-7clock_cycle ............................................................................................................................ 2-7clock_offset............................................................................................................................ 2-8dont_touch ............................................................................................................................. 2-8input_drive ............................................................................................................................. 2-9input_max_fanout ................................................................................................................ 2-9input_max_load .................................................................................................................... 2-9lut_max_fanout ...................................................................................................................... 2-9map_complex......................................................................................................................... 2-9map_complex_reg_type....................................................................................................modgen_select .................................................................................................................... 2-10no_buff................................................................................................................................. 2-10noopt .................................................................................................................................... 2-11

LeonardoSpectrum for Altera Reference Manual, v2001.1d iii

TABLE OF CONTENTS [continued]

Table of Contents

.

..... 3-2

........... 3-2....... 3-3..... 3-....

.

.

..... 3-4

....

..... 3-5

..

.......... 3

..............

nopad.................................................................................................................................... 2-11output_fanout ....................................................................................................................... 2-12output_load .......................................................................................................................... 2-12pad........................................................................................................................................ 2-12pin_number .......................................................................................................................... 2-12preserve_driver .................................................................................................................... 2-13preserve_signal .................................................................................................................... 2-14pulse_width.......................................................................................................................... 2-14required_time ....................................................................................................................... 2-14simple_register..................................................................................................................... 2-15

Chapter 3Variables ..................................................................................................................................... 3-1

Tcl Syntax ................................................................................................................................. 3-1The Variable Editor ................................................................................................................. 3-2List of Variables........................................................................................................................ 3-2

allow_black_box_modgens ..............................................................................................alt_auto_fast_io...................................................................................................................... 3-2alt_auto_register_packing.................................................................................................3-2altera_allow_cascade_fanout ...........................................................................................altera_cascade_chain_length ..........................................................................................altera_map_complex_ios ..................................................................................................3altera_use_cascades ........................................................................................................... 3-3area_weight ............................................................................................................................ 3-3auto_dissolve_limit ............................................................................................................... 3-4balance_adders...................................................................................................................... 3-4big_mux_percentage_for_lut ............................................................................................bubble_tristates ...................................................................................................................... 3-4buffer_for_timing................................................................................................................... 3-5check_complex_ios............................................................................................................. 3-5comm_socket ........................................................................................................................ 3-5complex_ios ........................................................................................................................... 3-5constraints_save_only_multicycle ....................................................................................critical_path_clustering........................................................................................................ 3-5critical_path_restructuring ................................................................................................. 3-6cross_probe_tool_name ...................................................................................................-6default_bdbuf ......................................................................................................................... 3-6default_input_arrival.............................................................................................................. 3-6default_input_buffer ............................................................................................................. 3-6default_output_buffer ......................................................................................................... 3-6default_output_required..................................................................................................... 3-6default_register_arrival ........................................................................................................ 3-7default_register_required ................................................................................................... 3-7

LeonardoSpectrum for Altera Reference Manual, v2001.1div


Table of Contents

...

..... 3-8

....

...

.... 3-...... 3-..... 3-9... 3-10... 3-10... 3-10.... 3-10.. 3-10... 3-11... 3-11... 3-11... 3-11

....

... 3-13

.... 3-..

.... 3-14.... 3.... 3-.

default_tribuf ......................................................................................................................... 3-7delay_break_loops .............................................................................................................. 3-7delay_weight .......................................................................................................................... 3-7dont_lock_lcells ..................................................................................................................... 3-7drc_const_nets ....................................................................................................................... 3-8edif_array_range_extraction_style....................................................................................edif_eqn_and.......................................................................................................................... 3-8edif_eqn_not .......................................................................................................................... 3-8edif_eqn_not_is_prefix ...................................................................................................... 3-8edif_eqn_or ............................................................................................................................ 3-9edif_function_property ....................................................................................................... 3-9edif_write_arrays ................................................................................................................... 3-9edif_write_internal_properties...........................................................................................9edifin_ground_net_names................................................................................................9edifin_ground_port_names ...............................................................................................edifin_ignore_port_names ................................................................................................edifin_power_net_names ..................................................................................................edifin_power_port_names ................................................................................................edifout_ground_net_name ...............................................................................................edifout_no_prims_in_noopt...............................................................................................edifout_power_ground_style_is_net.................................................................................edifout_power_net_name..................................................................................................edifout_write_noopted_contents.......................................................................................enable_dff_map_optimize ................................................................................................encoding............................................................................................................................... 3-11exclude_gates....................................................................................................................... 3-12extract_cin_cout................................................................................................................... 3-12extract_counter..................................................................................................................... 3-12extract_cse ........................................................................................................................... 3-12extract_decoder .................................................................................................................... 3-12extract_ram .......................................................................................................................... 3-12extract_reduction_ops......................................................................................................3-13extract_rom .......................................................................................................................... 3-13flex_auto_implement_in_eab............................................................................................flex_lock_lcells .................................................................................................................... 3-13force_user_load_values ...................................................................................................13fsm_do_collapse ................................................................................................................ 3-14fsm_flow .............................................................................................................................. 3-14full_case ............................................................................................................................... 3-14generate_timespec_from_inputs ......................................................................................hdl_array_name_style ......................................................................................................-15hdl_array_separator_style ................................................................................................15hdl_input_location .............................................................................................................. 3-15

LeonardoSpectrum for Altera Reference Manual, v2001.1d v


Table of Contents

.... 3-

.... 3-..

.. 3-16

........ 3-.... 3-1.. 3-1.... 3-18

.

.

..

... 3... 3-2.... 3-21.. 3-21... 3-21... 3-21... 3-22

..

..

... 3-

.. 3-22

... 3-. 3-23

hdl_integer_name_style ...................................................................................................15hdl_record_name_style ....................................................................................................16hdl_write_inv_as_cell ........................................................................................................3-16input2output ......................................................................................................................... 3-16input2register ....................................................................................................................... 3-16insert_bufs_for_internal_clock ..........................................................................................inversion_prefix ................................................................................................................... 3-17keep_flattened_views.......................................................................................................3-17lgen_array_name_style ....................................................................................................17list_design_object_separator............................................................................................7load_library_file_extension ...............................................................................................7lpm_remove_unused_ports ..............................................................................................lut_buffering ........................................................................................................................ 3-18lut_cell_name....................................................................................................................... 3-18lut_max_fanout .................................................................................................................... 3-18map_fanin_limit................................................................................................................... 3-18map_sync_reg ..................................................................................................................... 3-18max_cap_load ..................................................................................................................... 3-19max_fanin ............................................................................................................................ 3-19max_fanout_load ............................................................................................................... 3-19max_lock_lcells ................................................................................................................... 3-19max_pt ................................................................................................................................. 3-19max_transition ..................................................................................................................... 3-20maxarea................................................................................................................................ 3-20maxdly ................................................................................................................................. 3-20maxplusii_exec_path ........................................................................................................-20mem_minimum_size.........................................................................................................0modgen_select .................................................................................................................... 3-21move_files_on_cwd_change.............................................................................................multi_driver_drc_resolving ...............................................................................................names_collision_extension ...............................................................................................no_boundary_optimization ...............................................................................................no_sequential_cell_replication .........................................................................................nowire_table......................................................................................................................... 3-22old_style_session_file........................................................................................................ 3-22operating_condition ........................................................................................................... 3-22optimize_clock_enable .....................................................................................................22optimize_clock_enable_support_limit...............................................................................optimize_cpu_limit ............................................................................................................. 3-22optimize_drc_resolving .....................................................................................................23optimize_timing_cpu_limit.................................................................................................package ................................................................................................................................ 3-23parallel_case......................................................................................................................... 3-23

LeonardoSpectrum for Altera Reference Manual, v2001.1dvi


Table of Contents

... 3-2.... 3-.... 3-24.... 3.... 3

...... 3-....... 3-25... 3-2

.... 3-.... 3-.... 3-26... 3-27.... 3-2... 3-27....... 3-28........ 3-...... 3-29

...

..... 3-30

... 3-30

.... 3-

.... 3-3

part ....................................................................................................................................... 3-23prepend_dff_inst_name ....................................................................................................4prepend_io_inst_name .....................................................................................................24prepend_latch_inst_name ................................................................................................prepend_tri_inst_name.....................................................................................................-24preserve_dangling_net .....................................................................................................-24process ................................................................................................................................. 3-24process_pragma ................................................................................................................. 3-25propagate_clock_delay ....................................................................................................25pterm_max_fanin ............................................................................................................... 3-25quartus_exec_path ............................................................................................................ 3-25quick_enable_dff_map_optimize.......................................................................................ram_inference_blackbox...................................................................................................5register2output ..................................................................................................................... 3-26register2register ................................................................................................................... 3-26replicate_logic_for_drc ......................................................................................................3-26replicate_logic_for_timing.................................................................................................26report_area_format_style .................................................................................................26report_delay_analysis_mode ...........................................................................................report_delay_arrival_threshold .........................................................................................report_delay_detail ............................................................................................................. 3-27report_delay_format_style ................................................................................................7report_delay_slack_threshold ...........................................................................................resolve_mux_stat ............................................................................................................... 3-28resource_sharing ................................................................................................................. 3-28resource_sharing_through_pattern...................................................................................restructure_for_timing ......................................................................................................3-28sdf_hier_separator............................................................................................................... 3-28sdf_hierarchical_names ...................................................................................................28sdf_names_style.................................................................................................................. 3-29sdf_read_suppress_warnings ..........................................................................................sdf_type................................................................................................................................ 3-29sdf_write_flat_netlist ........................................................................................................... 3-29state_table_threshold ........................................................................................................ 3-30sweep_in_fe ......................................................................................................................... 3-30sweep_unused_user_cells ...............................................................................................temp ..................................................................................................................................... 3-30timing_characterize_print_constraints..............................................................................transformations .................................................................................................................... 3-30tristate_map.......................................................................................................................... 3-31ungroup_hier_separator ...................................................................................................31use_assign_for_vcc_gnd..................................................................................................1use_dffenable ....................................................................................................................... 3-31

LeonardoSpectrum for Altera Reference Manual, v2001.1d vii


Table of Contents

.. 3-3... 3-32... 3-32.... 3-32

... 3-

... 3-33

.

..

... 3-34.... 3-34.. 3-... 3-34... 3-34.. 3-34... 3-35.... 3-35

... 3-3

.

...

..

.. 4-1

.... 4-1

..... 4-4.....

user_verbose ........................................................................................................................ 3-31verilog_max_line_length ...................................................................................................2verilog_parameter_to_attribute.........................................................................................verilog_read_ignore_input_assign_errors ........................................................................verilog_write_arrays .......................................................................................................... 3-32verilog_write_pwr_gnd_cells ............................................................................................vhdl_87 ................................................................................................................................ 3-32vhdl_generic_to_attribute .................................................................................................33vhdl_identifiers_lower_case .............................................................................................vhdl_write_87 ...................................................................................................................... 3-33vhdl_write_arrays ............................................................................................................... 3-33vhdl_write_bit ...................................................................................................................... 3-33vhdl_write_bit_vector ........................................................................................................3-33vhdl_write_component_package ......................................................................................vhdl_write_component_package_name...........................................................................vhdl_write_configuration...................................................................................................34vhdl_write_inst_uppercase ...............................................................................................vhdl_write_port_uppercase...............................................................................................vhdl_write_pwr_gnd_cells.................................................................................................vhdl_write_signal_uppercase............................................................................................vhdl_write_use_packages ................................................................................................viewlogic_vhdl..................................................................................................................... 3-35virtex_apply_maxskew .....................................................................................................5voltage.................................................................................................................................. 3-35wire_load_library................................................................................................................. 3-36wire_load_mode.................................................................................................................. 3-36wire_table............................................................................................................................. 3-36wire_tree .............................................................................................................................. 3-36write_lut_binding................................................................................................................. 3-36write_xrf_file ....................................................................................................................... 3-37x_probe ................................................................................................................................ 3-37x_probe_autocopy............................................................................................................. 3-37xdb_write_version ............................................................................................................. 3-37xor_decomp ......................................................................................................................... 3-37

Chapter 4Shell-Level Commands............................................................................................................

Invoking the GUI using the leonardo Command..................................................................leonardo ................................................................................................................................. 4-2

Batch Mode Operations using the spectrum Command ......................................................Options and Switches........................................................................................................4-4

License Information................................................................................................................ 4-20Tcl Script Sourcing ................................................................................................................. 4-20

LeonardoSpectrum for Altera Reference Manual, v2001.1dviii


Table of Contents

. 4-20

.. 4-21

.... 5-1

..... 5-2

..

....

..... 5

.

.

...

... 5-

GUI Menu Bar File -> Run Script ......................................................................................Command Line with Path to LeonardoSpectrum ..............................................................

Chapter 5Tcl Commands.......................................................................................................................

Command Summary .........................................................................................................Commands ................................................................................................................................ 5-6

Aliases.................................................................................................................................... 5-6add_rename_rule.................................................................................................................. 5-8alias ...................................................................................................................................... 5-11all_clocks ............................................................................................................................. 5-13all_inputs.............................................................................................................................. 5-14all_outputs............................................................................................................................ 5-15all_registers.......................................................................................................................... 5-16all_selected........................................................................................................................... 5-17apply_rename_rules .........................................................................................................5-18auto_read.............................................................................................................................. 5-19auto_write ............................................................................................................................ 5-20balance_loads....................................................................................................................... 5-21blackbox............................................................................................................................... 5-23bubble_tristates .................................................................................................................... 5-24clean_all ............................................................................................................................... 5-25connect ................................................................................................................................. 5-26connect_path ........................................................................................................................ 5-28copy...................................................................................................................................... 5-30create .................................................................................................................................... 5-32create_rename_ruleset ....................................................................................................-34create_wrapper..................................................................................................................... 5-35decompose_luts................................................................................................................... 5-37dfs......................................................................................................................................... 5-39disconnect ............................................................................................................................ 5-40disconnect_path .................................................................................................................. 5-42do_ip .................................................................................................................................... 5-44dont_touch ........................................................................................................................... 5-48extract_best_passes........................................................................................................... 5-49find ....................................................................................................................................... 5-50file_line_search.................................................................................................................... 5-53fix_backanno........................................................................................................................ 5-54getlist.................................................................................................................................... 5-55global_set_attribute.............................................................................................................. 5-56global_remove_attribute ...................................................................................................57group .................................................................................................................................... 5-58help....................................................................................................................................... 5-60

LeonardoSpectrum for Altera Reference Manual, v2001.1d ix


Table of Contents

.

.

..

.

.. 5-108

.. 5-..

. 5..

list_attributes........................................................................................................................ 5-62list_connection ..................................................................................................................... 5-64list_design ............................................................................................................................ 5-66list_technologies .................................................................................................................. 5-69lo2up .................................................................................................................................... 5-70load_library .......................................................................................................................... 5-71load_modgen........................................................................................................................ 5-73move..................................................................................................................................... 5-75move_nodelay..................................................................................................................... 5-77noopt .................................................................................................................................... 5-78optimize ............................................................................................................................... 5-79optimize_timing ................................................................................................................... 5-84place_and_route .................................................................................................................. 5-87pop_design ........................................................................................................................... 5-90pre_optimize ........................................................................................................................ 5-91present_design ..................................................................................................................... 5-93print_design_stack ............................................................................................................. 5-94push_design ......................................................................................................................... 5-95puts_log................................................................................................................................ 5-96read....................................................................................................................................... 5-97read_constraints ................................................................................................................. 5-101recompose_flex................................................................................................................. 5-102remove ............................................................................................................................... 5-103remove_attribute ................................................................................................................ 5-105remove_clock..................................................................................................................... 5-107remove_rename_ruleset ...................................................................................................report_area ......................................................................................................................... 5-109report_constraints............................................................................................................... 5-111report_delay ....................................................................................................................... 5-113report_rename_rules ........................................................................................................117report_wire_tables ............................................................................................................5-118restore_project_script........................................................................................................5-119select .................................................................................................................................. 5-120set_altera_eqn .................................................................................................................... 5-122set_attribute........................................................................................................................ 5-123set_clock ............................................................................................................................ 5-125set_multicycle_path ..........................................................................................................-126show_var_settings............................................................................................................5-128unalias ................................................................................................................................ 5-129undont_touch ..................................................................................................................... 5-130unfold ................................................................................................................................. 5-131ungroup .............................................................................................................................. 5-132unmap................................................................................................................................. 5-134

LeonardoSpectrum for Altera Reference Manual, v2001.1dx


Table of Contents

. 5

unnoopt .............................................................................................................................. 5-135up_design ........................................................................................................................... 5-136view_schematic.................................................................................................................. 5-137warp_vhdl .......................................................................................................................... 5-138write ................................................................................................................................... 5-139xmplr_exec......................................................................................................................... 5-143xmplr_socket_client..........................................................................................................-144

LeonardoSpectrum for Altera Reference Manual, v2001.1d xi

Table of Contents

LeonardoSpectrum for Altera Reference Manual, v2001.1dxii

Figure 1-1. Relationship between Commands, Variables, and Attributesl.............................. 1-2

LIST OF FIGURES

Table of Contents

.... 1-10... 1-10.... 5-2

LIST OF TABLES

Table 1-1. Commands that Generate Lists .........................................................................Table 1-2. Examples of Commands that Generate Lists ....................................................Table 5-1. Alphabetical Command Summary .....................................................................

LeonardoSpectrum for Altera Reference Manual, v2001.1d xiii

LIST OF TABLES [continued]

Table of Contents

LeonardoSpectrum for Altera Reference Manual, v2001.1dxiv

al

Chapter 1Introduction

Shell-Level Commands

Invoking the Graphical User Interface

You invoke the LeonardoSpectrum GUI with theleonardo command. Optional commandswitches allow you to customize the invocation. Theleonardo command usage is fullydocumented in the section titledInvoking the GUI using the leonardo Commandstarting onpage4-1

Invoking LeonardoSpectrum in Batch Mode

You can invoke LeonardosSpectrum in batch mode by using thespectrum command. You cancustomize and control each batch run by setting command switches and specifying optionarguments to this command. The details about using thespectrumcommand are documented inthe section titledBatch Mode Operations using the spectrum Commandstarting on page4-4.

LeonardoSpectrum for Altera Reference Manual, v2001.1d 1-1

The Tcl Command Interface Introduction

in

r. This

an

mands,

The Tcl Command InterfaceThe LeonardoSpectrum Graphical User Interface is based on the Tcl language. As shownFigure 1-1, Standard Tcl Commands provide a foundation for the command structure.LeonardoSpectrum Tcl command extensions proved the major synthesis processing powepower is directed by the setting of Tclvariables.Global constraints and directives arecommunicated to LeonardoSpectrum in this manner. A further level of control is exercisedwhen you setattributeson in-memory design objects. The message communicated throughattribute overrides the message communicated by setting value of a variable.

Figure 1-1. Relationship between Commands, Variables, and Attributesl

Standard Tcl Commands

LeonardoSpectrum accepts all standard commands of the Tcl language. Tcl supports comthat include: variable assignment, handling of lists and arrays, sorting, string manipulationarithmetic operations, (if/case/foreach/while) statements, and procedures.

Sets GlobalConstraints/Directives

Provides aFoundation

Overrides a Variableon a Design Object

Adds the Powerof Synthesis

LeonardoSpectrum for Altera Reference Manual, v2001.1d1-2

Introduction The Tcl Command Interface

le andas the

ying

m

bes a

pair. In

e

yation.

the

the

LeonardoSpectrum Tcl Commands

Exemplar Logic has added a number of command extensions to the Tcl language to handsupport the synthesis process. These commands are “built-in” and are executed the samestandard Tcl commands.

Setting Tcl Variables

The Tcl language supports the concept of variables. Variables are set and unset with thestandard Tclset andunset commands.Global constraints and directives are communicated bthe setting of variables and you can re-direct the behavior of LeonardoSpectrum by changthe value of variables.

Setting Attributes

An attribute is information that is attached to (owned by) an object in the LeonardoSpectruin-memory design database. Attributes allow users to fine tune the synthesis process.

Attributes take precedence over variables.

An attribute has a name, a type, a value, and an owner. An attribute’s value typically descricharacteristic about the design object. Many times the information is used tooverridea globalconstraint that is applied to the design as a whole by setting a Tcl variable.

The concept of an attribute in an HDL language is the same. The attribute is a name/valuethat is associated with, (“attached to”, “set on”, or “owned by”) a design object in the designVHDL, the attribute construct may be used to associated a design object with an attributvalue and in Verilog, a//exemplar attribute directive may be use. If these attributes aredeclared in the source files, the HDL attributes are converted to attributes in the in-memordatabase and many time are translated as EDIF properties during an EDIF netlisting operIf you are aLevel 3 user, you can attach an attribute to an in-memory design object by usingset_attribute command in the interactive command line window. Executing theunset_attribute command removes the attribute. Sometimes setting a variable also setsassociated attribute.

Methods for Using Commands With a Tcl Script

After you create a Tcl script in a standard text editor, you can source your Tcl script fromLeonardoSpectrum as follows:

• The Interactive Command Line Shell (Level 3)

• The GUI Menu Bar File -> Run Script



ary

your

• The Shell Command Line with a Path to LeonardoSpectrum

Note: The Exemplar history file is a Tcl script file that you can use after making the necessedits.

Interactive Command Line Shell (Level 3)

Type the following syntax to source your Tcl script:

source <my_tcl_script>

GUI Menu Bar File -> Run Script

On the menu bar click onFile -> Run Script. Type in your Tcl script name or click on thebutton and choose a Tcl script file. Your script file runs in the GUI Information window.

Command Line with Path to LeonardoSpectrum

Bring up your PC or UNIX window. In the LeonardoSpectrum install area, locate where$EXEMPLARpoints to the location of the software. Type the appropriate argument to sourceTcl script:

UNIX : $EXEMPLVAR/bin/spectrum -file <my_tcl_script>

PC DVOS: $EXEMPLAR/bin/win32/spectrum -file <my_tcl_script>

Commands Restricted to Level 3

The commands listed in this reference manual and the Tcl script methods for using thecommands are available to Levels 1, 2, and 3 with the following restrictions:

• The interactive command line shell (GUI window) is available only toLevel 3.

• The following commands are only available inLevel 3:

o elaborate

o analyze

o group

o unfold



and

nd

e the

r

ard

Command Line Description

Command and Option Abbreviation

LeonardoSpectrum allows abbreviated Tcl commands: you only need to spell out a communtil the command meaning is unambiguous.

For example, the commandpre_opt executes thepre_optimize command. If the command isstill ambiguous, LeonardoSpectrum produces an error message. For example, the commapredisplays the following:

ambiguous command “pre”: pre_optimize present_design preserve_signa

The LeonardoSpectrum commands also allow abbreviated options: you do not need to typoptions in full; only type the part that makes the option unambiguous.

For example,pre_optimize -c enables the-common_logic option for thepre_optimizecommand.

Aliasing

LeonardoSpectrum offers analia s command, which allows you to define your own name focommonly used command strings. For example, if you frequently use the commandlist_design -ports , then you may want to write an alias:

If you now type the command lp, LeonardoSpectrum executeslist_design -ports .

Redirecting Output

Almost all commands from the LeonardoSpectrum command list print information to standoutput (normally the screen). Standard output can be redirected into a file. For example:

All messages from theoptimize command are then redirected into the fileoptimize.log .

All messages from the command are appended to the filetotal.log .

alias lp list_design -ports

optimize -target xi4 > optimize.log

optimize -target xi4 >> total.log



areted

nds

at

ndy

m

want

Error messages are not redirected to a file when you use this method of redirection. Theydisplayed on your screen. Therefore, you always know whether or not a command complesuccessfully.

Command Line Help

You can display information about commands by using thehelpcommand. Thehelpcommanduses a regular expression (a name with or without wildcards), and prints usage for commathat match the regular expression. For example, you can typehelp * to bring up a transcriptlist of all commands. Typinghelp pre* displays information about all commands that startwith the stringpre .

Also, every command takes-help as an option.

is the same as:

Tcl Scripting Language

LeonardoSpectrum accepts all commands of the Tcl language. Tcl supports commands thinclude: variable assignment, handling of lists and arrays, sorting, string manipulation,arithmetic operations, (if/case/foreach/while) statements, and procedures. Tcl is VERY hafor writing scripts for LeonardoSpectrum.

The Tcl command,source <my_tcl_script> , enables you to source (execute) script files froLeonardoSpectrum, or from within other script files. This feature allows you to writecustomized (portions of) design flows, or any other sequence of commands that you mayto execute.

A feature inherited from Tcl isautoexec: all UNIX (and many DOS) commands availablefrom your path can be run from the LeonardoSpectrum command line. Another helpful Tclfeature is history tracking. Type the commandhistory to view your previous commands. Anyprevious command can be re-executed using! NUMBER,or !! for re-execution of the lastcommand.

Customizing the Command Line Interface

LeonardoSpectrum loads the following script file when starting up:

pre_optimize -help

help pre_optimize

$EXEMPLAR/data/exemplar.ini



ep

e in

C.

vides

line

You can customize the command line interface by modifying theexemplar.ini file.Frequently used aliases and several Tcl procedures, such asview_schematic andpush_design , are defined in this file. You can add your own definitions to this file. If you havanexemplar.ini file in your local directory, LeonardoSpectrum loads this file during startuinstead of$EXEMPLAR/data/exemplar.ini . Source$EXEMPLAR/data/exemplar.ini fromyour local file, rather than copying and then modifying this file so that any changes to this filthe next LeonardoSpectrum release will be picked up. For example, to add an alias formy_command, create a file in your local directory calledexemplar.ini and add the followinglines:

Command Syntax Definitions

The command list character symbols are defined as follows:

• [ ] optional arguments

• < > fields to be completed with your names

• | “or” symbol indicates mutually exclusive arguments

In the read command theread <file_name(s)> field is replaced with your file name(s). Forexample:read fsm.vhd data.vhd top.vhd .

In the read command the optional argument of[-format <format_name>] is entered as-format vhdl .

The optional arguments:[-parameters <parameters_list>] | [-generics <generics_list>]are mutually exclusive. Only one argument may be used as indicated by the | “or” symbol.

Always use the forward slash character (/) to separate directory names in a path, even on the PLeonardoSpectrum interprets the back slash character (\) as a Tcl escape character.

LeonardoSpectrum turns your HDL code into a design database while LeonardoInsight protools for exploring and interacting with the design. This chapter provides a brief tour of thedesign database and describes methods for using commands on the interactive commandshell.

source $env (EXEMPLAR)/data/exemplar.inialias MC my_command


The Design Data Model Introduction

ta

ldings of

vel of

peur

hen

ns,

view

The Design Data ModelThe LeonardoSpecturm in-memory design data base is modeled after the EDIF design damodel. All design data is stored in a set of EDIF-type libraries which start at theroot . A librarycontains a list of cells, and a cell contains a list of views. In comparison to VHDL, acell isequivalent to anENTITY and aview is equivalent to anarchitecture . Just as most VHDLentities have only one architecture, most cells have only one view. Views are the basic buiblocks of your design and are equivalent to a schematic sheet. A view can have three typeobjects, ports, nets, and instances. A view is the implementation or contents of a single lehierarchy.

Examples:

• When you read a VHDL description into LeonardoSpectrum, your VHDL entitytranslates to a cell, and the VHDL architecture (contents) translates to a view. Bydefault, the cell is stored in an EDIF-style library calledwork (by default). You canchange the name of this library if you wish.

• When you load a technology library into LeonardoSpectrum, it becomes an EDIF-tylibrary in the design database, which contains all of the cells of that technology. Yodesign in the work library will reference this technology library as an external EDIFlibrary.

• LeonardoSpectrum creates an EDIF style library ofPRIMITIVES automatically. Thislibrary represents all primitive logic functions that LeonardoSpectrum may require wcompiling or elaborating HDL (VHDL and Verilog) descriptions.

• LeonardoSpectrum also automatically creates anOPERATORSlibrary. This librarycontains operator cells (adders, multipliers, muxes). When compiling HDL descriptiothese operators are generated when needed.

In summary, the following objects are typically contained within a view and are used torepresent netlists and hierarchies in a design:

• A view has ports, nets and instances.

• A port is a terminal of a view.

• An instance is a pointer to a view.

• A net is a connection between ports and/or port instances (pointer to the port of theunder an instance).


Introduction Accessing Design Data

h allthe

fy

is sets

The following code example is a small VHDL description that represents a primitiveANDfunction:

LeonardoSpectrum then creates a cell calledand2 in the default librarywork . The cell containsa view, calledcontents . The view contains three ports:a, b ando. The view also contains aninstance of a view in the LeonardoSpectrumPRIMITIVES library. This is an instance of aprimitive AND. The name of the instance is created by LeonardoSpectrum. The view alsocontains three nets:a, b, ando, connecting the instance to the ports of the view. All objectslibraries, cells, views, ports, nets and instances can contain attributes.

Accessing Design DataThe optional LeonardoSpectrum Design Browser allows you to graphically browse througin-memory libraries and the design hierarchy. If you have Level 3 capability and are usingLeonardoSpectrum interactive command line shell to write scripts, then you can use thefollowing guidelines to identify objects in the database.

To identify an object in the design database, LeonardoSpectrum uses a formalized designnaming convention. Any object in the database is accessible from a single root (the set oflibraries). The root is identified by the design name. (dot). A library is identified by the designname:

The general design name for a view is:

Wildcards and regular expressions are accepted and expanded in design names to identimultiple objects simultaneously.

LeonardoSpectrum also has the concept of a “present design”. This is a design name thatidentifies the top of your design hierarchy. When LeonardoSpectrum starts up, the defaultto the root (.). After you read in a design, the “present design” is set to the top level view a

entity and2 isport (a,b: bit; o:out bit);

end and2;architecture contents of and2 isbegin

o <= a AND b;end contents;

. library_name

.library_name.cell_name.view_name


Accessing Design Data Introduction

nynames.

described in the source file(s).Table 1-1is a list of commands that enable you to investigate aobject in the in-memory design database using absolute design names or relative design

Table 1-1. Commands that Generate Lists

Table 1-2shows explicit examples of useful commands the generate lists.

Table 1-2. Examples of Commands that Generate Lists

Command Description

present_design Displays the present design name.

present_design <design_name> Changes the present design to<design_name> .

list_design -ports List all ports in the present design.

list_design -nets Lists all nets in the present design.

list_design -instances Lists all instances in the present design.

list_design <design_name> Lists all objects contained in<design_name> .

list_attributes Lists all attributes in the present design.

list_attributes -port <port_name> Lists all attributes on the port<port_name> of the present design.

push_design <design_name> Changes the present design to<design_name> . This precompiled Tclprocedure is defined inexemplar.ini fileand allows you to change the presentdesign while returning to your startingpoint.

pop_design Returns you to the present design beforethe lastpush_design. This precompiledTcl procedure is defined inexemplar.inifile and allows you to change the presentdesign while returning to your startingpoint.

Command Description

list_design .work Lists all cells in the library calledwork .


Introduction Accessing Design Data

lences),

rts

The formalized naming convention can uniquely identify libraries, cells and views in a singname. However, since a view can contain three different types of objects (ports, nets, instathere may be a problem identifying these uniquely. For example, the name:

.l.c.v.x

does not identify an objectx in view v of cell c in library l as a port, net or instance. To workaround this problem, thelist_design command (and other commands that accept nets, poor instances) all have an option that you can use (-port , -net , or -instance ) to identify anobject type.

The result oflist_design is a (Tcl) list, which can easily be used in scripts. The followingexample script reports how many cells are in each library in the database:

After thedemo/mancala.vhd file, for example ($EXEMPLAR/LeoSpec/demo ), has been read andtheact2 library loaded, this script will produce the following output:

list_design -ports.work.and2.contents

Lists all ports on the viewcontents ofthe celland2 in thework library.

list_design .* Lists all cells in all libraries.

list_design -nets Lists all the nets in the present design(only valid if present design is a view).

list_design -instances x Lists the design name of the view underthe instan cex of the present design.

present_design .work.and2.contents Changes the present design to viewcontents of cell and2 in theworklibrary.

push_design inst_1 Changes the present design to the viewto which the instanceinst_1 is pointing.

pop_design Changes the present design back tobefore the previouspush_design call.

for each i [list_design .] {set the_length [llength [list_design $i]]puts “library $i contains $the_length cells”

}

library .PRIMITIVES contains 19 cellslibrary .work contains 2 cellslibrary .OPERATORS contain 6 cellslibrary .act2 contains 925 cells


Accessing Design Data Introduction

again:

ctive

The object separator is programmable; the default is. (dot). You can change the separator bysetting the Tcl variablelist_design_object_separator . For example, the following scriptprints the present design name, changes the object separator, and prints the design name

Produces the output:

LeonardoSpectrum notifies you with a message when it recognizes the setting of aLeonardoSpectrum built-in variable, rather than a normal Tcl variable.

You can use the following example commands to list commands and variables in the interacommand line shell:

puts “The present design is [present_design]”set list_design_object_separator /

puts “The present design is [present_design]”

The present design is .work.mancala_32.exemplarInfo: setting list_design_object_separator to /The present design is /work/mancala_32/exemplar

help (lists all commands)help present_design (lists options and information)help list* (lists all list commands)help -variables (lists all variables)help -var write* (lists information about writevariables)


m

eby

pair. In

e

y

ess.this

Chapter 2Attributes

An attribute is information that is attached to (owned by) an object in the LeonardoSpectruin-memory design database. An attribute has a name, a type, a value, and an owner. Anattribute’s value typically describes a characteristic about the design object. Many times thinformation is used to override a global constraint that is applied to the design as a wholesetting a Tcl variable.

The concept of an attribute in an HDL language is the same. The attribute is a name/valuethat is associated with, (“attached to”, “set on”, or “owned by”) a design object in the designVHDL, the attribute construct may be used to associated a design object with an attributvalue and in Verilog, a//exemplar attribute directive may be use. If these attributes aredeclared in the source files, the HDL attributes are converted to attributes in the in-memordatabase and may be translated as EDIF properties during an EDIF netlisting operation.

Setting attributes is used as a “fine tuning” control mechanism to guide the synthesis procThe syntax and methods for applying attributes to your in-memory design are described inchapter.

How to Set AttributesThis section provides examples of four ways to set attributes.

1. You can declare and set attributes in your VHDL source files

2. You can declare and set attributes in your Verilog source files

3. You can use the set_attribute and remove_attribute commands in the InteractiveCommand Line Shell to set and remove attributes on in-memory design objects

4. You can set attributes using a LeonardoSpectrum constraint file


How to Set Attributes Attributes

(1) Using the VHDL attribute construct

The following syntax can be used for the declaration of a VHDL attribute:

attribute <attribute_name> : <attribute_type> ;

The following syntax describes how to set an attribute on a VHDL component.

attribute <attribute_name> of <object_name> : component is<attribute_value>

Note: Set on component which is corresponding to view.attribute <attribute_name> of <object_name> : label is <attribute_value>

Note: Set on a label which is corresponding to an instance.

VHDL Example:

library exemplar ;use exemplar.exemplar. all ; -- Include the ’exemplar’ packageentity example is

port ( inp, clk : in std_logic;outp : out std_logic;inoutp : inout std_logic;

) ;attribute buffer_sig : string ;attribute buffer_sig of clk: signal is “CLOCK BUFFER”;end example;


Attributes How to Set Attributes

te

(2) Using a Verilog directive

Use the followingdirectivefor Verilog attributes.

//exemplar attribute <object_name> <attribute_name> <attribute_value>

Verilog Example:

//examplemodule expr (a, b, c, out1, out2);input [15:0] a, b, c;output [15:0] out1, out2;

assign out1 = a + b;assign out2 = b + c;

// exemplar attribute expr modgen_sel fastestendmodule.

In this example, the “fastest ” LeonardoSpectrum modgen + operator is used for theout1assignment.

(3)Using the Interactive Command Line Shell

Sometimes it is desirable to avoid setting attributes in the HDL source files and instead seattributes by sourcing a Tcl script or typing a command directly from the Level 3 InteractivCommand Line Shell. You can use theset_attribute command to add an attribute to anin-memory design object and theremove_attribute command to remove an attribute. Thelist_attributes command gives you visibility into the current attributes that are set on adesign object.

You can use the following Tclsyntax, for example, if you do not want to modify your Verilog orVHDL code:

set_attribute -<obj_type> <obj_name> -name <attribute_name> -value<attribute_value>

Interactive Command Line Shell Example:.

set_attribute -instance abc -name noopt -type boolean-value TRUE

remove_attribute -instance abc -name noopt

where: -type is [instance, net, port]


How to Set Attributes Attributes

(4) Using a LeonardoSpectrum Constraint File

You can use the following syntax in a constraint file (constraint_filename.ctr ) that youmay be creating from a standard text editor:

<constraint_name> <value> <port or signal_name>

Constraint File Syntax:.

buffer_sig clkbuf clk1Note: Connects signal clk1 to the input of the external clockbuffer ( clkbuf ).

buffer_sig clkint rstnNote: Connects signal rstn (reset signal) to input of internalclock buffer ( clkint ).


Attributes List of Pre-Defined Attributes

s toourplar

ut(7),

List of Pre-Defined AttributesThe following is a list of pre-defined LeonardoSpectrum attributes that can be set with anabbreviated syntax that is accepted by a LeonardoSpectrum constraint file. In addition, theVerilog, VHDL, and interactive command line shell syntax can be used as shown for someattributes.

array_pin_number (VHDL only)

This VHDL only attribute makes it easier to assign pin numbers to buses. The alternative iset a pin_number attribute on each bus net. The attribute declaration can be included in ycode along with many other Exemplar-specific attribute declarations by including the exempackage. For example:

library exemplar;use exemplar.exemplar.all;

VHDL Example:

entity sync_ram isport (data_in : in UNSIGNED(7 downto 0);

address : in UNSIGNED(15 downto 0);we : in std_logic;clk : in std_logic;data_out : in UNSIGNED(7 downto 0));

attribute array_pin_number of data_out:signal is(“H2”,”H4”,”E4”,”P1”,”C1”,”D5”,”C4”,”A8”);end sync_ram;

In the above example, the pin numbers are assigned left to right. H2 is assigned to data_oH4 is assigned to data_out(6), and so on.

arrival_timearrival_time <delay_value> <input_port_list>

Interactive Command Line Shell Syntax:

set_attribute -port inp(1) -name arrival_time -value 10

Constraint File Syntax:

arrival_time <value> <input port 1....input port n>

Specifies the latest arrival time (nanoseconds) of a signal at an input port. Specifies themaximum delay to the input port through external logic. This is a timing related attribute.


List of Pre-Defined Attributes Attributes

iveffset

t

Refer also torequired_timeattribute.

VHDL Syntax:

attribute arrival_time : real;attribute arrival_time of inputA:signal is 3 ns;

IMPORTANT NOTE : All input arrival times start at time zero and cannot be specified relatto a particular clock edge. You can adjust for a particular clock edge by adding the clock oto the arrival time.

auto_dissolve

Theauto_dissolve attribute allows you to dissolve an instance or view on a port. If you seauto_dissolve on a view, then all instantiations in the view are affected. If you setauto_dissolve on an instance, then only that instance is affected. The function of theauto_dissolve attribute is in contrast to the global functions of theasic_auto_dissolve_limit (ASIC 30) orauto_dissolve_limit (CPLD/FPGA 50)variables. This attribute can also be set globally by setting theauto_dissolve_limitvariable.



mand.

Apply Attribute Examples:

set_attribute -instance <view_name> -name auto_dissolve -value trueset_attribute -instance <instance_name> -name auto_dissolve -value true

Remove Attribute Examples:

remove_attribute -instance <view_name> -name auto_dissolveremove_attribute -instance <instance_name> -name auto_dissolve

HDL Notes: attribute name:auto_dissolve (case insensitive); attribute value:{true|false}

buffer_sigbuffer_sig <buffer_type> <signal_name>

Specifies signals to be buffered. This is a signal buffering command.


set_attribute -net <signal_name> -name buffer_sig -value <buffer_name>


buffer_sig clkbuf clk1

clock_cycleclock_cycle <clock period> <signal name>

Specifies the length (nanoseconds, real numbers) of the clock. This is a clock control com

Note: clock_cycle is one of the three basic clock commands. The other two are:clock_offset andpulse_width .

Note: For flip flops the trailing edge occurs at timeclock_offset + clock_cycle .



is a

ftton


set_attribute -port foo -name clock_cycle -value 30.0

VHDL Syntax:

attribute clock_cycle : real;attribute clock_cycle of in_clock:signal is 30.0;

clock_offsetclock_offset <time> <signal name>

Specifies the time (nanoseconds, real numbers) of the leading edge offset from zero. Thisclock control command.

Note: clock_offset is one of the three basic clock commands. The other two are:clock_cycle andpulse_width .

Note: For both flip flops and latches, the leading edge occurs at timeclock_offset . For flipflops the trailing edge occurs at timeclock_offset + clock_cycle . For latches, the trailingedge occurs at timeclock_offset + pulse_width .


set_attribute -port foo -name clock_offset -value 5.0

VHDL Syntax:

attribute clock_offset : real;attribute clock_offset of clock:signal is 5 ns;

dont_touchdont_touch <instance name> <true or false>

dont_touch is used to mark desired instances to prevent unmapping and optimization. Incontrast tonoopt, dont_touch prevents optimization of the lower levels of hierarchy and leainstances. This attribute is also available on the design browser. Move the right mouse buover an object in the design browser and popup a menu.

Note: Refer to the CAUTION note listed forauto_writecommand.


set_attribute -instance foo -name dont_touch -value TRUE



ign.

hake

ters

input_driveinput_drive <value> <input signal>

Specifies the sensitivity to loading of the gate driving an input to the design.

input_max_fanoutinput_max_fanout <load>

Specifies the maximum fanout load the synthesized circuit presents at design input.

input_max_loadinput_max_load <load>

Specifies the maximum load that the synthesized circuit may create on an input to the des

lut_max_fanout

lut_max_fanout <value integer>

LeonardoSpectrum attempts to maintain reasonable fanouts by replicating the driver whicresults in net splitting. If replication is not possible, then the signal is buffered. This may mthe wire slower by adding intrinsic delays. A Max Fanout window is on the AdvanceTechnology FlowTab.


set_attribute -net <net_name> -name lut_max_fanout -value <integer>

map_complex

This Altera-specific attribute enhances your ability to control the mapping of boundary registo either APEX I/O ATOMS or FLEX IOEs. You can first set the global variablealtera_map_complex_ios to TRUE, then turn off the mapping of specific ports by setting thisattribute toFALSE on those ports.

Related variables:altera_map_complex_ios

Related attributes:map_complex_reg_type



tersut

l

map_complex_reg_type

This Altera-specific attribute enhances your ability to control the mapping of boundary regisin APEX and APEX II technologies. For bidirectional ports, you can select whether the inpregister or the output register should be mapped to the I/O cell. You do this by setting thisattribute on the port and setting the value to either input or output.


set_attribute -port <port_name> -name map_complex_reg_type -valueinput|ouput

Related variables:altera_map_complex_ios

Related attributes:map_complex

modgen_selectmodgen_select <auto|fast|fastest|small|smallest>

Operators in the modgen library useauto|fast|fastest|small|smallest to define theoperation of a counter, adder, or multiplier, for example. Also see Commands.

no_buffno_buff <signal name> <true or false>

Specifies signals that are not buffered internally. Works for input ports only. This is a signabuffering command.

Note: Input pins withno_buff applied are not buffered.

Verilog:

//exemplar attribute <module_name> nobuff TRUE;

VHDL:

attribute no_buff : boolean;attribute no_buff of inport: signal is TRUE;

Interactive Command Line Shell:

set_attribute -port abcde -name no_buff -type boolean -value TRUE



net
Note: You can prevent LeonardoSpectrum from buffering or resolving DRC violations on aby setting theno_buff attribute:
set_attribute -net <net_name> -name no_buff -value TRUE

nooptnoopt <instance name> <true or false>

Specifies that an instance should not be optimized or changed. However, in contrast todont_touch, lower level hierarchy and leaf instances are not protected from optimization orchange. For example:

Verilog://exemplar attribute <module_name> noopt TRUE

VHDL:

attribute noopt : boolean;attribute noopt of <component_name> : component is TRUE;


set_attribute -instance abcde -name noopt -type boolean -value TRUE

Note: Refer to the CAUTION note listed forauto_writecommand.

nopad


set_attribute -port <port_name> -name nopad -value true

VHDL Syntax:

attribute nopad : booleanattribute nopad of <port_name>:signal is true

Verilog Syntax:

//exemplar attribute <port_name> nopad true

Note: Refer also to ORCA FPSC section in the ORCA chapter of the LeonardoSpectrumSynthesis and Technology Manual.



lated

output_fanoutoutput_fanout <load> <port>

Specifies the amount of external fanout loads on an output port of the design.

output_loadoutput_load <load> <port>

Specifies the number of external unit loads on an output port of the design. This is a load recommand.

padpad <IO pad type> <signal name>

Specifies I/O gates to be used for specific signals. This is a signal buffering command.


set_attribute -port <name> -name pad -value <pad_name>


pad HCLKBUF hclk

VHDL Syntax:

attribute PAD of <signal_name>: signal is <pad_name>

pin_numberpin_number <pin number> <port name>

Assigns a device pin number to a certain port.

Note: Pin location corresponds topin_number attribute.

Verilog Syntax:

//exemplar attribute clock pin_number 10;

VHDL Syntax:



heto

attribute pin_number : string;attribute pin_number of i : signal is “P10”;


set_attribute pin_number abcde “P10”;set_attribute -port <name> -name pin_number -value <pin_name>

preserve_driver

The attribute,preserve_driver is similar topreserve_signal . When you applypreserve_driver , LeonardoSpectrum preserves the specified signal and the driver in thedesign.

preserve_driver <signal name>

Specifies that both a signal and the signal name must survive optimization.Note: This is anattribute that is allowed in the constraint file.

Verilog Example:

//exemplar attribute <signal_name> preserve_driver TRUE

VHDL Example:

Any parallel logic, such as a parallel inverters (gates), are optimized to a single instance. Tattributepreserve_driver can be applied on the parallel signals to tell LeonardoSpectrummaintain the parallel structure. Refer to the following:

library ieee;use ieee_std_logic_1164.allentity test is port (a1 : in bit ;z1, z2 : out std_logic) ;attribute preserve_driver :boolean;end test ;architecture exemplar of test issignal nz1, nz2 :bit;attribute preserve_driver of nz1:signal is true ;attribute preserve_driver of nz2:signal is true ;beginnz1 <= not(a1);nz2 <= not(a1);z1 <= nz1;z2 <= nz2;end exemplar ;



s a

Interactive Command Line Shell Example:

set_attribute -instance abc -name preserve_driver -type boolean -valueTRUE

Constraint File Example:

<preserve_driver> <value> <signal_name>

preserve_signalpreserve_signal <signal name>

Specifies that both a signal and the signal name must survive optimization. This attribute ipreserve signal command. Refer also to the Timing Constraints chapter in theLeonardoSpectrum User’s Manual.

pulse_widthpulse_width <clock width>

Specifies the width (nanoseconds) of the clock pulse. This is a clock control command.

Note: pulse_width is one of the three basic clock commands. The other two are:clock_offset andclock_cycle .

Note: For latches, the trailing edge occurs at timeclock_offset + pulse_width .

VHDL Syntax:

attribute pulse_width : real;attribute pulse_width of clock:signal is 10 ns;

required_timerequired_time <signal> <value>


set_attribute outp -name required_time -value 25 -port


required_time <value> <output port 1...output port n>



utput

rtainrsus

VHDL Syntax:

attribute required_time : real;attribute required_time of out_port:signal is 10.0;

Specifies the latest time (nanoseconds, real numbers) a signal is allowed to arrive at an oport. This is a timing related command.

Refer also toarrival_timeattribute.

simple_register

The ASIC mapper supports the attributesimple_register on signals. This attribute specifiesthat only simple registers are mapped to the signal. With this attribute, you can prevent cesignals from being mapped to complex registers. For example, prevent mapping to registewith synch clear. A simple register is a register that has only data, enable, and asynchronoinputs.


n is

gine.plete

aret

Chapter 3Variables

Tcl SyntaxLeonardoSpectrum supports the Tcl language and Tcl variable assignments and evaluatioalso supported (set for setting variables,$var_name to evaluate a variable, andunset forunsetting variables).

The Tcl variables in this section have direct links into the LeonardoSpectrum synthesis enThese variables affect the behavior of the LeonardoSpectrum synthesis commands. A comlist of LeonardoSpectrum variables can be displayed using the following command):

help -v

For help on a specific variable, you following the-v option with the variable name. Forexample:

help -v hdl_array_name_style

After you enter this command, the following message is displayed in the transcript:

hdl_array_name_style = %s(%d) -- bit name style for array type objects

This variable is set to%s(%d) by default.

This variable defines the name style to use when VHDL or Verilog array objects (vectors)compiled (in theread or extract_best_passes command) into sets of bits. Using the defaulsetting, a VHDL arraymy_bus(0 to 3) creates four bits in your design, calledmy_bus(0) ,my_bus(1) , my_bus(2) , and my_bus(3) . If you change this variable to another value usingthe Tcl commandset :

set hdl_array_name_style %s%d

then the bus names do not contain the() parentheses for the next time youread orextract_best_passes a VHDL or Verilog file. In this example, the bits are calledmy_bus0 ,my_bus1 , my_bus2 , andmy_bus3 .


The Variable Editor Variables

aluele. In

es

. If ar.

The Variable EditorYou can invoke the Variable Editor from the menuTools > Variable Editor ... From this editoryou can scroll through all the LeonardoSpectrum-defined variables and view the current vand the value type. In a Level 2 mode, you use this tool to change the value of a Tcl variaba Level 3 mode, you can also use theset andunset Tcl commands in the Interactive CommandLine Shell to perform the same task.

List of VariablesThe following list briefly describes the pre-defined variables that are available for use withLeonardoSpectrum commands.

Note: Variables are applied globally to your design, while attributes are applied to databasobjects. Attributes take precedence over variables. Some variables may also be applied aattributes.

allow_black_box_modgens

Produce a black box instead of an error for modgens for which there is no implementationmodgen does not have an implementation, then a black box is produced instead of an erro

Default value:FALSE

alt_auto_fast_ioset alt_auto_fast_io is for Altera place and route.

Default value:FALSE

alt_auto_register_packing

set alt_auto_register_packing is for Altera place and route.

Default value:FALSE

altera_allow_cascade_fanout

Set for Altera FLEX 6/8/10 and APEX, APEX II and Excalibur.

Default value:TRUE


Variables List of Variables

o

en

Map to cascades with fanouts. Applies ifaltera_use_cascades is TRUE.

altera_cascade_chain_length

Set for Altera FLEX 6/8/10 and APEX 20K/20KE.

Chain length = 8 for FLEX 8 and FLEX 10; chain length = 10 for FLEX 6

Chain length =10 for APEX 20K/20KE.

altera_map_complex_ios

When you set this variable toTRUE, either by clickingMap IO Registers on the TechnologyFlowTab, or directly in the Interactive Command Line window, LeonardoSpectrum willseparate boundary registers from internal Lcells in the output netlist and allow theimplementation tools to map the boundary registers to the registers in the I/O primitives. Toverride the mapping on specific ports, you can set themap_complex attribute toFALSEon thoseports.

Default value:FALSE

Related attributes:map_complex

altera_use_cascades

Map logic toCASCADEs during LUT mapping for AAltera FLEX 6/8/10 and APEX, APEX II andExcalibur.

Default value:TRUE

Related commands:optimize

area_weight

Indication of how much effort LeonardoSpectrum should make to minimize design area whmapping a design; higher values indicate more effort.

Default value: -1.000000

Valid Values: Numbers between 0 and 1.0



List of Variables Variables

ent is

p

rl

auto_dissolve_limit

Theauto_dissolve_limit variable dissolves (flattens by default) blocks of hierarchy thatcontain counts of 50 or fewer gates. Blocks or modules are dissolved in a context sensitivmanner. If a module is instantiated two or more times in the same design and the gate cou50 or less, then the module instantiation is dissolved. You canset auto_dissolve_limit to 0to disable. Refer to theauto_dissolve attribute and also to theoptimize command.

Example: set auto_dissolve_limit 2000

Default value: 50 gates

balance_adders

Balance adders/subtractors cascaded in series.

Default value:TRUE

big_mux_percentage_for_lut

This is the upper cutoff of the percentage of unique data signals for creating a LUT node.

Default value:50


bubble_tristates

Choose (1) or (2) for setting your variable:

(1)set bubble_tristates true if tristatesare not in common levels. The tristates bubble uto the common top level. (2)set bubble_tristates true if tristatesare feeding an outputport. The tristates bubble up to the top primary output port. This occurs if tristates are eitheinor not in a common level.Note: During optimization tristates automatically bubble up to leveof hierarchy where all drivers become visible, or bubble up to top level if boundary.Note:bubble_tristates only bubbles boundary tristates up to a level where all drivers of a netbecome known.bubble_tristates does not bubble internal tristates and does not converttristates to muxes. The conversion of tristates to muxes is controlled by thetristate_map .

Note: If you use the bubble_tristates command[-noclean] option to set this variable, thecommand does some pre_optimization to avoid redundant ports.

Default value:TRUE



buffer_for_timing

Buffer for timing optimization.

Default value:TRUE

Related commands:optimize , optimize_timing

check_complex_ios

Use Design Rules Checker for complex ios for Actel (Act3) technology.

Default value:TRUE


comm_socket

The<address:port> for the external tool that is connected to LeonardoSpectrum.

Default value: not set

complex_ios

Map generic logic to complex I/O cells.

Default value:TRUE


constraints_save_only_multicycle

Save multicycle constraints only, or save all advanced constraints.

Default value:TRUE

critical_path_clustering

Cluster critical path for Virtex and APEX.

Default value:FALSE



critical_path_restructuring

Do critical path restructuring in the optimize_timing command.

Default value:TRUE

cross_probe_tool_name

The name of the external tool that is connected to LeonardoSpectrum.


default_bdbuf

This is default for bidirectional buffer.


default_input_arrival

Default arrival time at all input ports.

Default value:0.000000

default_input_buffer

This is a default input buffer.


default_output_buffer

This is a default output buffer.


default_output_required

Default required time at all output ports.

Default value:1073741824.000000



hen

default_register_arrival

Default arrival time at all registers.


default_register_required

Default required time at all registers.

Default value:1073741824.000000

default_tribuf

Default tristate buffer.


delay_break_loops

Break combinational loops statically for timing analysis.

Default value:FALSE

Related commands:optimize , optimize_timing , report_delay

delay_weight

Indication of how much effort LeonardoSpectrum should make to minimize design delay wmapping a design; higher values indicate more effort.

Default value:-1.000000

Valid Values:0 to 1.0 , inclusive


dont_lock_lcells

OBSOLETE: Useflex_lock_lcells or max_lock_lcells instead.

Default value:FALSE




drc_const_nets

Perform design rule checking (drc) resolving on power and ground nets.

Default value:FALSE

edif_array_range_extraction_style

Format of arrays in EDIF (read/write) to identify range information.

Default value:%s[%d:%d]

Related commands:read , write , auto_read

edif_eqn_and

Symbol to representANDin EDIF equations.

Default value: *

Related commands:write , set_altera_eqn

edif_eqn_not

Symbol to representNOTin EDIF equations.

Default value: !


edif_eqn_not_is_prefix

Symbol to representNOTin EDIF equations is prefixed

Default value:FALSE




edif_eqn_or

Symbol to representORin EDIF equations

Default value:+


edif_function_property

Attribute name to read or write functions on lookup-table instances in EDIF.

Default value:EQN (lut_function) .

Related commands:read , write , auto_read , auto_write , set_altera_eqn

edif_write_arrays

Allows writing arrays (buses) in EDIF output.

Default value:TRUE

Related commands:auto_write , write

edif_write_internal_properties

Write out all properties in EDIF, including internal ones.

Default value:FALSE

Related commands:auto_write , write

edifin_ground_net_names

Specify that net(s) with given name(s) are ground nets.


Related commands:read

edifin_ground_port_names

Specify that port(s) with given name(s) are ground ports.




Related commands:read , auto_read

edifin_ignore_port_names

Specify that port(s) with given name(s) are ignore port(s).



edifin_power_net_names

Specify that net(s) with given name(s) are power nets.



edifin_power_port_names

Specify that port(s) with given name(s) are power ports.


Related commands:read , auto_read

edifout_ground_net_name

Special name for ground nets whenedifout_power_ground_style_is_net is TRUE

Default value:GND

Related commands:write

edifout_no_prims_in_noopt

Do not write primitives innoopts .

Default value:FALSE




edifout_power_ground_style_is_net

Writes out power and ground as undriven nets with special name.

Default value:FALSE


edifout_power_net_name

Special name for power nets whenedifout_power_ground_style_is_ne t is TRUE.

Default value:VCC


edifout_write_noopted_contents

Write contents for noopted views.

Default value:TRUE


Note: Refer toauto_write command for information on using this variable after running thedecompose_luts command.

enable_dff_map_optimize

Infer clock-enables from random logic.

Default value:FALSE


encoding

Specify default enumeration type encoding style.

Default value:auto

Valid Values:binary , onehot , twohot , gray , random , auto

Related commands:apply_rename_rules , read



exclude_gates

Specify gates to be excluded from target technology library.


Related commands:load_library

extract_cin_cout

Enable automatic detection of carry-in/carry-out.

Default value:TRUE

Related commands:pre_optimize

extract_counter

Enable automatic extraction of counters from generic logic.

Default value:TRUE


extract_cse

Extract common sub-expressions from XOR gates.

Default value:TRUE


extract_decoder

Enable automatic extraction of decoders from generic logic.

Default value:TRUE


extract_ram

Enable automatic extraction of RAMs from generic logic.



Default value:TRUE


extract_reduction_ops

Enable automatic detection of reduction operators.

Default value:TRUE


extract_rom

Enable automatic extraction of ROMs from generic logic.

Default value:TRUE


flex_auto_implement_in_eab

Set for Altera FLEX place and route.

Default value:FALSE

flex_lock_lcells

Lock LCELLS for Altera FLEX technologies.

Default value:TRUE

force_user_load_values

Use the user values for max capacitance and fanout loads, ignore library values.

Default value:FALSE

Related commands:balance_loads , optimize



fsm_do_collapse

Collapse the next state logic before optimization and mapping.

Default value:FALSE

fsm_flow

By specifying the FSM flow we take:

full_case

Interpret Verilog case statements as fully specified.

Default value:FALSE



generate_timespec_from_inputs

Generate timespec from input pins to registers or output pins.

best_optd optimized/mapped/unmapped network with bestencoding

best_orig original primary network with best encoding

bind_early optimized/mapped/noopted network with bestencoding

bind_late undefined currently

onehot_optd optimized/mapped onehot encode network (fordebug)

onehot_orig original primary network with onehot encoding

binary_optd optimized/mapped binary encoded network (fordebug)

binary_orig original primary network with binary encoding

noopt extract only dont optimize



s

Default value:FALSE

Related commands:getlist

hdl_array_name_style

Bit name style for array type objects.

Default value:%s(%d)

Related commands:extract_best_passes , read

hdl_array_separator_style

Dimension separator in bit name style for multi-dimensional array type objects.

Default value: ) (


hdl_input_location

Specifies directories to be searched during a read operation or Verilog ‘include compiledirective.

set hdl_input_location {“E:/my_packages” “C:/common_files”}READ my_pkg.vhd file1.vhd src/file2.vhd

During the read operation above, LeonardoSpectrum first searches for the filemy_pkg.vhdstarting with the current working directory (the directory from which LeonardoSpectrum wainvoked). The directory at pathnameE:/my_package is searched next, then the directoryC:/common_files . Finally, the directory$EXEMPLAR/data is searched. As soon as the file isfound, the file is loaded and a search for the next file begins.

hdl_integer_name_style

Bit name style for integer type objects (index 0 is LSB).





ut

that

hdl_record_name_style

Bit name style for record type objects.

Default value:%s_%s


hdl_write_inv_as_cell

Write technologyINV cells instead of assignment statements.

Default value:TRUE


input2output

Constrain paths between input ports and output ports.

Default:1073741824.000000

Example:set input2output 10

input2register

Constraint paths between input ports and register.Note: Use input2register to constrainsub-block boundary logic to one-half of the clock period (as defined by register2registervariable).

Default:1073741824.000000

Example:set input2register 10

insert_bufs_for_internal_clock

This variable directs LeonardoSpectrum to automatically insert global buffers on high fanointernal clock nets in Virtex designs. Primary clock nets are given the highest priority, theninternal clock nets are buffered if there are enough global buffers left over.

Default: TRUE

Note: You can override this directive on a specific net by setting the NOBUFF attribute onnet. For example:



nets

set_attribute -net internal_clk2 -name no_buff -value TRUE

If there are not enough global buffers, you can use the secondary (low skew) lines for clockand clock enable lines. See the explanation of the variablevirtex_apply_maxskew.

inversion_prefix

Prefix for inverted nets.

Default value:NOT

keep_flattened_views

Keep flattened views even if the views are no longer referenced.

Default value:FALSE


lgen_array_name_style

Naming style for array type objects in Lgen library cells.


Related commands: load_library

list_design_object_separator

Separator string used to find objects in a design name (library, cell, view, etc).

Default value:.

Related commands:list_design

load_library_file_extension

Technology library filename extension.

Default value: syn




blehen

out

lpm_remove_unused_ports

Remove unused ports from instantiated modules when reading VHDL or Verilog.

Default:TRUE

lut_buffering

Insert buffers (LUTs) on high fanout nets for better routeability.

Default value:FALSE


lut_cell_name

Prefix for LUT cells created by LUT decomposition.

Default value:lut_cell

Related commands:decompose_luts

lut_max_fanout

Specify net fanout for LUT technologies. LeonardoSpectrum attempts to maintain reasonafanouts by replicating the driver which results in net splitting. If replication is not possible, tthe signal is buffered. This may make the wire slower by adding intrinsic delays. A Max Fanwindow is on the Advanced Technology FlowTab. Refer also to thelut_max_fanout attribute.

Default value:0

set lut_max_fanout <integer>

map_fanin_limit

If limit is not 0 then specify upper boundary for fanin to a function.

Default value:4

map_sync_reg

Map to synchronize S/R registers.



Default value:TRUE

max_cap_load

Override defaultmax_cap_load if specified in the library. Refer to the technology library forvalues.


Example:set max_cap_load 4

Related commands:balance_loads , optimize , optimize_timing

max_fanin

Define upper bound for number of fanins to a function (0 is no limit).

Default value:0


max_fanout_load

Override defaultmax_fanout_load if specified in the library. Refer to the technology libraryfor values.


Example:set max_fanout_load 16


max_lock_lcells

Lock LCELLS for Altera MAX technologies.

Default value:FALSE

max_pt

Define maximum number of product terms in a function (0 is no limit).

Default value:0



r


max_transition

Override defaultmax_transition if specified in the library. Refer to the technology library fovalues.


Example:set max_transition 1.2


maxarea

Maximum area allowed in one design.

Default value:1073741824.000000

Related commands: optimize , optimize_timing

maxdly

Maximum delay allowed in one design.

Default value:1073741824.000000

Related commands:optimize -delay , optimize_timing

maxplusii_exec_path

Defines the pathname for the location of the Altera MAX+PLUS II Place and Routeexecutables.

Default value: (undefined)

mem_minimum_size

Minimum memory size for mapping to lpm_rom for Altera FLEX 10.

Default value:256



By default the minimum size of the ROMs detected in FLEX 10 is 256. Set this variable todetect ROMs smaller in size:

set mem_minimum_size 64

set mem_minimum_size 0 (Detect ROMs of all sizes.)

modgen_select

Default mode for modgen resolving.

Default value:auto

Valid Values:auto|smallest|small|fast|fastest

move_files_on_cwd_change

Move list and session file on new current working directory (cwd) when changing cwd.

Default:FALSE

multi_driver_drc_resolving

Perform DRC resolving on multidriver net.

Default value:TRUE

names_collision_extension

Name extension to be used when names collide in renaming process.

Default:_rename

no_boundary_optimization

Disable-boundary optimize which is executed during optimization. Skip boundaryoptimization.

Default value:FALSE

Related command:optimize



no_sequential_cell_replication

Do not replicate sequential cell.

Default value: FALSE

nowire_table

Do not use a wire table during delay calculations.

Default value:FALSE


old_style_session_file

Create old 4.x style history file.

Default value:FALSE

operating_condition

Specify operating conditions for timing computations.

Default: not set

optimize_clock_enable

Enable automatic optimization of clock enable.

Default value:FALSE

optimize_clock_enable_support_limit

Fanin limit for optimization of clock enable.

Default value:40

optimize_cpu_limit

CPU limit for theoptimize command, in seconds (0 is no limit).



at

Default value: 0 (no limit)

optimize_drc_resolving

Enables DRC (design rule checking) resolving during optimization by default.

Default value:TRUE

Note: You must run thebalance_loads command at the end of your design run to ensure ththe final design meets the design rule checking (DRC).

Note: DRC resolving may require more runtime. However, DRC resolving can improve theinitial timing estimation, and can prevent heavily loaded nets.

optimize_timing_cpu_limit

CPU limit for optimize_timing command, in seconds (0 is no limit).

Default value: 0 (no limit)

package

Indicate a specific package type for the output design.



parallel_case

Interpret VerilogCASEstatements as parallel.

Default value:FALSE


part

Indicate a specific part for the output design.





ctors.

prepend_dff_inst_name

Prepend the string to a dff name driving user defined net.

Default value:reg_


prepend_io_inst_name

Prepend the string to IO buffer instance names.

Default value:IO

prepend_latch_inst_name

Prepend the string to a latch name driving user defined net.

Default value:lat_


prepend_tri_inst_name

Prepend the string to a tri name driving user defined net.

Default value:tri_


preserve_dangling_net

Create ports to unconnected nets when readingXNF file.

Default value:FALSE

process

Use specified process or speed-grade from target technology to compute delay derating faRefer to the technology library for values.

Default value: not set (2)



tera.

.

r it.

Example:set process typical


process_pragma

Process VHDL and Verilog pragmas.

Default value:TRUE

propagate_clock_delay

If FALSE, then use ideal clock. IfTRUEthen use clock delay in delay calculation.

Default value:FALSE

pterm_max_fanin

If not 0 then specify upper boundary for fanin to a function for pterm based technology - Al

Default value:0

quartus_exec_path

Defines the pathname for the location of the Altera Quartus Place and Route executables

Default value: (undefined)

quick_enable_dff_map_optimize

Quickly infer clock enables from random logic.

Default value:FALSE

ram_inference_blackbox

Leave an inferred RAM as a black box, if there is no technology-specific implementation fo

Default value:FALSE



of

ble.

register2output

Constraint paths between registers and output ports.Note: set theregister2output andinput2register variables to one-half of the clock period to ensure that the boundary logicsubblocksmeets timing when combined in a top-level design.

Default value:1073741824.000000

Example:set register2output 10

register2register

Constraint paths between registers.

Default value:1073741824.0000000

Example:set register2register 20

replicate_logic_for_drc

Enable the use of logic replication for design rule checker (drc).

Default value:TRUE

replicate_logic_for_timing

Replicate logic for timing optimization.

Default value:TRUE

Related commands:optimize , optimize_timing

report_area_format_style

Style (precision) of reporting area numbers.

Default value:%6.0f

Related commands:report_area

report_delay_analysis_mode

Delay analysis mode. Note: Perform timing optimization and timing analysis with this varia



the

.

Default value:maximum

Valid Values:maximum, minimum , both

Example: set report_delay_analysis_mode minimum

Note: You can perform timing optimization and timing analysis when the variable is set todefault minimum.

Example:set report_delay_analysis_mode maximum

Note: You can perform worst-case hold time analysis when the variable is set to maximum

Related commands:report_delay

report_delay_arrival_threshold

Arrival time threshold for delay report, in nanoseconds.



report_delay_detail

Amount of detail in delay report.

Default value: full

Valid Values:full , short


report_delay_format_style

Style (precision) of reporting delay numbers.

Default value:%4.2f


report_delay_slack_threshold

Slack threshold for delay report, in nanoseconds.





resolve_mux_stat

Decision table for modgen resolving vs default resolving of muxes.


resource_sharing

Enable resource sharing. Allows you to reduce number of certain devices.

Default value:TRUE

resource_sharing_through_pattern

Enables resource sharing through pattern matching.

Default value:TRUE


restructure_for_timing

Restructure combinational logic for timing optimization.

Default value:TRUE

sdf_hier_separator

Separator for hierarchical names in the SDF writer.

Default value:/


sdf_hierarchical_names

Treat all SDF names with divider character as hierarchical.



Default value:TRUE


sdf_names_style

Rename rules for SDF writer

Default value:vhdl

Valid Values: verilog , vhdl , none


sdf_read_suppress_warnings

Suppress cell names mismatch warnings.

Default value:TRUE

sdf_type

Define delay derating for SDF reading and writing.

Default value:maximum

Valid Values:minimum , typical , maximum


sdf_write_flat_netlist

Write SDF for a flat netlist. This variable constrains the SDF writer when set toTRUE.

Default value:FALSE

Example: The SDF writer is controlled by thesdf_write_flat_netlist Tcl variable. Set thisvariable toTRUE. An example set ofLevel 3 commands may be:

set sdf_write_flat_netlist TRUE

ungroup -all /*need to flatten the netlist*/

write design.vhd /*write out flat VHDL or Verilog*/

write design.sdf /*write out SDF*/



).

ation.

e

state_table_threshold

Do not print a state assignment table for enumerated types with more values than this (40

Default value: 40

sweep_in_fe

Remove unused logic, propagate constants, merge common logic, etc. during pre-optimiz

Default value:TRUE

sweep_unused_user_cells

Remove unused instantiated cells.

Default value:TRUE

temp

Indicate temperature (in celsius, centigrade) to compute delay derating factors. Refer to thtechnology library for values.


Example:set temp 80

timing_characterize_print_constraints

For each module, write a plain text file that contains the propagated module constraints.

timing_characterize_print_constraints TRUE

When this variable is set toTRUE, LeonardoSpectrum writes a plain text constraint file to theworking directory for each module in the design. The file records theARRIVAL_TIME andREQUIRED_TIMEconstraints that have been propagated to each port on the module.

transformations

Allow transforming set/reset on dffs and latches to match target technology.

Default value:TRUE



tristate_map

Allow the conversion of internal tri-states to combinational logic to match the targettechnology.

Note: The conversion of tristates to muxes is controlled by this variable.

Refer also tobubble_tristates .

Default value:FALSE

ungroup_hier_separator

Separator for hierarchical names.

Default value:TRUE

Related commands:ungroup

use_assign_for_vcc_gnd

Use assign statement or supply [01] nets for power ground nets.

Default value:TRUE

use_dffenable

Infer clock-enable from HDLs. When set toTRUELeonardoSpectrum maps to any existingflip-flops with clock enable. When set toFALSE, LeonardoSpectrum is prevented from doingthis automatic optimization.

Default value:TRUE


user_verbose

Use this boolean global variable to print out optimization messages.

Default value:FALSE



verilog_max_line_length

Define maximum line length when writing Verilog.

Default value:80

verilog_parameter_to_attribute

Move the parameter values to the view (useful for LPM instantiation).

Default value:TRUE


verilog_read_ignore_input_assign_errors

Ignore assignment of input to bidir.

Default value:FALSE

verilog_write_arrays

Allows writing arrays (buses) in Verilog output.

Default value:TRUE

Related commands:write , auto_write

verilog_write_pwr_gnd_cells

Write technology power/ground cells instead of assign/supply statements.

Default value:TRUE

vhdl_87

Use VHDL'87 style syntax/semantics instead of VHDL'93 for reading VHDL.

Default value:FALSE




vhdl_generic_to_attribute

Move the generic values to the view (useful for LPM instantiation).

Default value:TRUE


vhdl_identifiers_lower_case

Convert VHDL identifiers to lower case (pre-v2000.1a2 behavior).

Default value:FALSE

vhdl_write_87

Use VHDL'87 style syntax/semantics instead of VHDL'93 for writing VHDL.

Default value:FALSE


vhdl_write_arrays

Allows writing arrays (buses) in VHDL output.

Default value:TRUE

Related commands:write , auto_write

vhdl_write_bit

type for bit used in VHDL writer.

Default value:std_logic

Valid Values: any user-defined string


vhdl_write_bit_vector

This is the type for bit vectors used in VHDL writer.



are

Default value:std_logic_vector


vhdl_write_component_package

Write components in package instead of in line with architecture.

Default:TRUE

vhdl_write_component_package_name

Name of package containing component for VHDL writing.

Default: components

vhdl_write_configuration

Write VHDL configuration.

Default:TRUE

vhdl_write_inst_uppercase

Write VHDL instance names in uppercase.

Default:FALSE

vhdl_write_port_uppercase

Write VHDL port names in uppercase.

Default: FALSE

vhdl_write_pwr_gnd_cells

When this variable is set to default TRUE, the power and ground cells in the logic networkwritten in the netlist. When the variablevhdl_write_pwr_gnd_cells is set toFALSE,then the power and ground cells are written as VHDL assignment statements instead.

set vhdl_write_pwr_gnd_cells TRUE

Default:TRUE



netses onlt the

d if

r

vhdl_write_signal_uppercase

Write VHDL signal names in uppercase.

Default:FALSE

vhdl_write_use_packages

Define which packages to include for each entity.

Default value: libraryIEEE, EXEMPLAR; use IEEE.STD_LOGIC_1164.all; useEXEMPLAR.EXEMPLAR_1164.all;

viewlogic_vhdl

Read ViewLogic's pack1076 built-in package as standard.

Default value:FALSE


virtex_apply_maxskew

Forces the usage of secondary (low skew) lines in Virtex. If the value is not 0, thanLeonardoSpectrum applies the value as the maxskew for high fanout nets.

set virtex_apply_maxskew 5

Default:0

Secondary (low skew) lines will be used if there are not enough global buffers for the clockand LeonardoSpectrum advises you to use the low skew lines. You can also use these linhigh fanout clock enable lines. The appropriate skew value is device dependent, so consuVirtex data book before you set the value.

Note: If you set a very low skew value, then Place & Route will try to achieve that value anit cannot meet the constraint, P&R will error out.

voltage

Specify voltage (in V) to compute delay derating factors. Refer to the technology library fovalues.




value

Example:set voltage 5.0


wire_load_library

Name of library the present design is mapped to.

DefaultNIL (char)

wire_load_mode

Mode to compute wire loads:top (default),segmented (enclosed).

Default: top

wire_table

Use named wire table from target library for delay calculations.Note: Set the wire load modelto reflect the gate count of the sub-block. The wire load model determines the capacitanceapplied to all nets.


Example:set wire_table cg61_50000area

Example:set wire_table worst


wire_tree

Specify interconnect wire tree model to use for delay calculations.Default value: not set

Valid Values: best , balanced , worst


write_lut_binding

Print LUT binding (HMAP/FMAP) information, if available, inEDIF files.

Default value:TRUE




write_xrf_file

Write cross reference file.

Default value:TRUE

x_probe

Enable cross probe for schematic viewer.

Default value:TRUE

x_probe_autocopy

During optimization, auto save a copy of RTL view forx_probe .

Default value: TRUE

xdb_write_version

For LeonardoSpectrumv1998.x to readxdb written by thev1999.1 version, set this variable to1998.x while in v1999.1 before writing.


Note: This variable is available only inv1999.x . This variable allows you to write a project inv1999.x and then read the project inv1998.x .

set xdb_write_version v1998.x

xor_decomp

Do XOR decomposition for Altera MAX technologies.

Default value:TRUE



)

Chapter 4Shell-Level Commands

Invoking the GUI using the leonardoCommand

When you invoke LeonardoSpectrum with theleonardocommand, the tool comes up with theGraphical User Interface (GUI). The usage methods are as follows:

1. When invoking from a Unix shell, type the following:

% $EXEMPLAR/bin/leonardo

2. When invoking from a Windows Command Prompt, type the following:

C:\> leonardo

(Assuming that the PATH variable is set to Exemplar tree ../bin/win32/leonardo.exe

3. Double-click on a Windows Shortcut with a Target set to the following path:

C:\ ...<Exemplar tree>.../bin/win32/leonardo.exe


Invoking the GUI using the leonardo Command Shell-Level Commands

fter

st

cally.

leonardoA shell-level command that invokes LeonardoSpectrum.

Syntaxleonardo

[ -scriptfile <file>][ -product ls1 | ls2 | ls3][ -ls1vendor <vendor>][ -mti ][ -no_mgls ][ -exemplar ][ -no_exemplar ][ -pre_license_check ][ -regclear ][ -reginit ][ -force ][ -help ][ -dumpdevicefile ][ -convertdevicefile ][-<global_variable>=<value>]

Options

• -scriptfile <file>

The switch can be specified as either -script or -file. The specified file will be sourced aLeonardoSpectrum is invoked

• -product ls1 | ls2 | ls3

Bypasses the product-level query message and directly sets the product level. If ls1 isspecified, then the-ls1vendor<vendor> option must also be specified. Otherwise, the firvendor listed in the devices.ini file is selected.

• -ls1vendor <vendor>

Sets the -product ls1option to the appropriate vendor. If specified, this option automatiset -product=ls1. If not specified, the first vendor listed in the devices.ini file is selected

• -mti

Check licenses using the Model Technology [modeltechd] licensing daemon. DefaultTRUE.

• -no_mgls

Do not check licenses using the Mentor Graphics [mgls] licensing daemon. DefaultFALSE.

• -exemplar

Check licenses using the Exemplar [exempard] licensing daemon. DefaultTRUE.

• -no_exemplar

Do not check licenses using the Exemplar [exempard] licensing daemon. DefaultFALSE.


Shell-Level Commands Invoking the GUI using the leonardo Command

ust

and

s up

fault

• -pre_license_check

Check for license availability before running the License Query Dialog. DefaultFALSE.

• -regclear

Clear out the registry. DefaultFALSE. Typically used during an uninstall procedure.

• -reginit

Initialize the registry. DefaultFALSE. Returns the tool to the same state as though it was jinstalled.

• -force

Force -regclear and -reginit, do not ask questions - act in silent mode. DefaultFALSE.

• -help

Bring up the help dialog box.

• -dumpdevicefile

Save the current device settings to an ini file.

• -convertdevicefile

Convert an old format device.ini file to the new (v2000.1) format.

• -<global_variable>=<value>

Set any LeonardoSpectrum <global variable> to <value>.

Description

This command invokes LeonardoSpectrum from a Unix Shell command line or DOS commprompt. The option switches may also be specified after the leaf nameleonardo.exein theTarget pathname on a Windows Shortcut.

Examples

The following command line bypasses the product-level query message and directly bringthe LeonardoSpectrum Level 2 GUI.

(Windows Shortcut Target:) C:\Exemplar\LeoSpec\LS2001_1d\bin\win32\leonardo.exe -productls2

The following command line clears and initializes the LeonardoSpectrum product to its desettings, invokes the level two GUI, and sources the Tcl file leo_do.tcl.

....leonardo.exe -force -product ls2 -script C:/project/leo_do.tcl


Batch Mode Operations using the spectrum Command Shell-Level Commands

s

e or

uce

ctice

Batch Mode Operations using thespectrum Command

Thespectrumcommand is LeonardoSpectrum’s invocation for batch mode operations. Thecommand line syntax is:

spectrum <input file> <output file> <-target technology> [more options]

spectrum -file <my_script_file> (Run your Tcl script file in batch mode)

spectrum -product ls2|ls1 -file <my_script_file>

Options and Switches

The following is an alphabetical list of options and switches for thespectrum command. Eachentry in the list is followed by a brief explanation. The defaults in the list are identified.

-architecture=<string>

This option, when used with the-entity=<string> option, defines the top level of hierarchyin the input VHDL design. This is a VHDL only option. By default, LeonardoSpectrum pickup the last architecture in the design to be synthesized if this option is not specified. The<string> is case sensitive and must be specified in lower case only. In VHDL, a mixed casall upper case architecture name cannot be used.

-area | -delay | -auto (default)

Directs LeonardoSpectrum to optimize the circuit to minimize area, minimize delay, or prodthe best combination of both. The-auto option (the default) instructs LeonardoSpectrum torun both area and delay optimization and automatically retain the best result on ablock-by-block basis.

-batchhelp

Type this option to display a list of all batch mode options. Type:

$EXEMPLAR\leospec\spectrum -batchhelp

Note

Pathnames that Contain SpacesBecause pathnames on a PC platform may contain spaces, it is a good prato enclose the pathname in double quotes.


Shell-Level Commands Batch Mode Operations using the spectrum Command

e for

nd

ordded

tion

at thehouldtrol

ns at

-bus_name_style=<string>

This option allows you to customize bus names in the EDIF output. This is the naming stylvector ports and nets. For example: default%s(%d) or a(0) , simple%s%dor a0, or a_0 . Forexample:

-bus_name_style %s%d|simple %s%d|old_galileo %s_%d

-chip | -macro

The-chip option directs LeonardoSpectrum to add I/O buffers or preserve I/O buffers arouthe periphery of the design. The-chip option is mutually exclusive with the-macro option.-chip is the default when neither-chip nor -macro is specified.

The-macro option specifies that the input design represents a part of a complete design, fexample a user level of hierarchy. When the macro mode is specified, I/O buffers are not ato the design. The-macro option is mutually exclusive with the-chip option.

-command_file=<list> | [{<file_name>}]...[{<file_name>}]

Specifies options from a separate file, instead of from the command line. Using this optioncauses LeonardoSpectrum to read additional command line options from this file. This opcan be used multiple times or can accept a list of files as a parameter.

-control=<string>-nocontrol

Specifies design specific constraints to LeonardoSpectrum. For example, the arrival timeinputs, the required times at the outputs, the load at the output ports, and the pads which sbe connected to a signal are a few of the design constraints that may be specified in a confile. By default, LeonardoSpectrum looks for<input_filename>.ctr as the control file. Thisoption can be used to specify a different file, or use the-nocontrol option to override the useof the default control file.

-crit_path_analysis_mode=<string> (maximum | minimum | both)

Directs LeonardoSpectrum to analyze and report setup violations (maximum) or holdviolations (minimum ) or both. The default ismaximum.

In themaximum delay analysis mode, worst case (maximum) arrival times and delaysthrough all the gates are used, and timing violations at the outputs and setup violatiothe register inputs are reported.

In theminimum delay analysis mode, best case (minimum ) arrival times and delaysthrough all the gates are used. Hold violations at the register inputs are reported.



s

esd

by

ed.

ritical.

or

nd

n isthe

-crit_path_arrival=<float>

Specifies a threshold for the arrival time (ns). Only paths with arrival times greater than thinumber are reported.

-crit_path_detail=short|full

Controls the level of detail in the critical path report. A critical path report with full detail giva point-to-point report of the entire path. A short report gives only the start point and the enpoint of a path. The default isfull .

-crit_path_from=<list>-crit_path_to=<list>

These are filters that direct LeonardoSpectrum to report critical paths starting or ending atspecific points (instances, nets, ports). Any number of start or end points can be specifiedproviding a list of start or end points as parameters to these options or by repeating theseoptions. When-crit_path_from is used, only critical paths starting at these start points arreported. When-crit_path_to is used, only critical paths ending at these points are reporte

-crit_path_longest

This option directs LeonardoSpectrum to show the longest path first rather than the most cpath. The paths are sorted by arrival time, with latest arrival time first, rather than by slack

-crit_path_no_int_terminals

This option filters out paths that terminate internally (paths that terminate at register inputsblack boxes) and reports paths terminating in primary outputs only.

-crit_path_no_io_terminals

This option filters out paths that terminate in primary outputs. Only paths that terminate atinputs of registers or black boxes are reported.

-crit_path_report_input_pins

Reports input pins of gates in the critical path report. By default, this option is turned off, aonly output pins are reported.

-crit_path_report_nets

Reports nets in the critical path report. By default, this option is turned off. When this optioturned on, the number of fanouts of the net are also reported in the last column, instead ofload.



d

anceof

se

vel)ell

lfor

-crit_path_rpt=<string>-nocrit_path_rpt

Specifies the critical path report file. By default, this is<output_filename>.rpt . The-nocrit_path_rpt option prevents the critical path report from being created.

-crit_path_slack=<float>

Specifies the slack threshold. Paths with slack less than the slack threshold are considerecritical. The default slack threshold is0.0 , so all paths with negative slack are critical bydefault.

-crit_paths_thru=<list>

This is a filter that reports critical paths through a particular instance, net, port, or port inst(pin). Any number of points can be specified by repeating this option or by specifying a listpoints. When points are specified with this option, only critical paths that pass through thepoints are reported.

-crit_paths_not_thru=<list>

This is a filter that reports only critical paths that do not pass through the specified points.

-design=<string>

When reading an EDIF netlist, LeonardoSpectrum assumes by default that the root (top lecell of the design has the same name as the input file. This option allows a different root cname to be specified.

-dont_lock_lcells | -lock_lcells (Obsolete)

These options are obsolete. Use the -flex_lock_lcells or -max_lock_lcells optioninstead.

-edif_file=<string>

An EDIF netlist can be written out as a second output netlist with this option. This is usefuwhen a VHDL or Verilog simulation netlist is produced and an EDIF netlist is also neededschematic viewing.

-edif_adl_flavor

Write out EDIF with legal adl naming.



-edif_timing_file=<string>

Write out EDIF file for timing analysis.

-edifin_ground_net_names=<list>

Specify that net(s) with given name(s) are ground nets.

-edifin_ground_port_names=<list>

Specify that port(s) with given name(s) are ground ports.

-edifin_ignore_port_names=<list>

Specify that port(s) with given name(s) ignore ports.

-edifin_power_net_names=<list>

Specify that net(s) with given name(s) are power nets.

-edifin_power_port_names=<list>

Specify that port(s) with given name(s) are power ports.

-edifout_ground_net_name=<string>

Special name for ground nets when-edifout_power_ground_style_is_net is TRUE,default GND.

-edifout_power_ground_style_is_net

Write out power and ground as undriven nets with special names.

-edifout_power_net_name=<string>

Special name for power nets when-edifout_power_ground_style_is_net is TRUE, defaultVCC.

-effort=<string>|[-reformat]|[-remap]|[-quick]|[-standard]

Optimization effort:

reformat|remap|quick|standard



the

tlistand

gn

gy.

such

heace.

ble

ign.

This switch controls the level of effort applied to optimizing the design.Choices foreffort=<string> are:

quick

Attempts only one optimization strategy on the network. This is much faster thanrunning with the standard option, but may not produce as good a final result. This isdefault if no effort option is specified.

reformat

Instructs LeonardoSpectrum to reformat the design from the source to the target neformat. This option does not do an optimization. Can only be used when the sourcetarget technologies are the same. May also be used to determine the size of a desibefore optimization by LeonardoSpectrum.

remap

Does not attempt to optimize the network, but simply maps it into the target technoloThis is useful when the input design is already optimized and mapped to sometechnology and the design needs to be mapped into a new technology. This optionusually results in inferior designs when the input format is technology independent,as VHDL or Verilog.

standard

Runs multiple optimization passes on the design. This is slower than running with tquick option, but may produce better results since it explores more of the design sp

-enable_dff_map_optimize-noenable_dff_map

Enable clock enables from random logic, while noenable disables inferences of clock enaDFFs.

-encoding=<string>

This switch controls the style of state machine encoding applied to a VHDL or Verilog desWhen there are N states,onehot encoding results in N state registers. All other encodingstrategies result in log2(N) state registers.Note: Verilog designs use the “enum” attribute. Thechoices for<encoding_style> are:

binary



his

alues

ingle

More

sry. Ona

Encoding is done based on the definition of the state type, counting left to right. In texample, the following state values are assigned to each state:

Change the order of the enumeration values to achieve different binary encoding vfor each of the states.

gray

Adjacent enumeration values differ only by one bit.

random

Values are encoded in random order (reproducible).

onehot

Each state is assigned a state register. The encoding is one-bit-per-value. Only a sbit is '1' at any given time.

twohot

Two flip flops are set high for each state. This is for large FSMs.

auto

For some technologies, LeonardoSpectrum varies the encoding based on bit width.specifically, enumerated types with fewer elements than global integerlower_enum_break are encoded as binary, larger enumerated types are encoded aonehot. Values larger than global integer upper_enum_break are encoded as binathe GUI,auto may be the default .v allows LeonardoSpectrum to select encoding oncase by case basis.

-entity=<string>

Defines the top level of hierarchy in the VHDL design. See also-architecture=<name> .

state state-bit 012

s0 000

s1 001

s2 010

s3 011

s4 100



thatthis

or

the

ctice

-exclude=<list> | [{<gate_name>}]...[{<gate_name>}]

Directs LeonardoSpectrum not to use the gate<gate_name> when mapping the design to thetarget technology.<gate_name> must be a gate in the target technology. This option can beused multiple times, or can accept a list of gates as the parameter.Not available for: AlteraFLEX and MAX.

Note: If modgen instantiates a gate, exclude will not filter it.

-file=<script_name>

Runs a specified script. For example, name your scripttry.tcl and type:spectrum -file try.tcl .

-full_case

If a case statement is used in the input Verilog, this option specifies to LeonardoSpectrumall conditions of the case statement are specified. If no default assignment was used, thenoption prevents the implementation of extraneous latches.

Note: Refer also to-parallel_case switch.

-generic=<list>=<value> |[{-generic=<name>=<value>}]...[{-generic=<name>=<value>}]

When using VHDL as input to LeonardoSpectrum, this option allows you to set the value fthe specified generic(s). For example,

-generic=Version=16#3201#

This option can be used multiple times or can accept a list of generics as a parameter.

--hdl_input_location

Specifies directories to be searched during a read operation or Verilog ‘include compiledirective.

-hdl_input_location=“E:/my_packages” “C:/common_files”

During a read operation, LeonardoSpectrum first searches for a specified file starting withcurrent working directory (the directory from whichspectrum was invoked). The directory at

Note

Pathnames that Contain SpacesBecause pathnames on a PC platform may contain spaces, it is a good prato enclose the pathname in double quotes.



.

ed

pathnameE:/my_package is searched next, then the directoryC:/common_files . Finally, thedirectory$EXEMPLAR/data is searched. As soon as the file is found, the file is loaded and asearch for the next file begins.

-help

Displays a list of the command line options. You can also type-batchhelp .

[-hierarchy_flatten]|[-hierarchy_preserve]|[-hierarchy_auto]

This option flattens, preserves or auto dissolves your design hierarchy during optimizationDefault ishierarchy_auto (auto dissolve).

-highlight_file=<string>

Critical path highlighting file for Netscope.

-input_format=<string>

Specifies the format of the input design. This is optional if the input format can be determinfrom the extension of the input filename. Supported input file types and correspondingextensions are:

Refer also to the-output_format option.

Both of the following specifications read a VHDL file:

input_filename1.foo -input_format=VHDLinput_filename2.vhd

-logfile=<string>

Specifies the logfile a name. See also-nologfile.

file_type extension description

EDIF .edf, .edif,.eds, .edn

EDIF netlist

VHDL .vhd, .vhdl VHDL

Verilog .v, .vg, .vlg,.verilog

Verilog HDL



iedver,

ied;

s in

re is

-lut_max_fanout=<integer>

Specify the fanout of the net for LUT technologies. Refer also to thelut_max_fanoutvariabledescription.

[-map_area_weight <float>]|[-map_delay_weight <float>]

Specifies an integer between0 and1.0 . The greater the number, the more mapping tries tominimize area. This allows finer control over the-area or -delay switch.

--maxarea=<float>

Specifies the maximum area acceptable for the optimized circuit. This directsLeonardoSpectrum to search for the fastest circuit implementation which meets the specifarea constraint. LeonardoSpectrum tries to find a solution that meets this constraint; howefinding a solution cannot be guaranteed.

-maxdly=<float>

Specifies the maximum delay acceptable for the optimized circuit. This directsLeonardoSpectrum to search for the smallest circuit implementation that meets the speciftiming constraint. LeonardoSpectrum attempts to find a solution that meets this constrainthowever, finding a solution cannot be guaranteed.

-max_fanin=<integer>

This option controls the maximum fanin into a function block when targeting lookup tableFPGA technologies.

-max_frequency=<float>

This option sets the maximum clock frequency timing constraint in Mhz, for all global clockthe design. Integer is 1 to 9999.

-max_pt=<integer>

This option controls the maximum number of product terms in a function. Applies to AlteraMAX technologies only.

-modgen_library=<list>

This option overrides the use of the technology-specific modgen library for the targettechnology. A different external modgen library can be specified, or-modgen_library=nonecan be used to prohibit the use of any external modgen library. If none is specified, or if the



tion

L

.

s areesign.te.gate,y

no technology specific library for the target technology, then default internal module generaroutines are used.

-module=<string>

This option allows the user to specify the top-level module in the hierarchy of a Verilog HDdesign.

-nobreak_loops_in_delay

Directs LeonardoSpectrum NOT to break combinational loops statically for timing analysis

-nobus

This option directs LeonardoSpectrum to write buses in expanded form.

-nocascades

Does not map to cascades during technology mapping for Altera FLEX.

--nocounter_extract

This option disables automatic extraction of counters in VHDL and Verilog.

-nodecoder_extract

This option disables automatic extraction of decoders in VHDL and Verilog.

-noglobal_symbol

This option directs LeonardoSpectrum to process global set/reset when running with-macrooption. When-noglobal_symbol is specified, a startup block is not instantiated.

-nologfile

Do not generate a logfile. See also-logfile=<string>.

--noopt=<list> | [{<gate_name>}]...[{<gate_name>}]

When this option is used, all instances of the specified gate are marked NOOPT. The gatenot touched by the optimization algorithms. The gate appears as unchanged in the output dIf the gate does not exist in any of the input libraries, then a black box is created for this gaSince information does not exist about the area, delay, input loading, or output drive of thethen reports on area and delay are not accurate and the output design may not be properl



leass

tlist.

se

and

buffered.Note: This option can be used multiple times, or can accept a list of files as aparameter.

Example: design_name[-noopt design_name]

-nopass=<list> | [{<pass_number>}]...[{<pass_number>}]

Instructs LeonardoSpectrum to skip the designated pass. These options are only applicabwhen effort isstandard . These options can be used multiple times, or can accept a list of pnumbers as a parameter. See also-pass=<list> | [{<pass_number>}]...[{<pass_number>}].

--noram_extract

This option disables automatic extraction of RAMs from VHDL or Verilog.

-nosdf_hierarchical_names

This option treats all names with the divider character in the SDF file as names in a flat ne

-nosession_file

Do not generate a session history file. See also-session_file=<string>.

-nosummary

Do not create a summary file. See also-summary=<string>.

-notime_opt

Do not run timing optimization.

--notransformations

Disables the conversion of latches, flip-flops, and I/O buffers into more primitive cells if thegates are not available in the target technology.

-nowire_table

Turns off the use of a wire table during delay calculations, which causes interconnect loaddelays to be ignored.

-nowrite_eqn

Disables the writing of LUT functions in the output netlist. Default is on. This option is notpassed when the option is off.



an

ined

allya

-noxlx_preserve_pins

When used, this option inhibits the preservation of pin locations in the netlist when readingXNF netlist.

-num_crit_paths=<integer>

The number of paths to report in the critical path report. The default number is 10.

-optimize_cpu_limit=<integer>

Specifies the CPU limit for the optimize command, in seconds. By default there is no limit.

-output_format=<string>

Specifies the format of the output design. This is optional if the output format can be determfrom the extension of the output filename. Refer also to-input_format option. Supported output file types and corresponding extensions are:

-parallel_case

When using the case statement in the Verilog input design, and case conditions are mutuexclusive, a multiplexer is often the preferred implementation (instead of priority encodingstate machine). This option specifies the multiplexer implementation. Also see-full_case .

-pass=<list> | [{<pass_number>}]...[{<pass_number>}]

Instructs LeonardoSpectrum to explicitly run only the specified Optimization/TechnologyMapping pass, designated by<pass_number> . See also-nopass=<list> |[{<pass_number>}]...[{<pass_number>}]

-process=<string>

Specifies the process variation used in delay calculations. Valid values are technologydependent. This option is used instead of speed grade.

file_type extension description

EDIF .edf, .edif,.eds, .edn

EDIF netlist

VHDL .vhd, .vhdl VHDL

Verilog .v, .vg, .vlg,.verilog

Verilog HDL



e

hs toalso

n

at the

delay

s

ts

-product=<ls1|ls2|ls3>

Invokes a command line run of LeonardoSpectrum with Level 1 (ls1) or Level 2 (ls2) licensinstead of the default Level 3 (ls3) license.

-propagate_clock_delay

When this switch is turned on, delays are propagated through the clock tree along the patthe clock input of the registers. This affects the arrival times at the outputs of registers, andaffects the arrival time at the end points. By default, this switch is turned off to represent aideal clock.

-report_brief|-report_full

This option provides an area report and a report of arrival times, required times and slack10 most critical or latest arriving end points. The-report_full option provides an area reportand a critical path report in the summary file.

-sdf_hier_separator=<string>

This option specifies the separator character to use for hierarchical names in the standardformat (SDF) writer. The default is /.

-sdf_in=<string>

Specifies the SDF input file to be read by LeonardoSpectrum.

-sdf_names_style=<string> (vhdl|verilog|none)

This option specifies the rename rules for the SDF writer. The default is vhdl.

-sdf_out=<string>

Specifies the file where LeonardoSpectrum writes delays in SDF format.

-sdf_type=<string> (min|typ|max)

Specifies type of delay for reading and writing SDF from LeonardoSpectrum. The default imax.

-select_modgen=<string> (smallest|small|fast|fastest)

Specifies the default mode for resolving modgen. Applies to VHDL and Verilog input formaonly. The default isauto (small if optimizing for area,fast if optimizing for delay).



logy,earch

y.

geth

d forrange

r all

-session_file=<string>

Override default session history filename. See also

-simple_port_names

Creates simple names for vector ports:%s%dinstead of%s(%d) . For example, the name for bitone of a bus called abus isabus1 instead ofabus(1 ) .

-source=<list> | [{<library_name>}]...[{<library_name>}]

Specifies the source technology of the input design. To read a source file in a given technothe corresponding technology library must be licensed and found in the search path. The spath for libraries is defined as the working directory and the$EXEMPLAR/lib directory, in thatorder. Libraries can also be specified with a complete path, relative to the working directorThis option can be used multiple times, or can accept a list of libraries as a parameter, fordesigns with multiple input technologies.Note: -source=<library_name> applies any time theinput design has library specific cells instantiated in it. For pure RTL code, no sourcetechnology is required.

-summary=<string>

Specifies the file where the design summary report is written. The default name is<output_filename> .sum . See also-nosummary.

-target=<string>

Specifies the target technology to map the optimized design to. To optimize for a given tartechnology, the corresponding technology library must be licensed and found in the searcpath.The search path for libraries is defined as the working directory and the$EXEMPLAR/libdirectory, in that order. Libraries can also be specified with a complete path, relative to theworking directory.

-temp=<string>

Specifies the operating temperature in celsius/centigrade. The timing information is deratethis operating temperature during delay computations. The value must be in the operatingof the target library.

-tristate_map

Enables conversion of tristate buses to combinational logic. This option is on by default foAltera technologies.



eot

d

ot

kage.

--verilog_file=<list>

List of Verilog files to analyze before main input file.

-verilog_wrapper=<string>

Creates a Verilog wrapper file for the design. This may be used when buses are split in thsynthesized netlist. By default buses are preserved in the output netlist and this option is nnecessary. This option is only necessary if you use the-nobus option.

-vhdl_file=<list>

List of VHDL files to analyze before main input file.

-vhdl_87|-vhdl_93

Directs LeonardoSpectrum to read 1987 style VHDL.-vhdl_87 is mutually exclusive with-vhdl_93 . By default this option is off. The-vhdl_93 option directs LeonardoSpectrum to reathe 1993 style VHDL.-vhdl_93 is mutually exclusive with-vhdl_87 . -vhdl_93 is the default.

-vhdl_wrapper=<string>

Creates a VHDL wrapper file for the design. This is useful when buses are split in thesynthesized netlist. By default buses are preserved in the output netlist and this option is nnecessary.

-vhdl_write_87

Uses VHDL ‘87 style syntax/semantics instead of VHDL ‘93 for writing VHDL.

-vhdl_write_bit=<string>

Specifies the type for the bit used in VHDL writer. The default is standard logic.

-viewlogic_vhdl

For VHDL synthesis, reads the ViewLogic pack1076 built-in package as the standard pac

-voltage=<string>

Specifies the operating voltage in volts. The timing information is derated for this operatingvoltage during delay computations. The value must be in the operating range of the targetlibrary.


License Information Shell-Level Commands

eee

. The

ce is

ctor

er there.

ary

-wire_table=<string>

Allows the selection of a wire table at run time. One or more wire tables are specified in thlibrary. Wire tables give an estimate of wire loads and delays as a function of fanout. Thesestimates can vary with the size of the module. With this option, a specific wire table can bselected. By default, the first wire table specified in the library is used. See also-nowire_table

-wire_tree=<string> (best|balanced|worst)

Sets the interconnect model. The default isworst .

Selectbest to get best case wire tree. This is the best case for interconnect delay. This is 0resistance of the wire is not a factor in the interconnect delay.

Selectbalanced to get a balanced wire tree. In this case, each segment of the wire resistanequally distributed on each of the branches of the net.

Selectworst (default) to get worst case wire tree. In this case, the full wire resistance is a fain the delay, which creates high interconnect delay.

License InformationIf options entered for a batch mode are incorrect, then LeonardoSpectrum attempts to entinteractive command line shell mode. Since the interactive command line shell mode is foLevel 3 only, then a license error message comes up if you only have a Level 1 or 2 licens

Tcl Script SourcingAfter you create a Tcl script in a standard text editor, you can source your Tcl script fromLeonardoSpectrum as follows:

• GUI Menu BarFile -> Run Script

• Command Line with Path to LeonardoSpectrum

Note: The Exemplar history file is a Tcl script file that you can use after making the necessedits.

GUI Menu Bar File -> Run Script

On the menu bar click onFile -> Run Script. Type in your Tcl script name or click on thebutton and choose a Tcl script file. Your script file runs in the GUI Information window.


Shell-Level Commands Tcl Script Sourcing

rerce

cticethe

Command Line with Path to LeonardoSpectrum

Bring up your PC DOS or UNIX window. In the LeonardoSpectrum install area, locate whe$EXEMPLAR points to the location of the software. Type the appropriate argument to souyour Tcl script:

UNIX : $EXEMPLAR/bin/spectrum -file <my_tcl_script>

PC DOS: $EXEMPLAR/bin/win32/spectrum -file <my_tcl_script>

Note

Pathnames that Contain SpacesBecause pathnames on a PC platform may contain spaces, it is a good prato enclose the pathname in double quotes when you are sourcing a file fromInteractive Command Line Shell.


Tcl Script Sourcing Shell-Level Commands


ort for

Chapter 5Tcl Commands

The LeonardoSpectrum command interface is based on the Tcl command language. Thecommands listed in this section are extensions to the basic Tcl language and provide suppthe LeonardoSpectrum synthesis flow.


Tcl Commands

.

.

Command Summary

Table 5-1contains a summary of LeonardoSpectrum-specific Tcl commandsTable 5-1. Alphabetical Command Summary

Command Description

add_rename_rule Add a renaming rule to a ruleset.

alias Define an alternative command for a (set of)command(s).

all_clocks List all clocks.

all_inputs List all input ports.

all_outputs List all output ports.

all_registers List all registers.

all_selected List port, net, object for ports only INOUT or IN OUT.

apply_rename_rules Change the names of objects, using renaming rules.

auto_read Automatically pre-process a technology-specific netlistin addition to executing the read command.

auto_write Prepare the design for netlisting to a target technologythen execute the write command.

balance_loads Resolve load violations in a design across the hierarchy

blackbox Write the instance or view as a blackbox in the outputnetlist.

bubble_tristates Move tristate buffers up in the design hierarchy.

clean_all Remove all objects from the in-memory design database

connect Connect a net with a port or a port instance.

connect_path Connect a timing path on an instance through ports.

copy Copy a single view or the full hierarchy under it andappend the suffix to all the copied view names.

create Create an object.

create_rename_ruleset Create a ruleset for object renaming.

create_wrapper Create a wrapper for a design.


Tcl Commands

.

t

.

decompose_luts Decompose Lookup Tables (LUTs) into AND/OR gates

dfs Perform a depth-first search and return a list of views.

disconnect Remove the connection between a net and a port or porinstance.

disconnect_path Disconnect a timing path in an instance through ports.

do_ip Runs a Quick Setup-type flow when the input designcontains one or more encrypted files.

dont_touch Set the dont_touch attribute on the specified objects(s).

extract_best_passes Find the best pass number for each view that wasoptimized in the last call to the optimize command.

find Find the specified objects in the in-memory designdatabase.

file_line_search Search for and return a list of objects in a give file.

fix_backanno Comment out simulation constructs.

getlist Display the contents of a technology library.

global_set_attribute Set attributes on nets throughout the design hierarchy.

global_remove_attribute Remove attributes on nets throughout the designhierarchy.

help Give help on commands, aliases, and variables.

list_attributes List attributes on specified objects.

list_connection List objects that are connected to the specified object(s)

list_design Return a list of objects in a design.

list_technologies Return a list of technology libraries used in a design.

lo2up Rename all lower case objects with upper case.

load_library Load a technology library.

load_modgen Read a module generator description from a file.

move Move object(s).

Table 5-1. Alphabetical Command Summary

Command Description


Tcl Commands

move_nodelay Move the attribute NODELAY from the input port to theinput flip-flop.

noopt Set the noopt attribute on the specified objects(s).

optimize Optimize and map a design to a target technology.

optimize_timing Perform critical path timing optimization on a design.

place_and_route Place and Route the design using the Vendor-suppliedtools.

pop_design Pop the specified number of levels out of the designstack.

pre_optimize Do constant propagation and other pre-optimization onthe design.

present_design Print or change the present design.

print_design_stack Print out the design stack for informational purposes.

push_design Push into the design stack while preserving the ability topop back to the current position in the stack.

puts_log Put a string to a stdout and log file.

read Read a file and create an in-memory design database.

read_constraints Read in a constraint file.

recompose_flex Recompose LUTs from post place and route.

remove Remove object(s) from the in-memory design database.

remove_attribute Remove an attribute from object(s).

remove_clock Remove the clock information from object(s).

remove_rename_ruleset Remove a ruleset for object renaming.

report_area Report the accumulated area of the present design.

report_constraints List user-specified constraints on any object.

report_delay Report timing information about the design.

report_rename_rules Report the loaded rename ruleset information.

report_wire_tables Report information about wire tables.


Command Description


Tcl Commands

e.

e

restore_project_script Restore a project script file.

select Select a list of objects.

set_altera_eqn Replace the following Altera variables: edif_eqn_and,edif_eqn_not, edif_eqn_not_is_prefix, edif_eqn_or,edif_function_property.

set_attribute Create or set an attribute on an object(s).

set_clock Create or set clock information on an object(s).

set_multicycle_path Constrain a path that requires more than one clock cycl

show_var_settings Display all variable settings made in a session.

unalias Remove an alias.

undont_touch Remove the dont_touch attribute from the specifiedobjects(s).

ungroup Flatten out the hierarchy.

unmap Flatten out technology cells in the design downtoprimitives.

unnoopt Remove the noopt attribute on the specified objects(s).

up_design Traverse the design hierarchy by moving up one or morlevels.

view_schematic Display a schematic view of the current design (default)or of the specified design.

warp_vhdl Aliased to “uplevel #0 set vhdl_write_use_packages“\”library ieee, work; use ieee.std_logic_1164.all;\nuseWORK.EXEMPLAR_GATES.ALL;\”””

write Write a design to a file.

xmplr_exec A version of an executable supporting a nonblockingread.

xmplr_socket_client Open a client socket.


Command Description


Commands Tcl Commands

hell.

Commands

Aliases

This alias list covers commands that are also available in the Interactive Command Line S

al Aliased toLIST_ATTRIBUTES

arrival_time Aliased toARRIVAL_TIME

buffer_sig Aliased toBUFFER_SIG

clock_cycle Aliased toCLOCK_CYCLE

clock_offset Aliased toCLOCK_OFFSET

clock_cycle Aliased toCLOCK_CYCLE

connect_timing_arc Aliased toCONNECT_TIMING_ARC

dc Aliased toPRESENT_DESIGN

dl Aliased toLIST_DESIGN

disconnect_timing_arc Aliased toDISCONNECT_TIMING_ARC

h Aliased toHISTORY

input_max_fanout Aliased toINPUT_MAX_FANOUT

input_max_load Aliased toINPUT_MAX_LOAD

max_trans_fall Aliased toMAX_TRANS_FALL

max_trans_rise Aliased toMAX_TRANS_RISE

modgen_read Aliased toMODGEN_READ

modgen_resolve Aliased toMODGEN_RESOLVE

nobuff Aliased toNOBUFF

noopt Aliased toNOOPT

output_fanout Aliased toOUTPUT_FANOUT

output_load Aliased toOUTPUT_LOAD

pd Aliased toPRESENT_DESIGN.

pin_number Aliased toPIN_NUMBER


Tcl Commands Commands

preserve_signal Aliased toPRESERVE_SIGNAL

pulldown Aliased toPULLDOWN

pullup Aliased toPULLUP

pulse_width Aliased toPULSE_WIDTH

quit Aliased toEXIT

required_time Aliased toREQUIRED_TIME

run_opt Aliased toOPTIMIZE

sc Aliased toSOURCE_CONSTRAINTS

sweep Aliased toPRE_OPTIMIZE

synthesis Aliased toELABORATE

uniquify Aliased toUNFOLD

unnoopt Aliased toUNNOOPT

undont_touch Aliased toUNDONT_TOUCH



with the

ted

net,

add_rename_ruleAdd a renaming rule to a ruleset.

Exampleadd_rename_rule ALTERA -find_substring ")(" -replace "_"

This example replaces all instances of the open and closed parentheses characters) and (underscore character _.

Syntaxadd_rename_rule <ruleset_name>

[ -type <type_of_objects>][ -find_word <word>]|[ -length_exceeds <integer>]|[ -find_substring <substring>]|[ -find_character <characters>]|[ -find_first_character <characters>]|[ -find_last_character <characters>][ -replace <replace_string>]|[ -prepend_word ][<prepend_string>]|[ -truncate_word <integer>]|[ -append_word <append_string>] |[ -escape_word <escape_string>]

Arguments• <ruleset_name>

Name of the ruleset to which this rule should be added. The ruleset should first be creausing thecreate_rename_ruleset command. This is a string type of argument.

Options• -type <type_of_objects>

Type of objects to which this renaming rule applies. Valid values are all (default), port,instance, view and cell.

Type Arguments

string <ruleset_name>, <type_of_objects>, <word>, <substring>,<characters>, <replace_string>, <prepend_string>,<append_string>, <escape_string>

integer<truncate_word>, <length_exceeds>



e

sh.

ouble

ouble

• -find_word <word>

Matchesword exactly. This option is mutually exclusive with the-find_substring ,-find_character , -find_first_character and -find_last_character options (onlyone may be specified at a time).

• -length_exceeds <integer>

The length of the word exceeds the specifications.

• -find_substring <substring>

Matchessubstring anywhere in a word. This option is mutually exclusive with the-find_word , -find_character , -find_first_character and -find_last_characteroptions.

• -find_character <characters>

Matches any <characters> anywhere in a word. This option is mutually exclusive with th-find_word , -find_substring , -find_first_character and-find_last_character options. Specify any number of characters, enclosed in doublequotes. To specify the double quote or back slash character, escape it using a back sla

• -find_first_character <characters>

Matches any <characters> at the start of a word. This option is mutually exclusive withthe -find_word , -find_substring , -find_character and-find_last_characteroptions. Specify any number of characters, enclosed in double quotes. To specify the dquote or back slash character, escape it using a back slash.

• -find_last_character <characters>

Matches anycharacters at the end of a word. This option is mutually exclusive with the-find_word , -find_substring , -find_character and-find_first_characteroptions. Specify any number of characters, enclosed in double quotes. To specify the dquote or back slash character, escape it using a back slash.

• -replace <replace_string>

Replaces any match found (using the -find_word, -find_substring,-find_character , -find_first_character or -find_last_character options) with thespecifiedreplace_string . This option is mutually exclusive with the-prepend_word ,-append_word , and-escape_word options.

• -prepend_word <prepend_string>

Prependsprepend_string to any word with a match found (using the-find_word ,-find_substring , -find_character , -find_first_character or-find_last_character options). This option is mutually exclusive with the-replace ,-append_word , and-escape_word options.

• -append_word <append_string>

Appendsappend_string to any word with a match found (using the-find_word ,-find_substring , -find_character , -find_first_character or



e the

h

^ `

> [ ]

sand

-find_last_character options). This option is mutually exclusive with the-replace ,-prepend_word , and-escape_word options.

• -truncate_word <integer>

Shorten the word to the specified length.

• -escape_word <escape_string>

Escapes any word with a match found (using the-find_word , -find_substring ,-find_character , -find_first_character or -find_last_character options) withthe two characters specified inescape_string . This option is mutually exclusive with the-replace , -prepend_word . This replaces any match with thisstring .

DescriptionThe add_rename_rule command adds an individual rule to a ruleset, defined with thecreate_rename_ruleset command. Rename rules may be used to modify any filenameswhich LeonardoSpectrum produces into filenames acceptable to your third-party tools. Us-find* options to identify which (illegal) words, substrings or characters to modify. Use the-replace , -prepend_word , -append_word and -escape_word options to specify what to dowith each match found using the-find* options. Multiple rename rules may be added to eacruleset.

More Examples

add_rename_rule ALTERA -find_character "\"#*+,-./:;=|!$%@?\\^`~" -replace "_"

This example replaces all instances of the (illegal) characters " # * + - , . / : ; = | ! $ % @? \and ~ with the underscore character _.

add_rename_rule ALTERA -find_character "()<>\[\]{}" -replace ""

This examples deletes (replaces with an empty string) all instances of the characters ( ) <{ and }.

add_rename_rule ALTERA -find_first_character _0123456789 -prepend "&"

This example prepends any word that begins with a number or underscore with the amper(&) character.

Related Commands

apply_rename_rulescreate_rename_ruleset

remove_rename_rulesetreport_rename_rules



ur in

trum

n only;

eeds

aliasDefine an alternative command for a (set of) command(s).

Examplealias dl list_design

This command defines an alias nameddl , which executes the LeonardoSpectrum commandlist_design.

Syntax

alias [<alias_name> [{script_expansion}]]

Arguments• <alias_name>

Name of an alias to define or to display. If you omit this argument, thealias command listsall defined aliases. This is a string type of argument.

• <script_expansion>

Tcl script (sequence of commands) that is executed in place of the alias. If spaces occscript , put braces ({}) around it, as in any Tcl script. If you specifyalias_name and omitscript , the existing definition of the alias is displayed.

DescriptionThealias command defines a new command that executes either a built-in LeonardoSpeccommand or a Tcl script.

When you use an alias, any added arguments are appended to the script (for that executiothe script itself is not modified).

Thealias command is very suitable for the simple redefinition of commands. When you nscripts with multiple commands, or when arguments cannot be simply appended to an aliascript, it is easier to write a Tcl procedure (with the Tclproc command) rather than create analias.

More Examplesalias list_ports {list_design -ports}

This command defines an alias namedlist_ports , which executes the LeonardoSpectrumcommandlist_ports -ports .

alias dl

This command causes the alias command to display the script for the alias dl. alias dllist_design



This example defines an alias nameddl , which executes the LeonardoSpectrum commandlist_design.

Related Commands

help unalias



all_clocksList all clocks.

Exampleall_clocks fir_filter -short

Syntax

all_clocks [<design>][ -short ][ -interanl ]

Arguments• <design>

Name of the design

Options• -short

Print only short names not the full path to objects.

• -interanl

Print only the paths to internal clock nets..

Related Commands

Type Arguments

string <design>

list_design



all_inputsList all input ports.

Exampleall_inputs fir_filter -short

Syntax

all_inputs [<design>][ -short ]


Name of the design

Options• -short


Related Commands

Type Arguments

string <design>



all_outputsList all output ports.

Exampleall_inputsfilter -short

Syntax

all_inputs [<design>][ -short ]

Arguments

• <design>

Name of the design

Options• -short


Related Commands

Type Arguments

string <design>



all_registersList all registers.

Exampleall_registersfilter -short

Syntax

all_registers [<design>][ -short ]

Arguments

• <design>

Name of the design

Options• -short


Related Commands

Type Arguments

string <design>



all_selectedList port, net, object for ports only INOUT or IN OUT.

Exampleall_selectedf ilter -short

Syntax

all_selected [<port>][<net>][<instance>][ -direction <string>]

Arguments

• <port>

Name of the design

• <net>

Name of the design

• <instance>

Name of the design

Options

• -direction <string>


Related Commands

Type Arguments

string <port> <net> <instance>



med.

apply_rename_rulesChange the names of objects, using renaming rules.

Example

Syntax

apply_rename_rules [<design>] -ruleset <ruleset>[ -single_level ][ -test ]


Name of the design where names of objects are to be changed using renaming rules.

• -ruleset <ruleset>

The is the rename ruleset string that should be applied to the design.

Options• -single_level

Apply the renaming rules only at the top level of the design hierarchy.

• -test

Do not apply the ruleset renaming string. Instead, produce a report of what will be rena

Related Commands

Type Arguments

string <design>, <ruleset>

add_rename_rulecreate_rename_ruleset




ad

auto_readAutomatically pre-process a technology-specific netlist in addition to executing the readcommand.

Includes the setting of variables.

Automatically does needed processing for technology-specific netlists in addition to the recommand, including setting the values of variable.

Altera Note: auto_read replaces the previously available read_altera script.

Related Commands



g for

er

nt a

l

auto_writePrepare the design for netlisting to a target technology then execute the write command.

Description

This command executes the write command, but in addition it does the needed processinyour target technology, including setting the proper variable values and callinggenerate_timespec , decompose_luts andapply_rename_rules , where applicable.

Attribute Removal

The following applies to theauto_write command, thedecompose_luts command, and thenoopt / dont_touch attributes:

If you want to use theauto_write command for a bottom-up hierarchical design, then considthe following:

• After you synthesize the lower modules of your design the first time, you can prevesecond optimization of these modules by applyingnoopt and/ordont_touch attribute toeach module.

• However, before usingauto_write command, you must manually remove thedont_touch andnoopt attributes. Otherwise, the output FPGA netlist is not valid inmost cases.

Before executing this commnad, you can set theedifout_write_noopted_contents variableto TRUEto write the contents of yournoopt / dont_touch modules into an EDIF file. If you donot set this variable, then you may have some black boxes in your netlist that the P&R toocannot read.

Related Commands

Related Attributes

decompose_luts unmap

dont_touch noopt



pe of

time.onries

gn,alyzese

balance_loadsResolve load violations in a design across the hierarchy.

Examplebalance_loads

Resolve load violations on hierarchy boundaries anywhere in the present design.

Syntax

balance_loads [<design_name>][ -single_level ]

Arguments• <design_name>

Name of the design for which thebalance_loads command performs load balancing. Ifyou omit this argument, the command operates on the present design. This is a string tyargument.

Options

• -single_level

Perform load balancing only at the top level of hierarchy. If you omit this option, thebalance_loads command performs load balancing on the entire design hierarchy.

Description

Thebalance_loads command resolves load violations throughout the design. Most of theLeonardoSpectrum commands work on individual levels of hierarchy in the design at oneWith this method, load violations on internal nets (not connected to ports) can be resolvedthe fly. However, in a hierarchical design, load violations can still be created at the boundaof the levels of hierarchy.

To assure that gates do not drive more load than they are allowed to anywhere in the desiLeonardoSpectrum traverses the entire hierarchy of the design starting at the bottom. It anall nets for load violations, and it uses buffer (tree) insertion to resolve these violations. Thbalance_loads command is sensitive to the following design constraints (attributes):

• On inputs/inouts:OUTPUT_LOADandOUTPUT_FANOUT

Type Argument

string <design_name>



the

• On outputs/inouts:MAX_LOADandv

More Examplesbalance_loads .work.second.contents

Resolve load violations on hierarchy boundaries anywhere in the viewcontents of the cellsecond in the librarywork .

Related Variables

Known Bugs, LimitationsThis command is only effective after the design is mapped to a particular technology withoptimize command.

map_sync_regmax_fanout_load

max_transitionoptimize_drc_resolving



blackboxWrite the instance or view as a blackbox in the output netlist.

Example

Syntax

blackbox <instance_name | view_name>

Description

You must ensure that view_name is hierarchical. The specified view_name is written as ablackbox in the output netlist.

Related Commands



e

ert

bubble_tristatesMove tristate buffers up in the design hierarchy.

Example

bubble_tristates

Syntax

bubble_tristates

Description

This command moves tristate buffers up in the design hierarchy, allowing you to optimizedesigns with buried tristate I/Os without flattening.

Choose (1) or (2) for setting the bubble_tristes variable:

1. Setbubble_tristates true if tristatesare not in common levels. The tristates bubbleup to the common top level.

2. Setbubble_tristates true if tristatesare feeding an output port. The tristates bubblup to the top primary output port. This occurs if tristates are eitherin or not in acommon level.

3. Setbubble_tristates false to disable.

Note: During optimization tristates automatically bubble up to level of hierarchy where alldrivers become visible, or bubble up to top level of boundary.

Note: bubble_tristates only bubbles boundary tristates up to a level where all drivers of anet becomes known.bubble_tristates does not bubble internal tristates and does not convtristates to muxes. The conversion of tristates to muxes is controlled bytristate_mapvariable.

Related Varaibles

bubble_tristates



clean_allRemove all objects from the in-memory design database.

Related Commands



soluteview.

d can

connectConnect a net with a port or a port instance.

Exampleconnect -port clk -net clk

This command line connects the portclk in the present design to the netclk in the presentdesign. This example is valid only if present design is a view.

Syntax

connect -port <port_name> -net <net_name>

Arguments• -port <port_name>

Formal name of an existing port to connect to the netnet_name . Only a single port orport-instance is accepted. This is a string type of argument.

• -net <net_name>

Formal name of an existing net to which you are connecting a port. Only a single net isaccepted. This is a string type of argument.

DescriptionThe connect command attaches a net to a port or port-instance. You can use relative or abport and net names. The net and the port or port-instance must be contained in the same

If the specified port or port-instance is already connected to a different net, it will bedisconnected first, then connected to the new net.

This command operates at a very low level of the design and changes the structure of thedesign. Simulation differences between pre- and post-synthesized versions of a design anoccur as a result of using this command.

More Examplesconnect -port inst73.reset -net rst

This example connects the port-instancereset of instanceinst73 in the present design to netrst in the present design. This example is valid only if present design is a view.

connect -port .work.top.contents.Out -net .work.top.contents.outnet

Type Arguments

string <port_name>, <net_name>



This example connects the portOut in the viewcontents in the celltop in the librarywork tothe netoutnet in the same view.

Related Commands

Known Bugs, LimitationsThere is no way to connect a net to multiple ports or port-instances with a single connectcommand.

disconnect list_connection



hisrough

connect_pathConnect a timing path on an instance through ports.

Example

Syntax

connect_path <port_names>[ -instance <instance_name>] | [ -gate <gate_name>] | [ -all ]

Arguments• <port_names>

Connect a timing path on an instance through ports.

Options

• -instance <instance_name>

Connect a path on instance_name.

• -gate <gate_name>

Connect a path on the instances of gate_name.

• -all

Connect paths on all instances.

Description

This command marks a timing arc in an instance of a gate as connected or propagating. Tcommand can be used to reconnect paths marked as false paths, or to reconnect paths thwhich timing analysis is desired.

More Examples

# connects set to q of DFF instance, DFF_inst1connect_path -instance DFF_inst1 SET Q

Type Arguments

string <port_names>, <instance_name>, <gate_name>



. If all
When gate is specified, all paths for all instances of this gate are disconnected/connectedSET to Q paths need to be connected/disconnected, for all gates that have these pins,-alloption can be used.
Related Commands



ts.

copyCopy a single view or the full hierarchy under it and append the suffix to all the copied viewnames.

Example

Syntax

copy <object1> <object2> | <object container>[ -hier <suffix_name>]

Arguments• <object1>, <object2>

Names of source and target design objects.object1 must exist prior to the copy operation,but object2 must not. This is a string type of argument.

• <object_container>

Name of an object in a design that is designed to organize and hold other design objecExamples are libraries and cells. Both source and targetobject_containers must existprior to the copy operation. This is a string type of argument.

Options

• -hier <suffix_name>

This option is only applicable to views. The entire hierarchy under view is copied. Thesuffix is appended to every copied view.

Description

The copy command duplicates the contents of an existing design object.

More ExamplesThere are two examples for thecopy command: Single View Copy and Full Hierarchy UnderView Copy.

Single View Copy

Type Arguments

string <object1>, <object2>, <object_container>, <suffix_name>



fix

copy .work.design.contents .work.design.save

This example copies the viewcontents contained in the celldesign within the librarywork tothe viewsave in the same cell.

Full Hierarchy Under View Copy

copy -hier _copy .work.address_decoder.test

This example copy command copies the entire hierarchy under view and appends the suf“_copy ” to every view that is copied as follows:

.work.address_decoder.test_copy

Related Commands

Known Bugs, LimitationsThecopy command does not copy ports, nets, or instances. You must use thecreate commandfor that purpose.



te

cts

reate

createCreate an object.

Examplecreate -port X -direction IN

This command line creates an input port namedX in the present design. This example is validonly if the present design is a view.

Syntax

create<object_name>[ -port ]|[ -net ]|[ -instance ][ -direction <port_direction>][ -of <view_name>]

Arguments

• <object_name>

Name of a design object, such as a library, cell, view, net, port, or instance for the creacommand to create. This is a string type of argument.

Options

• -port, -net, -instance

Type of the created object, if it is within a view.

• -direction <port_direction>

For port objects, the port type. Valid values forport_direction areIN , OUT, andINOUT.

• -of <view_name>

Defines the name of the view to instantiate. This argument is required for instance objeonly.

DescriptionThe create commvand makes a new object in the design. If the object already exists, the ccommand issues an error message.

Type Arguments

string <port_direction>, <view_name>



More Examplescreate .save_work

This example creates a new library calledsave_work .

create -instance vdd -of .PRIMITIVES.TRUE.INTERFACE

This example creates an instance of the view of the primitive cellTRUE(generic power symbol)namedvdd within in the present design.

Related Commands

removemovecopy

connectdisconnect



create_rename_rulesetCreate a ruleset for object renaming.

Example

Syntax

create_rename_rulese t <ruleset_name>[ -no_collision_between <object_list>][ -case_insensitive ]


Create a ruleset for object renaming.

Options

• -no_collision_between <object_list>

Valid values inobject_list are port, net, or instance. Renaming rule is created to avoidname collisions between objects of these types.

• -case_insensitive

Disregard case when checking name collisions.

More Examples

Related Commands

Type Arguments

string <ruleset_name>, <object_list>

list <object_list>

apply_rename_rulesadd_rename_rule




ng

d to

create_wrapperCreate a wrapper for a design.

Example

Syntax

create_wrapper [<root_entity/module_name>][ -architecture <architecture_name>][ -work <library_name>][ -file <file_name>][ -wrap_name <wrapper_name>][ -parameters <parameters_list>]|[ -generics <generics_list>]

Arguments• <root_entity/module_name>

Name of the VHDL entity or configuration or the Verilog module for which you are creatia simulation wrapper. The design unit must exist in the in-memorywork HDL library or inthe library indicated with the-work option. If you omit this argument, the design unit thatwas most recently analyzed (with the analyze or read <file_name(s)> command) is usecreate a simulation wrapper.

Options• -architecture <architecture_name>

Name of the VHDL architecture for which you are creating a simulation wrapper. Thearchitecture must exist under the root design unit. If you omit this argument, thecreate_wrapper command elaborates the most recently analyzed architecture ofroot_entity / module_name .

• -work <library_name>

Defines the HDL library where theroot_entity / module_name resides. If you omit thisargument, thecreate_wrapper command uses the HDL library namedwork .

Type Arguments

string <root_entity/module_name>, <architecture_name>, <file_name>,<wrapper_name> <library_name>

list <parameters_list>, <generics_list>



e. Inof a

e of the

rs,

Llexrt

, theo create

an, a

e.

• -file <file_name>

Defines the name of the file in which to write the simulation wrapper.

• -generics <generics_list>

Specify the setting of a generic in the top-level VHDL entity that will be elaborated. Notthat case-insensitive identifiers in VHDL are changed to lower case before elaborationthat case, define the name of the generic in lower case. This option also sets the valueparameter of the top-level Verilog module to be elaborated.

The create_wrapper command parses the value of each generic and compares the typvalue with the type of the generic.

The syntax ofgenerics_list is {generic=value generic=value...}

The following example is valid for a design unit with an integer genericsize , an arraygenericseed , and an enumeration-type (boolean) genericuse_this :

-generics { size=9 seed="00100011" use_this=TRUE }

• -parameters <parameter_list>

Equivalent to-generics <generics_list.>

DescriptionSynthesizing with LeonardoSpectrum expands complex types on ports (like arrays, integerecords, enumeration types) to individual bits. This creates a mismatch between thepre-synthesis and post-synthesis port list for VHDL and Verilog designs. To still be able tosimulate a post-synthesis netlist (in Verilog or VHDL) with a pre-synthesis Verilog or VHDtestbench, you can create a simulation wrapper. The wrapper model has the original comptypes on the port boundaries, and it instantiates a post-synthesis model (with bits at the poboundaries).

The create_wrappecommand creates the wrapper from the HDL library models. Thereforecreate_wrappe command takes almost the same arguments as the elaborate command. Ta wrapper model, you just need to analyze the top-level VHDL or Verilog model.

For VHDL source code, a VHDL wrapper will be created. The wrapper model will consist ofarchitecture that can be linked to the original entity of the design. For Verilog source codenew Verilog module will be created.

For VHDL, the create_wrappecommand uses type transformation functions from thetypetranpackage ($EXEMPLAR/data/typetran.vhd ) to translate the complex types to the bits of thesynthesized VHDL model. For Verilog, the wrapper does not require additional source cod

Related Commands

apply_rename_rulesextract_best_passes

write



isng type

tural

ing

decompose_lutsDecompose Lookup Tables (LUTs) into AND/OR gates.

Example

Syntax

decompose_luts [<design_name>][ -group_luts ][ -single_level ]

Arguments

• <design_name>

Name of the design to be used for the lookup table (LUT) decomposition. If you omit thargument, the decompose_luts command operates on the present design. This is a striof argument.

Options• -group_luts

Create a new view for each LUT.

• -single_level

Perform decomposition only at the top level of hierarchy. If you omit this option, thedecompose_luts command traverses the entire design hierarchy.

DescriptionThe decompose_luts command decomposes lookup tables (LUTs) within a view into strucnetlists expressed in terms of AND and OR gates. LUTs are created by theoptimizecommand.

You can usedecompose_luts : (1) to write out netlists in formats, such as EDIF, that do notsupport behavioral descriptions, such as LUTs; and (2) before unmapping designs containlookup tables.

You cannot re-assemble structural netlists back into LUTs. Therefore, you should use thedecompose_luts command just prior to writing the design to a file.

Type Arguments




Related Commandss

Related Variables

Known Bugs, Limitations

Area reporting may not include LUTs after they have been decomposed.

auto_writeoptimize

unmap

lut_cell_name



dfsPerform a depth-first search and return a list of views.

Related Commands



.

e orthe

d can

s

disconnectRemove the connection between a net and a port or port instance.

Exampledisconnect -net clk -port clk

This example disconnects the portclk from the netclk , both of which are in the present designThis example is valid only if the present design is a view.

Syntax

disconnect -port <port_name> -net <net_name>

Arguments• -port <port_name>

Name of an existing port to disconnect from the netnet_name . Only a single port orport-instance is accepted.

• -net <net_name>

Name of an existing net from which you are disconnecting a port. Only a single net isaccepted.

DescriptionThe disconnect command detaches a net from a port or port-instance. You can use relativabsolute port and net names. The net and the port or port-instance should be contained insame view.

This command operates at a very low level of the design and changes the structure of thedesign. Simulation differences between pre- and post-synthesized versions of a design anoccur as a result of using this command.

More Examplesdisconnect -net rst -port .work.top.contents.reset

This example disconnects the netrst in the present design from the portreset in the viewcontents of cell top within the librarywork . This example is valid only if the present design iset to the view containing the portreset .

disconnect -port modgen_1.d(0) -net data(0)

Type Arguments

string <port_name>, <net_name>



This example disconnects the port-instanced(0) of instancemodgen_1 in the present designfrom netdata(0) in the present design. This example is valid only if the present design is aview.

Related Commands


There is no way to disconnect a net from multiple ports or port-instances with a singledisconnect command.

connect list_connection



d canwhich

disconnect_pathDisconnect a timing path in an instance through ports.

Example

Syntax

disconnect_path <port_names>[ -instance <instance_name>] | [ -gate <gate_name>] | [ -all ]

Arguments• <port_names>

Disconnect a timing path on an instance through ports.

Options

• -instance <instance_name>

Connect a timing path on instance_name.

• -gate <gate_name>

Connect a timing path on the instances of <gate_name>.

• -all

Connect paths on all instances.

Description

This command marks a timing arc in an instance of a gate as disconnected. This commanbe used to block false paths. These false paths are asynchronous paths or paths throughtiming analysis is not desired.

More Examples# disconnects set toq of DFF instance, DFF_inst1

disconnect_path -instance DFF_inst1 SET Q

Type Arguments

string <port_names>, <instance_name>, <gate_name>



.s,

When gate is specified, all paths for all instances of this gate are disconnected/connectedIf all SET to Q paths need to be connected/disconnected, for all gates that have these pin-all option can be used.

Related Commands



.

s and

he

do_ipRuns a Quick Setup-type flow when the input design contains one or more encrypted files

Syntax

do_ip <file_name(s)>[ -format <format_name>][ -design <design_name>][ -architecture <architecture_name>][ -work <library_name>][ -parameters <parameters_list>]|[ -generics <generics_list>][ -target <technology_name>][ -hierarchy <auto|preserve|flatten>][ -effort <effort_type>][ -area ]|[ -delay ][ -pass <pass_nums>]|[ -nopass <pass_nums>][ -output <output EDIF_filename>]

Arguments• <file_name(s)>

Name of the input file or list of files.file_name(s) can be local filenames, relative pathnames, or absolute path names.

If multiple filenames are specified, use the Tcl list format, eg{name1 name2} . If filenameswith spaces are specified, wrap the filename with spaces in either quotes or curly bracewrap the list of one or more filename in curly braces, eg{“filename with spaces”} or{{filename with spaces}} or {“first filename with spaces” {second filenamewith spaces} normal filename} .

Example:do_ip {“my files/file1.vhd” “other files/file2.vhd”}

Always use the forward slash character (/ ) to separate directory names in a path, even on tPC. LeonardoSpectrum interprets the back-slash character (\ ) as a Tcl escape character.

Type Arguments

string <format_name>, <design_name>, <architecture_name>, <library_name><technology_name>, <effort_type>

list <file_names>, <parameters_list>, <generics_list>, <pass_nums>



on.

root

in

e. Inof a

lue

Options• -format <format_name>

The format of the input file. Valid values are as follows: verilog and VHDL.

If you omit this argument, thedo_ip command attempts to determine the file format fromthe filename extension, as shown in the following table.

If the do_ip command cannot determine the file format, it prompts you for the informati

• -design <design_name>

Specify top level design name to be read.

• -architecture <architecture_name>

Name of the VHDL architecture to be elaborated. The architecture must exist under thedesign unit. If you omit this argument, thedo_ip command elaborates the most recentlyanalyzed architecture ofroot_entity/module_name> .


Store designs in the input file inlibrary_name instead of thework library. This argument isonly effective for VHDL and Verilog formats, where the library of a design is not definedthe file itself.

• -generics <generics_list>

Specify the setting of a generic in the top-level VHDL entity that will be elaborated. Notthat case-insensitive identifiers in VHDL are changed to lower case before elaborationthat case, define the name of the generic in lower case. This option also sets the valueparameter of the top-level Verilog module to be elaborated.

Thedo_ip command parses the value of each generic and compares the type of the vawith the type of the generic.

The syntax ofgenerics_list is {generic=value generic=value...}

The following example is valid for a design unit with an integer genericsize , an arraygenericseed , and an enumeration-type (boolean) genericuse_this :

-generics { size=9 seed="00100011" use_this=TRUE }

• -parameters <parameter_list>

Equivalent to-generics <generics_list.>

• -target <technology_name>

Name of the technology library to use when thedo_ip command optimizes the design.

File Name Extension File Format

.v, .verilog Verilog

.vhd, .vhdl VHDL



.d

enstem

• -hierarchy <auto|preserve|flatten>

• auto (auto_dissolve) is selected by default. Logic is equated to 2-input NANDgates, and hierarchy is dissolved according to the following rules:

i. FPGA/CPLD auto_dissolve limit is 50 gates (default).

ii. There is a maximum system limit of gates that can be dissolved in a moduleThis system limit cannot be modified by a user switch. If this limit is exceedethenauto_dissolve is not completed. Theauto_dissolve dissolves instancesin a context sensitive manner. If a module is instantiated more than once, ththe instance is dissolved only if total number of gates does not exceed the sylimit.

• If preserve is selected, then hierarchy is not dissolved during optimization.

• If flatten is selected, then the entire design hierarchy is flattened (dissolved).

• -single_level

Optimize only the top-level view of the design. If you omit this option, thedo_ip commandoptimizes all views in the design hierarchy in a bottom-up manner.

• -effort <effort_type> (default)

Level of effort thedo_ip command should use during the optimization process. Validvalues are as follows:

• -area (default)| delay

The-area option tells thedo_ip command to minimize area in the optimized design. The-delay option instructs thedo_ip command to minimize delay in the optimized design.

• -pass <pass_nums>| -nopass <pass_nums>

The-pass option tells thedo_ip command to perform only the indicated optimizationpasses. The-nopass option instructs thedo_ip command not to perform the indicatedoptimization passes. LeonardoSpectrum performs a maximum of 4 passes.

remap Performs some local optimization and technology mapping to thetarget technology.

quick Performs one pass of optimization and technology mapping. This isa fast optimization effort that is usually be used at the beginning ofthe design cycle.

standard(default)

Performs multiple passes of optimization and technology mapping.Applies different strategies of optimization, and usually achievesbetter results than thequick effort, but takes more time.



pies, then

thend.

• -output <output_name>

This is the full pathname of the encrypted EDIF file that is to be generated.

DescriptionThe do_ip command runs an entire flow similar to the Quick Setup flow. This command coa design from one or more encrypted files into the LeonardoSpectrum in-memory databasesynthesizes and optimizes the design according to the options that are set. The design iswritten to disk as one encrypted EDIF file, a report is generated, and the memory is cleare

Related Commands

Related Variables

encodingfull_casehdl_array_name_stylehdl_input_locationhdl_integer_name_stylehdl_record_name_style

parallel_casepreserve_dangling_netuse_dffenableviewlogic_vhdlvhdl_87



y

dont_touchSet thedont_touchattribute on the specified objects(s).

Exampledont_touch .work.filter_top.rtl

This command sets thedont_touch attribute toTRUEon the data base object.work.filter_fsm.rtl

Syntax

dont_touch <object1> <object2>

Arguments• <object>

Name of an instance or view on which to set thedont_touch attribute. One or more objectnames may be specified.

Descriptiondont_touch is an alias to thedont_touch command. This command provides a short handmethod for setting thedont_touchattribute. Setting adont_touch attribute specifies that aninstance or view should not be optimized or changed, including the lower levels of hierarchand leaf instances.

For example, consider the following command line entry:

dont_touch .work.filter_top.rtl

This is the same as entering the followingset_attribute command line:

set_attribute .work.filter_top.rtl -name DONT_TOUCH -value TRUE

Related Commands

Related Attributes

nooptunnoopt

undont_touch

dont_touch noopt



extract_best_passesFind the best pass number for each view that was optimized in the last call to the optimizecommand.

Related Commands



hekeand

r

findFind the specified objects in the in-memory design database.

Example 1find *gen*

Find all objects with the sub-string “gen” in the name

Example 2arrival_time 7 [find arbit -port]

Apply an arrive time of 7 ns to all ports that contain the string “arbit”.

Syntax

find < object> -- object to search for[ -start < string> ]-- the object library, cell, view or instance

from where to start the search[ - nohier ] -- do not search through hierarchy (default FALSE)[ - show_scope ] -- add the instance scoping path to found hierarchical

object(default FALSE)[ -all ]-- match all objects (default TRUE)[ -library ]-- match libraries (default FALSE)[ -cell ]-- match cells (default FALSE)[ -view ]-- match views (default FALSE)[ -inst ]-- match instances (default FALSE)[ -pin ]-- match pins (default FALSE)[ -port ]-- match ports (default FALSE)[ -net ]-- match nets (default FALSE)[ -matchcase ]-- case sensitive (default FALSE)\[ -wholeword ]-- match whole word only (default FALSE)[ -regexp ]-- search string in a Regular Expression (default FALSE)

DescriptionThis Tcl scripting command allows you to search through the in-memory database for all tmatching objects. The return type is a TCL list. You can use this list in other commands (liforeach andselect). This find command itself can be used as an argument to another commforcing that command to apply not to a single item, but to the entire set of object that areidentified by the database search.

• -start <string>

Name of the starting point for the search. This can be the name of a library, cell, view oinstance. If this argument is not set, the present working design (PWD) is used.



w of

ned

ceerellsiew

• -nohier

For hierarchical designs, this switch tells LeonardoSpectrum to search the defining vieeach instance as well as the instance itself.

• -all

Match all objects. This is the default (TRUE). If any other match criteria is set, this is turoff.

• -library

Matches libraries.NOTE: Libraries can only be found when the PWD or –start switch is set to “.”

• -cell

Matches cells.

• -view

Matches views.

• -inst

Matches instances. An instance will match if one of three things is true: 1) if the instanname matches, 2) if the defining view’s name matches, or 3) if the defining view’s owncell’s name matches. This allows you to search for “DFF” and find all instances who’s care DFF. Or in another case, you can search for and find all instances with a defining v“SmallAndFast”.

• -pin

Matches pins

• -port

Matches ports

• -net

Matches nets.

• -matchcase

Match names with the exact case.

• -wholeword

Match whole words only.

• -regexp

A llow TCL regul arexpr essi onst o bei n thesear ch st ring.

Return Value



Error Messages

Related Commands



listjects

file_line_searchSearch for and return a list of objects in a give file.

Example

Syntax

file_line_search [<object>] --list line and file info for this object[ -file < string >] -- name of the file to search[ - line < list >] -- list of line numbers to search for the specified

object

Description

ThisTclscr ipting command can be used in two different ways. First, the command returns aof file names and line numbers for a given object. Second, the command returns a list of obfor a given file and line number.

• -file

The name of the file to be searched

• -line

The line numbers to search in the named file.

Return Value

Error Messages

More Examples

Related Commands



n

fix_backannoComment out simulation constructs.

Modifies VHDL files produced by FPGA Place & Route tools by commenting out simulatioconstructs which LeonardoSpectrum cannot parse.

Related Commands



getlistDisplay the contents of a technology library.

Related Commands



global_set_attributeSet attributes on nets throughout the design hierarchy.

This is useful for the clock_cycle constraint.

Related Commands



global_remove_attributeRemove attributes on nets throughout the design hierarchy.

Related Commands



w

a

groupLevel 3 only.Group a list of instances into one instance of a new view.

Example

Syntax

group <list_of_instances>[ -cell_name <cell_name>][ -view_name <view_name>][ -inst_name <instance_name>]

Arguments• <list_of_instances>

Names of design instances that thegroup command uses to form a single instance of a neview. All instance names must be from the same view.

Options• -cell_name <cell_name>

Name of a new cell to contain the new view. If you omit this option, thegroup commandautomatically generates a name (using the formatxmplr_cell_number ) for the new cell.The cell name must be a simple name.

• -view_name <view_name>

Name of a new view to containlist_of_instances . If you omit this option, the<Command | Filename>group <list_of_instances> command automatically generatesname (using the formatxmplr_view_number ) for the new view. The view name must be asimple name.

• -inst_name <instance_name>

Name of the new instance formed from the instances indicated by the value oflist_of_instances . If you omit this option, thegroup command automatically generatesa name (using the formatxmplr_inst_number ) for the new instance. The instance namemust be a simple name, not a formalized name.

Type Arguments

string <cell_name>, <view_name>, <instance_name>

list <list_of_instances>



an

rkesnew

een

DescriptionThegroup command moves a list of instances, with their connected nets, from one view tonew view in a new cell, thus creating a new level of hierarchy. With this command, you cadefine the name of the instance, the view, and the cell where the new view resides.

Thegroup command is useful to cluster logic that should be optimized as a single view. Foexample, if two instances of two views share much of the same logic or interconnect, it masense to group them into a new level of hierarchy (and to ungroup the hierarchy inside thegroup). This way, subsequent optimization operations can minimize the logic shared betwthe two original views, resulting in smaller or faster designs.

Related Commands

ungroup unfold



ds or

r Tcl

helpGive help on commands, aliases, and variables.

Example

Syntax

help [<search_string>][ -variables ]

Arguments• <search_string>

Regular expression used to search for a full-text informational message about commanvariables that match thesearch_string pattern. If you omit this argument, thehelpcommand displays a one-line description of all commands or variables.

Options• -variables

Displays a one-line description and the current settings for Tcl variables that affectLeonardoSpectrum. If you omit this option, thehelp command displays help informationfor commands and aliases instead.

DescriptionThe help command provides descriptions and usages of LeonardoSpectrum commands ovariables, and current settings of those variables.

More Exampleshelp optimize

This example produces a usage message for theoptimize command.

help *modgen

Type Arguments

string <search_string>



Related Commands

Known Bugs, LimitationsThe help command doesnot provide usage information for true Tcl commands or Tcl scripts.Tcl commands are documented inTcl and the Tk Toolkit,by John Ousterhout, published byAddison-Wesley, ISBN 0-201-63337-X.

alias



ant

mit

a Tcl

list_attributesList attributes on specified objects.

Example

Syntax

list_attributes [<list_of_objects>][ -port ]|[ -net ]|[ -instance ]

Arguments• <list_of_objects>

Names of attributes applied to any objects (library, cell, view, port, net, instance) you wlisted. Object names are case-sensitive, and you can use wildcards. If you omit thisargument, thelist_attributes command lists the attributes of the present design.

Options• -port | -net | -instance

Indicator that the object name(s) refer to ports, nets, or instances, respectively. If you othis argument, thelist_attributes command assumes that the objects inobject_listare instances, unlessobject_list explicitly refers to libraries, cells or views.

DescriptionThe list_attributes command returns a Tcl list of case-insensitive{name value} pairs forthe attributes of indicated objects.

This command is intended to be used in Tcl scripts. You can, however, assign the result tovariable. You can then use the variable in any other Tcl command, for example, aforeach loop.

More Exampleslist_attributes

This example lists the attributes of the present design and their values.

list_attributes .work

This example lists the attributes and their values of the library calledwork .

Type Arguments

list <list_of_objects>



a

list_attributes .work.top.INTERFACE

This example lists the attributes and their values of the viewINTERFACEof the celltop in thelibrary work .

list_attributes -port inport(1)

This example lists the attributes and their values of the portinport(1) in the present design.This command is valid only if the present design points to a view.

list_attributes -inst u*

This example lists the attributes and their values for all instances whose names starts withu.

Related Commands

Known Bugs, LimitationsYou cannot use file I/O redirection with this command, because it returns a Tcl list and nostandard output.

There is no command that returns the value of a single attribute on an object.

list_design



.

ent,

port

list_connectionList objects that are connected to the specified object(s).

Example

Syntax

list_connection <list_of_objects>[ -port ] | [ -net ] | [ -instance ][ -hierarchical ][ -direction <net_direction>]

Arguments• <list_of_objects>

Names of the objects for which the list_connection command lists network connectionsObject names are case-sensitive, and wildcards are accepted.


Indicator that the object name refers to ports, nets, or instances. If you omit this argumthe list_connection command assumes that the objects inlist_of_objects are nets.

• -hierarchical

List all objects connected hierarchically to the ones in<list_of_objects> . Thelist_connection command lists objects at each level of hierarchy below the objects inlist_connection . If you omit this argument, only the connections to objects in one vieware listed.

• -direction <net_direction>

This is for nets only: direction DRIVER DRIVEN.

DescriptionThe list_connection command returns a Tcl list of formal names of connections for theindicated objects. If the object list denotes a port or port-instance, the net connected to the

Type Arguments

string <net_direction>

list <list_of_objects>



snces

d to

iew.

with

or port-instance is returned. If the object list denotes a net, a list of ports and port-instanceconnected to the net is returned. If the object list denotes an instance, a list of all port-instaassociated with the instance is returned.

In a netlist, ports and port-instances can be connected to a net, and nets can be connectemultiple ports and multiple port-instances.

The list_connection command enables you to browse through the netlist, finding netlistconnections step by step. The-hierarchical argument extends the returned list of allconnections from the indicated objects downward through the hierarchy within the same v

More Exampleslist_connection -port clk

This example returns the name of the net to which the portclk is connected in the presentdesign. This example is valid only when the present design is a view.

list_connection -net Net15

This example returns the list of the ports and port-instances to which the netNet15 is connectedin the present design. This example is valid only when the present design is a view.

list_connection -port i145.out

This example returns the name of the net to which the port-instancei145.out is connected, thatis, the portout on the view to which the instancei145 is pointing.

list_connection -instance i*

This example returns the list of the port-instances for all the instances whose names startsan i in the present design.

list_connection -port clk -hier

This example returns the list of nets to which the portclk is connected, all the way downthrough the hierarchy.

Related Commands

Known Bugs, LimitationsYou cannot use file I/O redirection with this command, because it returns a Tcl list and nostandard output.

connectdisconnect

list_design



.es are

list_designReturn a list of objects in a design.

(libraries in the root, cells in a library, views in a cell, etc).

Example

Syntax

list_design [<list_of_designs>][ -ports ]|[ -nets ]|[ -clocks ]||[ -internal_clocks ]|[ -instances ]|[ -references ][ -direction <port_direction>][ -hdl ][ -short ]

Arguments• <list_of_designs>

Name of the library, cell, or view for which you want to retrieve a listing of the contentsYou can use absolute or relative object names, and wildcards are accepted. Object namcase-sensitive. If you omit this argument, the list_design command returns a list of thecontents of the design objects in the present design.

If <list_of_designs> indicates a view, and you omit other arguments, thelist_designcommand uses theinstances argument.

Options• -ports

List all the ports of<list_of_designs> . This argument is valid only if<list_of_designs> is one or more views.

• -nets

List all the nets of<list_of_designs> . This argument is valid only if<list_of_designs> is one or more views.

• -clocks

List all the primary (external) clocks of<list_of_designs> . This argument is valid only if<list_of_designs> is one or more views.

Type Arguments

string <list_of_designs>



|

sts

d by

ason,

cutingtrt.

• -internal_clocks

List all the internal clocks of<list_of_designs> . This argument is valid only if<list_of_designs> is one or more views.

• -instances (default)

List all the instances in<list_of_designs> . This argument is valid only if<list_of_designs> is one or more views.

If <list_of_designs> indicates a view, and you omit other arguments, the <CommandFilename>list_design [<list_of_designs>] command uses theinstances argument.

• -references

List all the instances pointing to<list_of_designs> . This argument is valid only if<list_of_designs> is one or more views.

• -direction

Valid only with -ports option. The-direction option takes the port direction (IN OUT orINOUT) and prints only the ports of given direction. If this option is not provided with-port , all the ports will be printed.

• -hdl

List the design units stored in HDL libraries. If you omit this argument, this command liobjects in the design.

• -short

Display only short path names, not full path names, of design objects.

DescriptionThe list_design command returns a Tcl list of the contents of one or more designs indicatethe<list_of_designs> argument. The returned Tcl list contains formalized names. If the<list_of_designs> is relative, the list returns relative names. If the<list_of_designs> isabsolute, the list returns absolute names.

Although an instance does not contain any objects itself, it does point to a view. For that rethe list_design command returns the formal name of the view if<list_of_designs> itselfindicates an instance.

The command does not operate recursively through a design hierarchy. For example, exelist_design where<list_of_designs> is a library returns only the names of cells in library bunot the names of views within the cells. Use the report_area command to generate a repo



More Examples

Related Commands

Related Variables


You cannot use file I/O redirection with this command, because it returns a Tcl list and nostandard output.

list_design .work list all cells in the library namedwork

list_design -hdl.work

list all entities, packages and modules, analyzed intothe HDL library .work

list_design -port.work.and2.contents

list all ports on the viewcontents of the celland2in the librarywork

list_design . list all libraries in the data base

list_design list the contents of the present design. If the presentdesign is a view, list the instances.

list_design -ports list the ports of the present design. Valid only if thepresent design is a view.

list_design -ref list the references (instances of) the present design;valid only if the present design is a view.

list_design .* list all cells in all libraries

list_design -net list all the nets in the present design; valid only ifpresent design is a view

list_design xyz If the present design is a view, then return the viewname to which the instancexyz is pointing.

list_design -inst x list views contained in the instancex in the presentdesign; valid only if present design is a view

list_design -nets n* list the nets in the present design that start with lettern; valid only if present design is a view

all_clocksall_inputsall_outputs

list_connectionreport_arealist_attributes

list_design_object_separator



list_technologiesReturn a list of technology libraries used in a design.

Example

Syntax

list_technologies [<list_technology>][ -single_level ] --List technology libraries in this level only.

Related Commands



lo2upRename all lower case objects with upper case.

Related Commands



me.

h

the

load_libraryLoad a technology library.

Example

Syntax

load_library [[ -s ][ -t ] <library_name>]

Arguments• <library_name>

Name of a technology library file. The library must have been previously compiled withlGen tool which is part of Exemplar’s XlibCreator Tool Kit.

The library_name may be a simple name, a relative path name, or an absolute path naFor simple names, such asxi4 , the load_library [[-s][-t] <library_name>]command searches the directory$EXEMPLAR/lib for the file,xi4.syn in this example. Iftwo or more vendor libraries have same name, you must use the full pathname for eaclibrary.

Description

This load_library [[-s][-t] <library_name>] command reads a compiled technologylibrary file, then creates a library in the LeonardoSpectrum design database. The name ofcreated library is derived fromlibrary_name . If library_name is not a simple name, theload_library [[-s][-t] <library_name>] command uses just the base of the name toderive a new name.

More ExamplesThe following command loads the file$EXEMPLAR/lib/max7.syn and creates the libraryman7in the design database.

load_library max7

Type Arguments

string <library_name>



Related Commands

Related Variables

optimize

exclude_gatesinput2outputload_library_file_extension

processtempvoltage



file

ed in

frome

write

load_modgenRead a module generator description from a file.

Example

Syntax

load_modgen <modgen_library_name>

Arguments• <modgen_library_name>

Name of a module generator library file. The search path for a module generator libraryis the present working directory, then the$EXEMPLAR/data/modgen directory. Theload_modgen command can also read user-defined module generator library files codVHDL when such modules follow the coding guidelines explained in theLeonardoSpectrum HDL Synthesis Manual.

DescriptionThe load_modgen command loads a module generator library description into theLeonardoSpectrum HDL database. The command resolve_modgen uses the descriptionsthis generic library to resolve instances of arithmetic and relational operators created in thdesign during file read operations or inferred when extracting counters and RAMs with thepre_optimize command. There is only one generic module generator library, namedOPERATORS,assigned in LeonardoSpectrum. Successive loading of module generator library files overexisting ones, operator by operator.

Note: To force old behavior use:_orig_load_modgen

More Examplesload_modgen apex20e

Load the module generator library that Exemplar provides for the Altera Apex family ofdevices.

load_modgen my_modgen.vhd

Load a user-defined module generator library coded in VHDL.

Type Arguments

string <modgen_library_name>



Related Commands

optimizepre_optimize

read



iew

ew

moveMove object(s).

Moves a single view or the full hierarchy under it and appends the suffix to all the moved vnames.

Example

Syntax

move <object1> <object2> | <object1>..<object_n> <object_container>[ -port ]|[ -net ]|[ -instance ][ -hier <suffix_name>]

Arguments• <object1> <object2> | <object1...object_n> <object_container>

Name of source and target objects. The target object can be an object container or a nobject name.object2 , when used, must not exist prior to the move operation.object_container , when used, must exist prior to the move operation.

Options• -port, -net, -instance

Indicates that the source object is a port, a net or an instance, respectively.

• -hier <suffix_name>

This option is only applicable to views. The entire hierarchy under view is moved. Thesuffix is appended to every moved view.

DescriptionThe move command relocates objects in the design database. In many cases, the movecommand effectively renames an object. This is similar to the UNIXmv command.

More ExamplesThere are two examples for themove command: Single View move and Full Hierarchy UnderView Move.

Type Arguments

string <object1>, <object2>, <object_container> <suffix_name>



ame

t

ffix

the

view.

Single View Move

move .work.design.contents .work.design.save

In this example, the move command moves the viewcontents in cell design of the librarywork to the viewsave in the same cell. The result is essentially the same as changing the nof the view.

move .work.top .save_work

In this example, the move command moves the celltop in the librarywork to the librarysave_work .

move -port clk CLK

In this example, the move command moves the portclk to a new portCLK in the present design.The result is the same as changing the port name. This example is valid only if the presendesign is a view.

Full Hierarchy Under View Move

move -hier _move .work.address_decoder.test

This example move command moves the entire hierarchy under view and appends the su“_move” to every view that is moved as follows:

.work.address_decoder.test_move

move -port clk CLK

In this example, the move command moves the portclk to a new portCLK in the present design.The result is essentially the same as changing the port name. This example is valid only ifpresent design is a view.

Related Commands

Known Bugs, LimitationsYou cannot use this command to move ports, nets, or instances across the boundary of a

copycreate

remove



move_nodelayMove the attribute NODELAY from the input port to the input flip-flop.

Related Commands



mes

ot

nooptSet thenooptattribute on the specified objects(s).

Examplenoopt .work.filter_fsm.rtl

This command sets thenoopt attribute toTRUEon the data base object.work.filter_fsm.rtl

Syntax

noopt <object1> <object2>


Name of an instance or view on which to set the noopt attribute. One or more object namay be specified.

Descriptionnoopt is an alias to theNOOPTcommand. This command provides a short hand method forsetting thenooptattribute. Setting anoopt attribute specifies that an instance or view should nbe optimized or changed. However, in contrast todont_touch, lower levels of hierarchy and leafinstances are not protected from optimization or change.


noopt .work.filter_top.rtl

This is the same as entering the followingset_attribute command line:

set_attribute .work.filter_top.rtl -name NOOPT -value TRUE

Related Commands

Related Attributes

dont_touchunnoopt

undont_touch

dont_touch noopt



optimizeOptimize and map a design to a target technology.

Example.

Syntax

optimize [<design_name>][ -target <technology_name>][ -io_target <technology_name>][ -single_level ][ -effort <effort_type>][ -chip ]|[ -macro ][ -area ]|[ -delay ]|[ -auto ][ -pass <pass_nums>]|[-nopass <pass_nums>][ -hierarchy <auto|preserve|flatten>]

Arguments

• <design_name>

Name of the design where theoptimize command performs logic optimization. If you omitthis argument, the command operates on the present design.

Options• -target <technology_name>

Name of the technology library to use when theoptimize command optimizes the design.The technology library named in this argument must be previously loaded by theload_librarycommand.

• -single_level

Optimize only the top-level view of the design. If you omit this option, theoptimizecommand optimizes all views in the design hierarchy in a bottom-up manner.

Type Arguments

string <design_name>, <technology_name>, <effort_type>,<auto|preserve|flatten>

list <pass_nums>



is.

ng

ple

and

• -effort <effort_type> (default)

Level of effort theoptimize command should use during the optimization process. Validvalues are as follows:

• -chip (default)| -macro

The-chip option tells the optimize command to add I/O buffers to top-level view in thedesign. The-macro option prevents the optimize command from adding I/O buffers.

• -auto | -delay | -area (default)

The-area option (the default) tells theoptimize command to minimize area in theoptimized design. The-delay option instructs theoptimize command to minimize delay inthe optimized design. The-auto option instructs theoptimize command to run both areaand delay optimization and automatically retain the best result on a block-by-block bas

• -pass <pass_nums>| -nopass <pass_nums>

The-pass option tells theoptimize command to perform only the indicated optimizationpasses. The-nopass option instructs theoptimize command not to perform the indicatedoptimization passes. LeonardoSpectrum performs a maximum of 4 passes.

You obtain information on optimization passes from prior optimization operations. Durieach optimization of a design, theoptimize command displays the results of eachoptimization pass, together with the ID number of the pass. The Optimize Report Examshows the results of the commandoptimize -target xi4 on a design with one level ofhierarchy.

• -hierarchy <auto|preserve|flatten>

The hierarchy manipulation option is available from the interactive command line shellbatch mode (DOS or UNIX environments).

• auto (auto_dissolve) is selected by default. Logic is equated to 2-input NANDgates, and hierarchy is dissolved according to the following rules:

i. FPGA/CPLD auto_dissolve limit is 50 gates (default).

ii. ASIC auto_dissolve limit is 30 gates (default).

remap Performs some local optimization and technology mapping to thetarget technology.

quick Performs one pass of optimization and technology mapping. This isa fast optimization effort that would usually be used at thebeginning of the design cycle.

standard(default)

Performs multiple passes of optimization and technology mapping.Applies different strategies of optimization, and usually achievesbetter results than thequick effort, but takes more time.



.d

enstem

.

e

as

s on

mping

of

aschy,

iii. There is a maximum system limit of gates that can be dissolved in a moduleThis system limit cannot be modified by a user switch. If this limit is exceedethenauto_dissolve is not completed. Theauto_dissolve dissolves instancesin a context sensitive manner. If a module is instantiated more than once, ththe instance is dissolved only if total number of gates does not exceed the sylimit.

• If preserve is selected, then hierarchy is not dissolved during optimization.

• If flatten is selected, then the entire design hierarchy is flattened (dissolved)

In addition,auto_dissolve is now the default for the optimization command in both theinteractive command line shell and in batch mode. Hierarchy can be preserved with th"-hierarchy_preserve " option in batch mode; and with-hierarchy <preserve> optionon the interactive command line shell.

Note: Typing the-hierarchy auto is an option, sinceauto is the default.

Note FPGA/CPLD: You can use a variable to change the number of gates to be dissolvedfollows:

set auto_dissolve_limit (600)

optimize -ta apex20e-hierarchy auto

optimize -ta apex20e-hierarchy auto

Note: You can preserve the entire design hierarchy with:optimize -ta xi4 -hierarchypreserve

Note: You can flatten (dissolve) the entire design hierarchy with:

optimize -ta apex20e -hierarchy flatten

DescriptionTheoptimize command performs technology-specific logic optimization and technologymapping. You control optimization and mapping efforts by setting variables and constraintthe design boundaries, and indicating area and delay options.

Optimization and mapping results also depend on design rules. For example, the maximucapacitance allowed on a single driver as defined in a target technology library effects mapresults.

The default optimization action is to process each level of hierarchy, starting at the bottomthe hierarchy and optimizing one view at a time. Theoptimize command allows you todissolve boundaries in some views and to group elements into new levels of hierarchy.

Functional Description of Boundary Optimization

The inputs to the hierarchical module in a hierarchical design may contain constants suchTRUE/FALSE. By propagating the constants across the boundary into the low level hierarthe design can be optimized more effectively. Similarly, unused outputs of a hierarchical



d to

dontext

rts or

ogic

d

tingation

ign

not

module can be disconnected and common nets connecting to multiple ports can be mergesingle net. This propagation occurs in both upward and downward directions. By default,hierarchical modules are checked for usage at the boundary, then the modules are groupebased on the common usage for boundary optimization. The created views are given the cnames based on the higher level cell, instance, and the view name:<cellname_instancename_viewname>

The user may find that some of the lower level hierarchical modules have unused output ponets that are merged together. Disable this function with:set no_boundary_optimizationTRUE

Optimization Sequence

1. Theoptimize command removes unused logic, and extracts and shares common lamong design elements, and extracts counters, rams and decoders.

2. Theoptimize command performs a series of optimizations based on algorithms anheuristics specific to the target technology.

3. Theoptimize command maps the design to the target technology.

4. Theoptimize command performs a design rule check.

User Control

You control optimization and mapping efforts by setting LeonardoSpectrum variables, setconstraints on the design boundaries, and indicating area and timing goals for the optimizand mapping. For more information refer to theVariablessection in this manual. Boundaryconstraints include the following:

• timing constraints on input and output signals

• input drive and capacitance

• output load

• definition of clocking schemes

Design boundary information is useful in optimizing the timing of critical sections in the desduring technology mapping.

You can also direct the optimize command not to optimize certain views in a hierarchicaldesign by adding thenoopt attribute to the views. Theoptimize command treats such viewsas black boxes for optimization purposes. Similarly, you can direct the optimize commandto optimize and/or delete certain signals by adding thepreserve_signal attribute to theappropriate nets.Note: Refer topreserve_driverattribute.



as

for

for

Design Rules

Design rules, specified in a target technology library by a vendor, also affect optimizationefforts. Design rules address design characteristics relevant to physical design tools, suchplace-and-route tools.

More Examplesoptimize -ta apex20e -effort standard -delay

This command optimizes the view pointed to by the present design. The design is targetedthe Altera Apex technology library. Theoptimize command optimizes the view to minimizetiming delays and uses a standard optimization effort.

optimize -ta flex10 -pass 4

This command optimizes the view pointed to by the present design. The design is targetedthe FLEX 10k technology library. The optimize command performs only optimization passnumber 4.

Related Commands

Related Variables

load_librarygroup

ungrouppre_optimize

area_weightauto_dissolve_limitcheck_complex_ioscomplex_iosdelay_break_loopsdelay_weightextract_reduction_opsflex_lock_lcellsinversion_prefixmaxareamaxdlymax_fanin

max_lock_lcellsmax_transitionmulti_driver_drc_resolvingno_boundary_optimizationnowire_tableoperating_conditionoptimize_drc_resolvingpackageparttransformationstristate_mapwire_load_librarywire_tree



nt,

ally

e

optimize_timingPerform critical path timing optimization on a design.

Exampleoptimize_timing -through out1

Optimizes all critical paths in the present design that end at signalout1 .

Syntax

optimize_timing [<design_name>][ -through <node_lists>][ -force ][ -single_level ]


Name of the view in the design for which to optimize the timing. If you omit this argumethe command operates on the present design.

Options• -through <node_list>

A list of instances, ports, or nets. Given this list, theoptimize_timing command tries toimprove the timing along signal paths on which the indicated nodes participate.

• -force

Makes theoptimize_timing command use the longest paths as the basis of a timingconstraint. Useful when no timing constraints are specified, but explicit constraints usuyield better quality of results.

• -single_level

Performs timing optimization only at the top level of hierarchy. If you omit this option, thoptimize_timing command traverses the entire design hierarchy.

Type Arguments


list <node_list>



s the

a

r a

s:

Descriptionoptimize_timing examines most critical paths and tries to improve thearrival_time at theend of each. This command is more effective if the user indicates timing constraints, such abehavior of clock signals, the arrival time of primary input signals, and the required time onprimary output signals. Theoptimize_timing command infers timing constraints from theseparameters.

You specify clocks by defining the clock cycle, pulse width, and clock offset. The followingfigure graphically defines these concepts.

| <- width -> || ___________ || | | || _____________| |_________________|| <-- offset --> || <-- cycle ------------------------------>|

Arrival times and required times are specified in nanoseconds. These times are relative toreference point, usually a clock edge.

Theoptimize_timing command enables you to define clocks and arrival times within eitheVHDL source file or the LeonardoSpectrum command-line interface. An example VHDLspecifications is as follows:

ATTRIBUTE CLOCK_CYCLE OF clock:SIGNAL is 20ns;

ATTRIBUTE CLOCK_OFFSET OF clock:SIGNAL is 5ns;

ATTRIBUTE PULSE_WIDTH OF clock:SIGNAL is 10ns;

ATTRIBUTE ARRIVAL_TIME OF inputa:SIGNAL is 3ns;

Using the LeonardoSpectrum interface, you would express this same information as follow

CLOCK_CYCLE 20 clock

CLOCK_OFFSET 5 clock

PULSE_WIDTH 10 clock

ARRIVAL_TIME 3 inputa



More ExamplesThe following command optimizes the timing of the present design and requires theoptimize_timing command to use the longest path as a timing constraint.

optimize_timing -force

The following command optimizes all critical paths in the present design that end at signalout1 .

optimize_timing -through out1

Related Commands

Related Variables

ungroupgroup

set_attribute

constraints_save_only_multicyclemaxareamaxdlymap_sync_regmax_fanout_loadmax_transition

multi_driver_drc_resolvingnowire_tableoptimize_timing_cpu_limitwire_load_librarywire_tree



place_and_routePlace and Route the design using the Vendor-supplied tools.

Example

Syntaxplace_and_route <edif input file> -target <string>

[ -gui ][ -exe_path <string>]

[ -part <string>]

[ -speed_grade <string>]

[ -ba_format format_name ]

[ -n ][ -view_placement ][ -ncf_file ]

[ -m1_pr_standard ]

[ -m1_pr_high ]

[ -m1_functional_sim ]

[ -m1_preroute_timing ]

[ -m1_pack_iobs ]

[ -m1_no_bits ]

[ -m1_no_backanno ]

[ -m1_no_ngm ]

[ -m1_bitgen_cmd_file <file>]

[ -m1_user_constraint_file <file>]

[ -m1_guide_file <file>]

[ -m1_guide_mode <file>]

[ -m1_guide_mode_leverage <file>]

[ -max_acf_only ]

[ -max_no_acf ]

[ -max_ta_delay ]

[ -max_ta_setup ]

[ -max_ta_reg ]

[ -max_area ]|[ -max_delay ]

[ -max_auto_fast_io ]

[ -max_auto_register_packing ]

[ -max_auto_implement_in_eab ]

[ -max_no_cliques ]

[ -max_no_pins ]

[ -max_no_timing ]

[ -quartus_compile ]

[ -quartus_setup ]

[ -quartus_ba_sim ]

[ -quartus_ba_timing ]

Type Arguments



ied,

Arguments• <edif_input_file>

This required argument is the name of the edit input file. If a full pathname is not specifthen LeonardoSpectrum searches the working directory for the file with this relative filename.

• -target <string>

This required argument is the name of the target technology for place and route.

Standard Options• -gui

Bring up the Graphics User Interface instead of using the interactive shell mode

• -exe_path <string>

The full pathname to the location of the place and route executable.

• -part

Name of the part in the specified technology.

• -speed_grade

Name of the speedgrade in the specified technology.

• -ba_formatVHDL|Verilog|EDIF

Specify whether the back annotation format should be VHDL, Verilog, or EDIF.

• -view_placement

• -ncf_file <file>

Altera MAX+PLUS II Options

• -max_acf_only

Only generate acf, don’t run the MAX+PLUS II compiler.

• -max_no_acf

Suppress the generation of the acf file.

• -max_ta_delay

MAX+PLUS II shows input to output delays.




• -max_ta_setup

MAX+PLUS II shows setup hold matrix.

• -max_ta_reg

MAX+PLUS II shows register performance.

• -max_area | -max_delay

MAX+PLUS II optimized for area (the default) or minimum delay.

• -max_auto_fast_io

MAX+PLUS II place and route option.

• -max_auto_register_packing


• -max_auto_implement_in_eab


• -max_no_cliques

• -max_no_pins

• -max_no_timing

Altera Quartus Options• -quartus_compile

• -quartus_setup

• -quartus_ba_sim

• -quartus_ba_timing

Description



pop_designPop the specified number of levels out of the design stack.

Related Commands



’s

t,

r the

pre_optimizeDo constant propagation and other pre-optimization on the design.

Examplepre_optimize -common_logic -unused_logic -extract

This command performs all pre-optimization operations on all levels of the present designhierarchy.

Syntax

pre_optimize [<design_name>][ -common_logic ][ -unused_logic ][ -extract ][ -xor_comparator_optimize ][ -single_level ][ -boundary ]


Name of the view to perform preliminary logic optimization on. If you omit this argumenthe command operates on the present design.

Options• -common_logic

Share operators and primitives that have common inputs.

• -unused_logic

Remove logic that does not affect output signals from the design.

• -extract

Recognize counters, decoders, and RAMs from generic logic. New views are created forecognized logic.

• -xor_comparator_optimize

Optimizes wide XORs and comparators by determining common sub-expressions.

Type Arguments




n

• -single_level

Perform preliminary logic optimization only at the top level of hierarchy. If you omit thisoption, the pre_optimize command traverses the entire design hierarchy.

Description

Thepre_optimize command performs technology-independent logic optimization, such asresource sharing, removal of unused logic and extraction of data path elements, such ascounters, decoders, and RAMs.

LeonardoSpectrum always executes thepre_optimize command as part of theoptimizecommand, so you rarely need to use thepre_optimize command independently. One casewhere you will use it is to investigate the design before going through a lengthy optimizatioand mapping process with theoptimizecommand.

More Examples

Related Commands

Related Variables

optimize

extract_counterextract_decoder

extract_ramextract_rom



s set to

resent

present_designPrint or change the present design.

Example

Syntax

present_design [<new_present_design_name>]

Arguments• <new_present_design_name>

Name of a design that identifies the top of a design hierarchy and on whichLeonardoSpectrum performs actions. If you omit this argument, thepresent_designcommand returns the setting of the present design.

DescriptionPresent design is a term to determine the design on which LeonardoSpectrum performsdesign-related operations. The default present design when you start LeonardoSpectrum ithe top list of libraries in the LeonardoSpectrum design database, called theroot. Once you readin a design from a design file, however, the present design is set to the top-level view asdescribed in that file.

You use the present_design command to change the present design explicitly or list the pdesign. <new_present_design_name> can only be set on the root, a library, a cell or a view.

Type Arguments

string <new_present_design_name>



print_design_stackPrint out the design stack for informational purposes.

Example

print_design_stack -v

Syntax

print_design_stack[ -v ]

This is useful with the push_design and pop_design scripts.

Options• -v

Print the design stack in verbose mode.

Description

Related Commands



n the

push_designPush into the design stack while preserving the ability to pop back to the current position istack.

Example

push_design

Syntax

push_design

Description

Related Commands

pop_designpush_design

print_design_stack



puts_logPut a string to a stdout and log file.

Example

puts_log -v

Syntax

puts_log[ -nonewline ]

Options• -nonewline

Do not add a new line.

Description

Related Commands



s and

he

.

readRead a file and create an in-memory design database.

Example

Syntax

read <file_name(s)>[ -format <format_name>][ -dont_elaborate ][ -design <design_name>][ -architecture <architecture_name>][ -work <library_name>][ -parameters <parameters_list>]|[ -generics <generics_list>][ -technology <technology_name>]

Arguments• <file_name(s)>

Name of the input file or list of files.file_name(s) can be local filenames, relative pathnames, or absolute path names.

If multiple filenames are specified, use the Tcl list format, eg{name1 name2} . If filenameswith spaces are specified, wrap the filename with spaces in either quotes or curly bracewrap the list of one or more filename in curly braces, eg{“filename with spaces”} or{{filename with spaces}} or {“first filename with spaces” {second filenamewith spaces} normal filename} .

Example:read {“my files/file1.vhd” “other files/file2.vhd”}

Always use the forward slash character (/ ) to separate directory names in a path, even on tPC. LeonardoSpectrum interprets the back-slash character (\ ) as a Tcl escape character.


The format of the input file. Valid values are as follows: edif, sdf, verilog, vhdl, and xdb

Type Arguments

string <format_name>, <design_name>, <library_name>, <architecture_name><technology_name>

list <file_name(s)>, <generics_list>, <parameters_list>



e

n.

in

file.

If you omit this argument, theread command attempts to determine the file format from thfilename extension, as shown in the following table.

If the read command cannot determine the file format, it prompts you for the informatio

• -dont_elaborate

Analyze input file only; do not elaborate. Valid only for HDL-format files. Using thisargument is equivalent to using the commandapply_rename_rules<file_name> .


Specify top level design name to be read.


Store designs in the input file inlibrary_name instead of thework library. This argument isonly effective for VHDL and Verilog formats, where the library of a design is not definedthe file itself.

• -technology <technology_name>

Specify a target technology to guide analysis.

Descriptionread copies of a design from a file into the LeonardoSpectrum design data base.

If no errors occur, the read command sets the present design to the top-level design in theWhich design in the input file is the top-level design depends on the format of the file.


.edf, .edif, .eds DIF

.sdf SDF

.v, .verilog Verilog

.vhd, .vhdl VHDL

.xdb XDB

EDIF View defined by the EDIF 'design' construct

VHDL Last architecture of the last entity in the file

Verilog First module in the file



sign.re,

dyn and

her

nect

,

p ofring

ed

is

n.

Since SDF defines only timing information, the read command does not set the present deInstead, the tool annotates the timing information in the file on the present design. Therefomake sure that present_design is set to the appropriate existing design.

For all formats except SDF, if a design with the same name as the design being read alreaexists in the database, the read command replaces the existing design with the new versioissues a warning message. If there were already references to the existing design from otdesigns in the database, the read command links the port references to the new designautomatically. If ports in the existing design are missing in the new design, the tool disconthe references to those ports and issues a warning.

If the file contains references to technology cells, make sure to load the appropriate library(using the load_library command) first. Otherwise,read creates black boxes for all these cellsand area, timing and functional information is not present.

XDB Designs Only

The output file is saved in a format that can be read back into LeonardoSpectrum withoutprocessing the netlist to remove technology-specific information. XDB writes a binary dumyour hierarchical database to a file. You can read this file back into LeonardoSpectrum. Duthe write command the library, cell and view objects were saved. The view includes nets,instances, attributes. Separate nets, ports, instances are low level objects and are not savduring write.

Note: During read, the necessary libraries for the design must be read in before the designread in. The read command reads the file containing information in XDB format andreconstructs the design database. The technology libraries are required during thereconstruction.

Limitations

The read command reads VHDL and Verilog designs in two steps: analysis and elaboratioread filename for VHDL or Verilog, therefore, is equivalent to the following two separatecommands:

apply_rename_rulesfilename

extract_best_passes

Theread command can operate only on VHDL or Verilog designs that meet the followingcriteria:

The design is described in a single file.

The top-level design does not have uninitialized generics or parameters.

The top-level design is either the last design in the file (VHDL) or the first (Verilog).

In all other cases, you need to run the analyze and elaborate commands separately.

XDB XDB is a binary dump of the hierarchical designdatabase. The netlist is saved in the original form.



es(s)hicalandn,do

le

how

reade

VHDL and Verilog Designs Only

The read command file(s) are analyzed and then the top level design is elaborated. Duringelaboration only the architectures/modules in the lower level of hierarchy - present in the fil- would be elaborated. Any other lower level designs are either picked up from the hierarcdata base or a black box is created. This is for bottom up design methodology. If you readoptimize the lower level of hierarchy first and then read a file containing the top level desigthe lower level designs are untouched and only the top level design is elaborated. You canoptimization on the top level design only. Read in a design which is distributed over multipfiles with ‘read {file names}’. You can read the files individually by analyzing all of the filesand then doing elaborate on the top level design.

ScriptsThe script is available from the new Utilities menu, and includes a description on when andthe script is used. A brief description follows:

auto_read automatically does needed processing for technology netlists in addition to thecommand, including setting of variable values. This script is invoked automatically from thRead dialog when "Do Automatic Processing" is checked.

Note this script replaces theread_altera script available with previous releases ofLeonardoSpectrum.

Related Commands

Related Variables

apply_rename_rules extract_best_passes

edif_function_propertyencoding, full_casehdl_array_name_stylehdl_integer_name_stylehdl_record_name_styleparallel_casepreserve_dangling_net

sdf_hierarchical_namessdf_read_suppress_warningsuse_dffenableviewlogic_vhdlvhdl_87



read_constraintsRead in a constraint file.

Print out the design stack for informational purposes.

Example

read_constraints filter_top.ctr

Syntax

read_constraints [<file_name>]

Arguments• <file_name>

Name of the constraint file to be read.

Description

This command reads the specified constraint file and applies the constraints to thepresent_design.

Related Commands



recompose_flexRecompose LUTs from post place and route.

Example

recompose_luts -source apex20

Syntax

recompose_luts -source <source_technology>

Arguments• -source<source_technology>

Name of the source technology.

Description

Related Commands



s are

mit

from

If an

removeRemove object(s) from the in-memory design database.

Example

Syntax

remove <object_name>

[ -port ]|[ -net ]|[ -instance ]

[ -hdl ]

Arguments• <object_list>

List of names of objects to be removed. Object names are case sensitive and wildcardaccepted

Options• -port, -net, -instance

Indicator that the object name(s) refer to ports, nets or instances, respectively. If you othis argument, theremove command assumes thatobject_lis t refers to instances unlessobject_list refers to libraries, cells or views.

• -hdl

Remove objects (libraries, packages, entities, architectures, configurations, modules)the hdl database, rather than objects from the design database.

Description

Remove objects (libraries, cells, views, ports, nets, instances) from the design data base.object does not exist, an error is issued. When a port, net or instance is removed, anyconnections to it are removed as well.

More Examplesremove .work

Remove the entire librarywork from the design database

Type Arguments

list <object_list>



o.

to

ng

remove -hdl .ieee.std_logic_1164

Remove the VHDLieee packagestd_logic_1164 from the hdl data base.

remove -port P

Remove portP in the present design, and disconnect it from any net it might be connected tOnly valid if the present design is a view.

Related Commands

Known Bugs, LimitationsTheremove command will refuse to remove the present design. For this reason, make surealways specify a full name (starting with.) when a library, cell or view needs to be removed.You can change the present design with the present_design command beforehand.

Theremove command will refuse to remove a view if there are still references to it. A warnimessage will be issued.

createmovecopy

connectdisconnect



s are

it this

case

remove_attributeRemove an attribute from object(s).

Exampleremove_attribute -port clk -name PIN_NUMBER

Remove attributePIN_NUMBERfrom portclk of the present design. Only valid if the presentdesign is a view.

Syntax

remove_attribute [<object_list>][ -port ]|[ -net ]|[ -instance ][ -name <attribute_name>][ -global ]

Arguments• <object_list>

List of names of objects to be removed. Object names are case sensitive and wildcardaccepted


Indicator that the object names refer to ports, nets or instances, respectively. If you omargument, theremove_attribute command assumes thatobject_list refers to instancesunlessobject_list refers to libraries, cells or views.

• -name

Name of the attribute to be removed. Wildcards are not accepted. Attribute names areinsensitive.

• -global

Remove attributes from nets globally (all levels of hierarchy).

Type Arguments

string <attribute_name>

list <object_list>



DescriptionRemove an attribute from an object in the design database.

More Examplesremove_attribute -port { in1 bus_a(*) } -name ARRIVAL_TIME

Remove the attributeARRIVAL_TIME from the portsin1 and all the ports of the bundlebus_a , ofthe present design. Only valid if the present design is a view.

remove_attribute -name NOOPT

Remove the attributeNOOPTfrom the present design.

Related Commands

list_attributes set_attribute



remove_clockRemove the clock information from object(s).

Example

Syntax

remove_clock -name <object_name>[ -port ] | [ -net ][ -type <string>]

Arguments

Options

Related Commands

Type Arguments

string -name <string> Name of the object.

string -type <string> Type of attribute (default) - remove even iftype not specified.



remove_rename_rulesetRemove a ruleset for object renaming.

Example

Syntax

remove_rename_ruleset <ruleset_name>

Arguments

• <ruleset_name>

Remove rulesetruleset_name for object renaming. Ruleset was previously created withcreate_rename_ruleset .

Related Commands

add_rename_rule,apply_rename_rulescreate_rename_ruleset




nt,

ands a

report_areaReport the accumulated area of the present design.

Example

Syntax

report_area [<report_file_name>][ -cell_usage ][ -hierarchy ][ -all_leafs ]

Arguments• <report_file_name>

Name of the output file in which to write the design area report. If you omit this argumethe report goes to standard output screen. This is a string type of argument.

Options• -cell_usage

report cell usage per instance in design.

• -hierarchy

report all levels of hierarchy separately.

• -all_leafs

report on all leaf cells, including black boxes.

DescriptionThereport_area command is a general-purpose area reporting routine.

For a technology-independent (not optimized) design, thereport_area -all_leafs commandgives an overview of the complexity of the design prior to technology mapping. The reportincludes the total number of primitives (AND, OR) and operators (add, subtract, multiply),a count of the black boxes. On a mapped (optimized) design, the same command producereport that includes technology-specific area information.

Type Arguments

string <report_file_name>



Related Commands

Related Variables

decompose_lutsoptimize

pre_optimizeread, write

report_area_format_style



andis a

s are

are

nets.

report_constraintsList user-specified constraints on any object.

Example

Syntax

report_constraints [<design_name>][ -port ][ -net ][ -hierarchy ]


Name of the design for which to report constraints. If you omit this argument, the commoperates on the present design. This argument is valid only if the design is a view. Thisstring type of argument.

Options• -port

Report constraints on ports only. If you omit this argument, both port and net constraintreported

• -net

Report constraints of nets only. If you omit this argument, both port and net constraintsreported.

• -hierarchy

Report constraints on all levels of hierarchy in the design. If you omit this option, onlyconstraints at the top level of hierarchy are reported.

DescriptionReport constraints on a design. Design constraints are modeled as attributes on ports andYou should use the following methods to set constraints:

• Use theset_attribute command.

Type Arguments




• Use a design constraint Tcl script from theexemplar.ini file.

• Use the constraint editor from the GUI.

• Set attributes on ports in VHDL or Verilog design source code.

More Examples

LEONARDO: report_constraints [present_design]-- Printing User constraints for view .work.prep1_2.top_level

clk CLOCK_CYCLE 20clk CLOCK_OFFSET 5rst ARRIVAL_TIME 2q(7) REQUIRED_TIME 15q(6) REQUIRED_TIME 15q(5) REQUIRED_TIME 15q(4) REQUIRED_TIME 15q(3) REQUIRED_TIME 15q(2) REQUIRED_TIME 15q(1) REQUIRED_TIME 15q(1) REQUIRED_TIME 15q(0) REQUIRED_TIME 15

Related Commands

list_attributes set_attribute



eport

report_delayReport timing information about the design.

Example

Syntax

report_delay [<report_file_name>][ -num_paths <number>][ -longest_path ][ -end_points ][ -start_points ][ -clock_frequency ][ -critical_paths ][ -no_io_terminals ][ -no_internal_terminals ][ -show_input_pins ][ -show_nets ][ -through <node_list>][ -from <start_points>][ -to <end_points>][ -not_through <node_list>][ -show_schematic <number>]

Arguments

• <report_file_name>

Name of file in which to write the delay report.report_file_name can be a local filename, a relative path name, or an absolute path name. If you omit this argument, the rappears on the standard output screen.

Type Arguments

string <report_file_name>

list <node_list>, <start_points>, <end_points>

integer <number>



n

te in

aths

o the

Options• -num_paths<number>

Number of paths to report. Thereport_delay command reports on paths in descendingorder of criticality. If you omit this argument, thereport_delay command reports 10critical paths.

• -longest_path

Sort paths in the design by length, report the longest path first, and ignore criticality.

• -end_points

Reports slack, arrival and required times at end points only. This option may be used icombination with-start_points and/or -critical_paths . By default, report_delayreports on critical paths only. This default is identical to the-critical_paths option.

• -start_points

Reports slack, arrival and required times at start points only.

• -critical_paths

Reports critical paths only.

• -no_io_terminals

Report only those paths that terminate in inputs to registers, ignoring paths that terminadesign outputs or primary outputs.

• -no_internal_terminals

Report only those paths that terminate in design outputs or primary outputs, ignoring pthat terminate in input to registers.

• -show_input_pins

Include the input pins of gates in the report.

• -show_nets

Include in the report the names of nets being driven by the output of gates in addition toutput pin names of gates.

• -through <node_list>

Report only those paths through ports and instances indicated bynode_list .

• -not_through<node_list>

Do not report paths through ports and instances indicated bynode_list .

• -from <start_points>

Report only those paths that originate at the indicated input ports or register outputs<start_points> .



e

rt

• -to <end_points>

Report only those paths that terminate at the indicated input ports or register outputs(end_points ).

• -show_schematic<number>

Number of critical path schematics to generate. This is an integer value.

Descriptionreport_delay reports the timing status of a design. The command creates a list of criticalpaths and, by default, displays them from most critical to least critical. (A critical path is onthat has a slack of 0 nanoseconds or less.)

More ExamplesThe following command example reports the most critical path in a given design. The repogenerated by the command follows the command example.

report_delay -num 1Critical Path Report

Critical path #1, (unconstrained path)NAME GATE ARRIVAL LOAD---------------------------------------------------------------------------clock information not specifieddelay thru clock network 0.0 (ideal)

XMPLR_INST_17/I1/Q FD 3.00 dn 0.0modgen_0/XMPLR_NET_8/O F3_LUT 7.50 dn 0.0XMPLR_NET_8/O F3_LUT 12.00 dn 0.0XMPLR_NET_9/O F4_LUT 16.50 dn 0.0XMPLR_NET_155/O H3_LUT 19.00 dn 0.0nxstate(1)/O F4_LUT 23.50 dn 0.0XMPLR_INST_15/I1/D FD 23.50 dn 0.0data arrival time 23.50

data required time not specified---------------------------------------------------------------------------data required time not specifieddata arrival time 23.50unconstrained path



Related Commands

Related Variables


report_delay treats all designs as if they are flat. If a design is hierarchical, the commandreports the critical paths through the hierarchy, without regard to hierarchy boundaries.

optimize,optimize_timing

report_area

constraints_save_only_multicyclemulti_driver_drc_resolvingnowire_tablepropagate_clock_delayreport_delay_analysis_modereport_delay_arrival_threshold

report_delay_arrival_thresholdreport_delay_detailreport_delay_format_stylereport_delay_slack_thresholdwire_treewire_load_library



report_rename_rulesReport the loaded rename ruleset information.

Example

report_rename_rules ruleset1

Syntax

report_rename_rules [<ruleset_name>]


Report the loaded rename ruleset information.

Description

Related Commands

add_rename_ruleapply_rename_rules

create_rename_rulesetremove_rename_ruleset,



report_wire_tablesReport information about wire tables.

Example

report_wire_tables

Syntaxreport_wire_tables [<report_file_name>]

[ -library <list>][ -summary ][ -detail ]

Arguments

• <report_file_name>]

Options• -library <list>

Report wire tables in the specified technology library(s)

• -summary

Report only a summary of the wire table(s).

• -detail

Report everything in the wire table(s).

Related Commands



restore_project_scriptRestore a project script file.

Example

restore_project_script

Syntax

restore_project_script [<file_name>][ -nodesign ]

Arguments• <file_name>]

Options• -nodesign

Do not restore the design.

Related Commands



selectSelect a list of objects.

Example

Syntaxselect [<objects>]-- objects to select

[ -linenum [<list >][ - db ][ - schview ][ - renoir ][ - edit[ - clear

Arguments• <objects

List of object to select.

Options

• -linenum

A list of file names and line numbers to select

• -db

Brings up a Design Browser hierarchy view of the selected objects

• -schview

Brings up a schematic view of the selected objects

• -renoir

Brings up a Renoir schematic of the selected objects

• -edit

Brings up an edit window on the associated file(s)

• -clear

Unselects all selected objects.

DescriptionThisTclscr ipting com m and can ber un i n oneoft w o w ays.Thef irstw ay al low syou t o sel ectalistofobj ect s.Thesecond al low syou t o sel ectobj ect sassoci ated w ith al istofl ineand f ilenum bers(Seefile_l ine_sear ch).Thesel ectcom m andby def aul tdoesnotst artanyw i ndows.So,



unl essyou haveal ready st arted acl ient,you m ustuset heappr opriateswitch t o bring thew indow up.

Return Value

Error Messages

More Examples

Related Commands



set_altera_eqnReplace the following Altera variables:edif_eqn_and , edif_eqn_not ,edif_eqn_not_is_prefix , edif_eqn_or , edif_function_property .

Related Commands



e

is

sitive.

set_attributeCreate or set an attribute on an object(s).

Example

set_attribute -port {in1 bus_a(*)} -name ARRIVAL_TIME -value 1.3

Set the attributeARRIVAL_TIME to 1.3 (ns) for the portin1 and all the ports of the bundlebus_aof the present design. Valid only if the present design is a view. This is an alternative to thARRIVAL_TIME script command

Syntaxset_attribute [<object_name>]

[ -port ]|[ -net ]|[ -instance ][ -global ][ -name <attribute_name>][ -type <attribute_type>][ -value <attribute_value>]

Arguments• <object_name>

Name of the object (library, cell, view, port, net or instance) for which theset_attributecommand sets an attribute value. Wildcards and lists are accepted. If you omit thisargument, theset_attribute command operates on the present design.


Indicator thatobject_name refers to a port, net, or an instance, respectively. If you omit thargument, theset_attribute command assumes thatobject_name refers to an instanceunlessobject_name refers to a library, cell or view.

• -global

Apply this attribute to nets globally (all levels of hierarchy).

• -name <attr_name>

Simple name for the attribute whose value is being set. Attribute names are case-insen

Type Arguments

string <object_name>, <attr_name>, <attr_type>, <attr_value>

list <object_name>



e

is

• -type <attr_type>

Data type of the attribute whose value is being set. Valid values depend on the attributindicated with the-name option.

• -value <attr_value>

Alphanumeric string to assign to named attribute.

DescriptionTheset_attribute command assigns a value to an attribute on an object in the designdatabase.

If the object already has an attribute with the same name as that indicated by the-name option,theset_attribute command overwrites the existing value with the newly specified value.Although a user can define and attach any named attribute to a design object,LeonardoSpectrum only responds to certain attributes. AList of Pre-Defined Attributesisprovided starting on page2-5.

More Examples

set_attribute -port clk -name PIN_NUMBER -value "P14"

Set attributePIN_NUMBERon portclk of the present design to the stringP14. Valid only if thepresent design is a view. This is an alternative to thePIN_NUMBERscript command.

set_attribute .work -name Version -value "My library version 3.0"

Set the attributeVersion on the librarywork to the stringMy library version 3.0 .

set_attribute -name NOOPT -value TRUE

Set attributeNOOPTon the present design toTRUE. The present design could be anything. Thisan alternative to theNOOPTscript command.

Related Commands

list_attributes remove_attribute



tance.

set_clockCreate or set clock information on an object(s).

Example

Syntaxset_clock [ -port ]|[ -net ] -name <string>

Arguments• [-port] | [-net]

Indicates that the object is a port or a net. If omitted, the object is assumed to be an ins

• -name <string>

Name of the object

Options• [-type]

Related Commands

Type Arguments

string [-clock_cycle <string>] clock cycle

string [-clock_offset <string>] clock offset

string [-pulse_width <string>] pulse width

string -name <string> name of object

string [-type <string> type of attribute (default)



set_multicycle_pathConstrain a path that requires more than one clock cycle.

Example

Syntaxset_multicycle_path <-value number> < -from start_points> < -to end_points>

[ -setup ][ -hold ][ -rise ][ -fall ][ -src_clk ][ -dest_clk ][ -unset ][ -to <list>][ -from <list>][ value <integer>

Arguments• <-value number>

This is the number of clock cycles needed to account for the path delay.

• <-from start_points>

v is a list of names of instances and ports at the path start point.

• <-to end_points>

end_points is a list of names of instances and ports at the path end point.

Options• -setup, -hold

Specifies the use of the<-value number> of clock cycles.-setup is for start point numberof clock cycles.-hold is for end point number of clock cycles. The default is-setup .

Type Arguments

list <start_points>, <end_points> <to> <from>

integer <number> <value>



t:

• -rise, -fall

Indicates the effect of<-value number> on delays.-rise specifies that rising path delaysare affected at path end point.-fall indicates a falling value at the path end point. Defaulboth rising and falling delays are affected.

• -value

Specifies number of cycles.

• -to

Specifies target of node list.

• -from

Specifies source of node list.

• -src_clk, -dest_clk

Indicates if the<-value number> information is relative to the start clock or to the endclock. -src_clk is equivalent to the input of the path.-dest_clk is equivalent to the outputof the path.

• -unset

-unset removes multicycle constraints from path.

Note: The register-to-register constraint does not work withset_multicycle_path . Youmust set the clock to make theset_multicycle_path active.

Related Commands



show_var_settingsDisplay all variable settings made in a session.

Related Commands



unaliasRemove an alias.

Example

Syntaxunalias <alias_name>

Arguments

• <alias_name>

Alias to be removed. This is a string type of argument.

DescriptionThe unalias command removes an alias previously created with the alias command.

More Examplesunalias dl

Removes the alias definition ofdl .

Related Commands

Type Arguments

string <alias_name>

alias help



ore

d

undont_touchRemove thedont_touchattribute from the specified objects(s).

Exampleundont_touch .work.filter_top.rtl

This command removes thedont_touch attribute from the data base object.work.filter_fsm.rtl

Syntax

undont_touch <object1> <object2>


Name of an instance or view from which to remove the dont_touch attribute. One or mobject names may be specified.

Descriptionundont_touch is an alias to theUNDONT_TOUCHcommand. This command provides a short hanmethod for removing thedont_touchattribute.


undont_touch .work.filter_top.rtl

This is the same as entering the followingremove_attribute command line:

remove_attribute .work.filter_top.rtl -name DONT_TOUCH

Related Commands

Related Attributes

dont_touchnoopt

unnoopt

dont_touch noopt



y.

nces

ltiplee

ances,fold

with a

nces

unfoldLevel 3 only.Duplicate views that are used more than once (folded) in the design hierarch

Exampleunfold work.ufold_ex.example

Theunfold command operates on a level of hierarchy (view). Unfold ensures that all instain the view refer to unique cell or view.

Syntax

unfold [<design>]


Ensure that all instances in the given view or views refer to unique cell or view.

DescriptionThe result of reading a design into LeonardoSpectrum is a netlist in which there may be muinstances which refer to the same cell/view. This is referred to as the folded state. While thdesign is in the folded state, you can save it, view reports, set the environment, select instand perform optimization. When you select the view of a level of hierarchy and issue the uncommand, LeonardoSpectrum alters the design so that each instance refers to a uniquecell/view. This means that LeonardoSpectrum “clones” all hierarchical cells with multiplereferences so that each cell is referenced by only one instance. This is the unfolded state.

By default, LeonardoSpectrum represents multiple hierarchical instances of the same cellsingle view or folded state. Operators are the most common instances to be folded.

More ExamplesThe unfold command operates on a level of hierarchy (view). Unfold ensures that all instain the view refer to unique cell or views.

unfold work.ufold_ex.example

Related Commands



fter

se

e

et

ungroupFlatten out the hierarchy.

Exampleungroup -all -hierarchy

In this example, the ungroup command removes all hierarchy under the present design. Athis command, the present design will be a flat netlist of primitives or technology cells.

Syntaxungroup <instance_list>

[ -all ][ -hierarchy ][ -simple_names ][ -except <exclude_instance_list>][ -force ]

Arguments

• <instance_list>

Name or names of instances to decompose into non-hierarchical instances. You can unames of any existing instances, including those created previously with the groupcommand. Wildcards are allowed. You may use the-all option in place of specifyinginstance_list .

Options• -hierarchy

Remove all levels of hierarchy under all instances identified ininstance_list ; thenremove hierarchy recursively under each new instance, until all levels of hierarchy havbeen removed.

• -simple_names

Use original, non-hierarchical names for new instances. If you omit this argument, theungroup command generates names automatically. The format for new instance and nnames is as follows:

<ungrouped instance name>ungroup <original name>

The default for the variableungroup is the underscore ( _ ) character.

Type Arguments

list <instance_list>, <exclude_instance_list>



ed in

For example, suppose a viewTOPcontains an instance calledX. X points to a viewV.Suppose also thatV contains a netNand an instanceI . If you execute the commandungroupX when the present design isTOP, the instanceX will be removed, and the contents in theview thatX is pointing to (V) will be copied toTOPand get new names:

• Net N (in V) will be copied to a net calledX_N in TOP

• InstanceI (in V) will be copied to instanceX_I in TOP

• -all

Decompose every instance in the current level of hierarchy of the present design. The-all

option is equivalent to using the* character forinstance_list and may be used in placeof specifying instance_list .

• -except <exclude_instance_list>

Exclude the named instances ininstance_list from the ungroup operation.

-force

Flatten outcel ls,even noopt ort echnol ogy cel ls.

Description

Remove one or more levels of hierarchy from a design by decomposing the instances naminstance_list , excluding the instances named inexclude_instance_list .

More Examplesungroup {x y} -except x -hierarchy

In this example, the ungroup command ungroups all hierarchy under the instancey. Instancexis unaffected, since instance x is a parameter of the-except option.

ungroup x

In this example, the ungroup command ungroups only instancex in the present design.Additional hierarchy under the view pointed to byx remains in place.

Related Commands

Related Variables

group present_design

ungroup_hier_separator



sign

n

unmapFlatten out technology cells in the design downto primitives.

Example

Syntaxunmap [<design_name>]

[ -single_level ]

Arguments

• <design_name>

Name of the design in which theunmap command is to flatten out technology cells. Thedefault is the present design.

Options

• -single_level

unmap technology cell instances only at the top level of hierarchy.

DescriptionTheunmap command flattens out technology cells in the design down to primitives. The decan then be written out in VHDL or Verilog and is simulatable without a technology library.Note: Afterunmap command runs, the design may contain redundant logic and be large. Rupre_optimize -common -unused . This cleans the design, removes constants, shared logicand unused logic. The functionality of the design is not changed.unmap unmaps a design thatis mapped to a technology byoptimize. unmap unmaps the design back to primitives. Thedesign afterunmap probably does not have the same structure as the design beforeoptimize .

Caution for FPGA designs with lookup tables (luts): Before you useunmap, run thedecompose_luts command. Refer also to theauto_write command.

Related Commands

write optimize



for

unnooptRemove thenooptattribute on the specified objects(s).

Exampleunnoopt .work.filter_fsm.rtl

This command removes thenoopt attribute from the data base object.work.filter_fsm.rtl

Syntax

unnoopt <object1> <object2>


Name of an instance or view from which to remove thenoopt attribute. One or more objectnames may be specified.

Descriptionunnoopt is an alias to theUNNOOPTcommand. This command provides a short hand methodremoving thenooptattribute.


unnoopt .work.filter_top.rtl

This is the same as entering the followingremove_attribute command:

remove_attribute .work.filter_top.rtl -name NOOPT

Related Commands

Related Attributes

undont_touchnoopt

dont_touch

dont_touch noopt



up_designTraverse the design hierarchy by moving up one or more levels.

Related Commands



view_schematicDisplay a schematic view of the current design (default) or of the specified design.

Example

Syntaxview_schematic [<design>][ -symlib <symbol_library_name>[ -rtl ]

Arguments

• <design>

Name of the design for which to display the schematic.

Options• -symlib <string>

Specifies the name of the symbol library file.

• rtl

Display the RTL schematic for the named design.

Related Commands



warp_vhdlAliased to“uplevel #0 set vhdl_write_use_packages “\”library ieee, work;use ieee.std_logic_1164.all;\nuse WORK.EXEMPLAR_GATES.ALL;\”””

Related Commands



heter.

d

writeWrite a design to a file.

Example

Syntaxwrite <file_name>

[ -format <format_name>][ -downto <library_name>][ -silent ][ -single_level ][ -design <design_name>]

Arguments• <file_name>

Name of the output file.file_name can be a local file name, a relative path name, or anabsolute path name. If you use a dash character (- ) for file_name , the output appears on thestandard output screen.

Always use the forward slash character (/ ) to separate directory names in a path, even on tPC. LeonardoSpectrum interprets the back-slash character (\) as a Tcl escape charac


The format of the output file. Valid values are as follows: edif, sdf, verilog, vhdl, xdb, anpreferences.

Type Arguments

string <format_name>, <design_name>, <library_name>

list <file_name>



the

youit

can

heehave

If you omit this argument, the write command attempts to determine the file format fromextension in the file name as shown in the following table.

If the output file has a file name extension that the write command does not recognize,must indicate the format explicitly. If the write command cannot determine the format,prompts you for the information.

• -downto <library_name>

Do not write the contents of any cells inlibrary_name . Essentially, this argument indicatesthe leaf level of design hierarchy to be written. If you omit this argument, the writecommand writes design hierarchy down to primitives (or technology cells).

• -silent

Do not write any warnings or informational messages.

• -format <format_name>

Specify the format:vhdl|Verilog|edif|xdb|sdf|preference

• -single_level

Write only the top level of (present design) hierarchy. If you omit this option, the writecommand writes the entire design hierarchy of the present design.


By default, the current design is saved duringwrite command.

DescriptionThe write command records the present design to a file in the file format you indicate. Youuse this command at any point in any design flow, as long as there is a present design.

The write command ensures that all identifiers that are written out comply with syntaxrestrictions in the indicated format by using built-in renaming rules. If you want to change tnames of identifiers before writing out a netlist, you need to apply renaming rules before thwrite command is executed. This could be needed if you want to guarantee that identifiers


.edf, .edif, .eds edif

.sdf sdf

.v, .verilog verilog

.vhd, .vhdl vhdl

.xdb xdb

Preference



es,

, theln out

e

lwaysor

the

fter

akes

n.

,

the same name in multiple formats, or if you want to comply with stricter syntax rules on namimposed by the tools that will read the file. For more information, see theapply_rename_rulescommand.

The write command never changes anything in the design database.

Format-Specific Considerations

EDIF

Since the LeonardoSpectrum design database uses the same information model as EDIFwrite command always writes EDIF files with a one-to-one reflection correspondence to alobjects in the design. Libraries, cells, views, nets, ports, instances and attributes are writteexactly as they exist in the design. Therefore, the EDIF format is useful to save and restordesign data to a file at any point in the design flow.

Verilog, VHDL

Since LeonardoSpectrum has no internal representation for busses, the write command awrites all nets and ports as single bits. To simulate a synthesized design against its VHDLVerilog original (with busses), you can create a wrapper file that will re-install the types oforiginal ports. For more information, see the create_wrapper command.

If you write a design expressed in terms of technology-independent primitives (before theoptimize command), VHDL and Verilog formats contain simulatable dataflow statements. Atechnology mapping, all formats (except SDF) contain netlist descriptions in terms oftechnology cells.

SDF

If you indicate SDF for the output format, the write command writes only annotated timinginformation. This information is in a design only after previously reading in SDF timinginformation that was back-annotated from place-and-route tools. Therefore, writing SDF msense only for support of (timing) simulation of back-annotated designs.

XDB

During thewrite command, the output file is saved in a format that can be read back intoLeonardoSpectrum without processing the netlist to remove technology-specific informatioXDB writes a binary dump of your database to a file. The netlist is saved in the originalcondition duringwrite . The objects related to the hierarchical database are saved: librariescells, views. Individual nets, ports, instances are low level objects that are not saved. Inaddition, constraints, if any, are not saved and must be reapplied.

Lookup Tables (LUTs)

Lookup Tables (LUTs), used by LUT mapping routines for Altera FLEX technologies, arewritten as dataflow statements for VHDL and Verilog output formats.



in

The auto_write CommandTheauto_writecommand automatically does needed processing for your target technologyaddition to the write command, including setting variable values and callinggenerate_timespec , decompose_luts andapply_rename_rules , where applicable.

Note: this command replaces thewrite_altera script available with previous releases ofLeonardo.

Related Commands

Related Variables

apply_rename_rulesauto_writecreate_wrapper

readlist_technologies

edif_function_propertynames_collision_extensionsdf_hier_separatorsdf_names_stylevhdl_generic_to_attribute

vhdl_write_bitvhdl_write_use_packageswrite_lut_binding



xmplr_execA version of an executable supporting a nonblocking read.

Syntax

xmplr_exec

Related Commands



xmplr_socket_clientOpen a client socket.

Syntaxxmplr_socket_client [ -host <host_name>]

Arguments• -host <host_name>

Name of the host.

Description

Related Commands

Type Arguments

string <host_name>


Index

INDEX

Aabbreviated options,1-5abbreviated Tcl commands,1-5alias command,1-5alias utility,5-6alphabetical list

batch mode options,4-4attribute

HDL object,1-3, 2-1attributes,1-9auto_read

read command,5-19, 5-100auto_write

utility, 5-20write command,5-142

Bbatch mode

command line,4-4

Ccharacter symbols,1-7CLI Commands

allocate, 5-50, 5-53, 5-120component

corresponding view,2-2connect

connect,5-26connect path,5-28

createcreate,5-32create_rename_ruleset,5-34create_wrapper,5-35

customizecommand line interface,1-6

Ddatabase

design,1-7object,1-9

design browser,1-9design names,1-9

absolute,1-10relative,1-10

disconnectdisconnect,5-40disconnect_path,5-42

Eexemplar.ini,1-7

Hhelp command,1-6history tracking,1-6

Iinteractive command line shell

design database,1-7list commands,1-12list variables,1-12

Llabel

corresponding to instance,2-2Level 3

interactive command line shell,1-9Level 3 commands

group, unfold, analyze, elaborate,1-4library, 1-8

cell, 1-8work, 1-9

listlist_attributes,5-62list_connection,5-64list_design,5-66list_technologies,5-69

list_attributes command,1-10list_design command,1-10load

load_library,5-71

LeonardoSpectrum for Altera Reference Manual, v2001.1d Index-1

INDEX [continued]

Index

load_modgen,5-73

Mmessages

optimize.log,1-5total.log,1-5

Nname style,3-1net,1-8

Oobject names,1-11objects,1-9operators,1-8optimize

optimize,5-79optimize_timing,5-84preoptimize,5-91

options-architecture=<name>,,4-4-area,,4-4-batchhelp,4-4-bus_name_style,,4-5-chip,,4-5-command_file=<file_name>,,4-5-control=<file_name>,,4-5-crit_path_analysis_mode=both,,4-5-crit_path_analysis_mode=maximum,,4-5-crit_path_analysis_mode=minimum,,4-5-crit_path_arrival=<float_number>,,4-6-crit_path_detail=short|full,,4-6-crit_path_from=<node_list>,,4-6-crit_path_longest,,4-6-crit_path_no_int_terminals,,4-6-crit_path_no_io_terminals,,4-6-crit_path_report_input_pins,,4-6-crit_path_report_nets,,4-6-crit_path_rpt=<file_name>,,4-7-crit_path_slack=<float_number>,,4-7

-crit_path_to=<node_list>,,4-6-crit_paths_not_thru=<node_name>,,4-7-crit_paths_thru=<node_name>,,4-7-delay,4-4-design=<name>,,4-7-dont_lock_lcells,,4-7-edif=<file_name>,,4-7-edif_file=<file_name>,,4-7-edif_timing_file,4-8-edifin_ground_net_names,4-8-edifin_ground_port_names,4-8-edifin_ignore_port_names,4-8-edifin_power_net_names,4-8-edifin_power_port_names,4-8-edifout_ground_net_name,4-8-edifout_power_ground_style_is_net,4-8-effort=<effort_level>,,4-8-enable_dff_map_optimize,4-9-encoding=<encoding_style>,,4-9-entity=<name>,,4-10-exclude=<gate_name>,,4-11-file=<script name> Level 3,,4-11-full_case,,4-11-generic=<name> <value>,,4-11-global_sr=<name>,,4-11-help,,4-11, 4-12-hierarchy_auto,,4-12-hierarchy_flatten,,4-12-hierarchy_preserve,,4-12-highlight_file,4-12-include=<gate_name>,,4-12-input_format=<file_type>,,4-12-insert_global_bufs,4-12-lock_lcells,,4-7-log_file, 4-12-lut_max_fanout,4-13-macro,4-5-map_area_weight=<integer>,,4-13-map_delay_weight=<integer>,,4-13-map_muxf5,4-13

LeonardoSpectrum for Altera Reference Manual, v2001.1dIndex-2

Index

INDEX [continued]

a

-max_cap_load=<integer>,,4-13-max_fanin=<integer>,,4-13-max_frequency=<integer>,,4-13-max_pt=<integer>,,4-13-maxarea=<integer>,,4-13-maxdly=<integer>,,4-13-modgen_library=<name>,,4-13-module=<name>,,4-14-ncf_filename,4-14-nobreak_loops_in_delay,,4-14-nobus,4-14-nocascades,,4-14-nocheck_complex_ios,,4-14-nocontrol,,4-5-nocounter_extract,,4-14-nocrit_path_rpt,,4-7-nodecoder_extract,,4-14-noenable_dff_map,4-9-noglobal_symbol,,4-14-noinfer_global_sr,,4-14-noopt=<gate_name>,,4-14-nopack_clbs,,4-15-nopass=<pass_number>,,4-15-nopld_xor_decomp,,4-15-noram_extract,,4-15-nosdf_hierarchical_names,,4-15-nosummary,,4-15-notimespec_generate,,4-15-notransformations,,4-15-nowire_table,,4-20-nowrite_lut_binding,,4-15, 4-16-noxlx_preserve_pins,,4-16-num_crit_paths=<number_paths>,,4-16-optimize_cpu_limit=<seconds>,,4-16-output_format=<file_type>,,4-16-package=<name>,,4-16-parallel_case,,4-16-part=<part_number>,,4-16-pass=<pass_number>,,4-16-preference_filename=<file_name>,,4-16

-preserve_dangling_net,,4-16-process=<name>,,4-16-product=<ls1| ls2| ls3>,,4-17-propagate_clock_delay,,4-17-report_brief,,4-17-report_full,,4-17-

sdf_hier_separator=<separator_chracter>,,4-17

-sdf_in=<file_name>,,4-17-sdf_names_style=vhdl|verilog|none,,4-17-sdf_out=<file_name>,,4-17-sdf_type=min|typ|max,,4-17-select_modgen=fast|fastest,,4-17-select_modgen=smallest|small,,4-17-session_file,4-18-simple_port_names,,4-18-source=<library_name>,,4-18-summary=<file_name>,,4-18-target=<library_name>,,4-18-temp=<degrees>,,4-18-tristate_map,,4-18-use_qclk_bufs,,4-19-verilog_file,4-19-verilog_wrapper=<wrapper_file>,,4-19-vhdl_87,,4-19-vhdl_93,,4-19-vhdl_file, 4-19-vhdl_wrapper=<wrapper_file>,,4-19-vhdl_write_87,,4-19-vhdl_write_bit=<type>,,4-19-viewlogic_vhdl,,4-19-voltage=<volts>,,4-19-wire_table=<name>,,4-20-wire_tree=best|balanced|worst,,4-20-write_clb_packing,,4-20-xlx_preserve_gts,,4-20

Ppop_design script,1-10

LeonardoSpectrum for Altera Reference Manual, v2001.1d Index-3

INDEX [continued]

Index

port instance,1-8present_design command,1-10primitives,1-8push_design script,1-10

Rread

auto_read,5-100read command,5-97

redirecting output,1-5remove

remove,5-103remove_attribute,5-105remove_clock,5-107remove_rename_ruleset,5-108

reportreport_area,5-109report_constraints,5-111report_delay,5-113report_rename_rules,5-117report_wire_tables,5-118

root,1-9libraries,1-8

Sscripts,1-11, 4-4set

set_attribute,5-123set_clock,5-125set_multicycle_path,5-126

slash character,1-7Sourcing files

with spaces in the pathname,4-4, 4-11Spaces

in pathnames,4-4, 4-11syntax

constraint file,2-4declaration,2-2interactive command line shell,2-3Verilog, 2-3

VHDL, 2-2

TTcl, 1-12, 4-4, 4-11Tcl language,1-2, 1-6Tcl script

command line with path,1-4Exemplar history file,1-4interactive command line shell,1-3run script,1-3

Tcl variables,3-1

Uutility aliases,5-6utility scripts,5-14, 5-15

VVerilog array objects,3-1VHDL array objects,3-1view

instance,1-8port,1-8

Wwildcards,1-9write

auto_write,5-142write command,5-140

LeonardoSpectrum for Altera Reference Manual, v2001.1dIndex-4

leonardospectrum reference manual

Documents