leon3-fault tolerant design against radiation effects...

Tous droits réservés © 2007, Alcatel Alenia Space ETCA

Alcatel Alenia Space ETCARef : LEONDARE-ETCA-XR-0034 Iss. 1 Rev. 1

LEON3-Fault TolerantDesign Against Radiation Effects ASIC

Microelectronic Presentation Days – 3rd Edition 7 March 2007



Table of Contents

Project Overview� Context

� Industrial Organization

LEON3-FT IP� LEON3-FT

� ASIC Baseline Design

� LEON3-FT DARE Architecture

� IP Cores and Performances

ASIC Layout and Manufacturing� DARE Cell Library

� Layout and Manufacturing

ASIC Evaluation Testing� Electrical Tests

� Radiation Tests



Project Overview



Context

ESA ITT AO/1-4912/05/NL/JD dated June 2005

GSTP funding

Study objective :� To develop, manufacture, test and evaluate an ASIC prototype for space using DARE library and UMC 180 nm technology

� To enable foundry and assembly services for qualified Flight Models in a commercial deep sub micron technology

Proposal�Based on high performance SPARC V8 processor using LEON3-FT design

� Suitable for high-end applications



Industrial Organization

Contractors�Alcatel Alenia Space ETCA (B) - Prime

� Validation and evaluation testing

�GAISLER RESEARCH (SE)

� LEON3-FT processor design

� IMEC (B)

� Layout generation and DARE library

� ASIC manufacturing

Planning�Kick-Off dated end August 2006

� Projected duration of 2 years

�Activities now ongoing for 6 months



LEON3-FT IP



GAISLER RESEARCH and LEON3-FT

Gaisler Research develops IP-cores for both space and commercial markets, targeting demanding embedded applications.

Main VHDL IP-core products are:

� LEON3-FT SPARC V8 32-bit Integer Unit

�GRFPU-FT IEEE-754 Floating Point Unit

� 32-bit / 33 MHz Target/Initiator PCI

� SpaceWire with DMA and RMAP

� 10/100/1000 Ethernet MAC

�MIL-STD-1553, CAN 2.0, CCSDS TM/TC, USB 2.0, IDE-ATA, SVGA

�Memory controllers with EDAC, DDR, SDRAM, SRAM/PROM

The objective is to develop a complex and performant System-on-a-Chip design that challenges and fully demonstrates the capability of the DARE silicon library.



ASIC Baseline Design

The LEONDARE baseline design comprises :

�LEON3 SPARC V8 32-bit Integer Unit

�GRFPU-FT IEEE-754 Floating Point Unit

�Debug Support Unit with UART Debug Links

�Memory controller with EDAC: PROM/SRAM/SDRAM/I/O

�Timer unit with 32-bit timers and watchdog

�Interrupt controller for 15 interrupts in two priority levels

�Two UARTs with FIFO and separate baud rate generators

�8-bit general purpose input output port

�3 x SpaceWire links with RMAP support

The baseline package is the 208-pin Ceramic Quad Flat Package.

The operating temperature range is -55 to 125 oC.



LEON3-FT DARE Architecture



IP Cores and Performances

The LEONDARE design uses IP-cores exclusively from the GRLIB VHDL IP-core library.

The architecture is based on AMBA AHB / APB buses and implements plug&play capabilities, used by debug tools and operating systems.

Expected performance:

� SEU tolerant:

�hardened flip-flops

� on-chip memory protection by means of design methods

� 100 MHz – 200 MHz processor speed

� 100 – 200 MIPS / MFLOPS

� 200 Mbit/sec bi-directional SpaceWire links



ASIC Layout and Manufacturing



DARE cell library

DARE = Design Against Radiation Effects Technology: UMC L180 CMOS Logic 1P6M (1.8V/3.3V) Hardened using layout techniques

� Enclosed transistors & guard bands� No leakage current increase (TID tested up to 1MRad)

86 Core Cells� 50 combinatorial cells� 2 x 18 flip-flop & latch cells included (18 HIT cell–based SEU hard)

23 In-line IO Pad Cells (+ P/G + Corners + Fillers)� 3.3V & 2.5V I/O’s� Includes LVDS (driver, receiver & bias)� Several pull-up/down options� >4KV HBM ESD performance� 5V tolerance & cold spare possibility proven

Single Port SRAM Compiler (standard 6 transistor RAM cell) PLL Maximum gate density: 25Kgates/mm2



LEONDARE Layout & Manufacturing

Scan insertion, ATPG & Layout� For 10 years IMEC has a (commercial) ASIC design support service (RTL to GDSII), Tool sets:

� Synopsys Galaxy Platform

� Cadence Encounter Platform

Manufacturing�Monthly UMC .18 EUROPRACTICE MPW run

� Extra wafers supply sufficient samples for testing

�Only LEONDARE dies are delivered (no wafers)

Note: DARE can also be used in mixed signal designs



ASIC Evaluation Testing



Electrical Tests

Production electrical tests � Electrical go-no go tests and measurements performed at –55/+25/+125°C on all devices including :

� Assembly (wire bonding) and I/O (protection network) continuity check

� Supply currents measurement

� Static and dynamic parameters measurement

� Scan and functional tests

Functional electrical tests � 5 prototypes validated by the production electrical test randomly selected

� Functional tests performed in application-representative conditions on GAISLER GR-PCI-XC2V LEON PCI development board



TID Radiation Tests

Radiation test – Total dose (10 prototypes)� Total dose (Co60) level is set to 1 Mrad(Si) applied in to 2 steps :

� Low dose rate (36 to 360 rad/hr) for 0 to 100 kRad(Si)

� High dose rate (3.6krad/hr to 36 krad/hr) for 200 to 1000kRad(Si)

�Verification with the production test setup at each step

� Supply current and ring oscillator drifts measurement



SEE Radiation Tests

Radiation test – Single events (3 prototypes)� Self-checking SEU test software running internally into chip with external monitoring

� GAISLER dedicated SEU test software

� SEL detection by supply current monitoring

� Ion types

Ion type M/Q Energy (MeV) LET

(MeV/mg/cm²)

20Ne4+ 5 78 5.85

40Ar8+ 5 150 14.1

84Kr17+ 4.94 316 34

132Xe26+ 5.07 459 55.9



Alcatel Alenia Space ETCA Tél. : + 32/71 44 22 11

Fax : + 32/71 44 22 22

www.alcatel.be/etca

E-mail : [email protected]

leon3-fault tolerant design against radiation effects...

Documents