lecture3

Lecture 3

Signal Description of 8086

Zelalem Birhanu, AAiT 1

In this lecture

• Pin layout and signal description

• Memory Addressing

• I/O Addressing


8086 Features

40 pin CERDIP or plastic package

5, 8 and 10MHz clock rate Can operate in minimum or

maximum modeo Minimum- single

processor modeo Maximum-

multiprocessor mode


Pin Layout


Signal Description

• Signals can be categorized based on their function

Memory and I/O interfacing signals

Status signals

Interrupt signals

Other signals


Memory Interfacing Signals

8086Memory

(up to 1MB)

20-bit Address

16-bit Data

8086 uses the same lines for address and data These lines are time multiplexed (the same lines are

used as address lines and data lines at different times)


Memory Interfacing Signals…cntd

• A bus cycle includes applying physical address and accessing (reading / writing) a byte of data from memory location

• A bus cycle consists of four clock cycles (T1, T2, T3, T4) and optional waiting clock cycles Tw



T1: The address is put on address bus

T2,T3, Tw, T4: Data is put on the data bus

AD15 – AD0: Time multiplexed address

and data lines

A19 – A16: Time multiplexed address

and status lines



AD15-AD08086

Memory(up to 1MB)

A19-A16 LATCH(8282)

TRANSCEIVER(8286)

Address

Data


• During T1 the address latch is enabled using the signal ALE (ALE = 1)

• After T1 the data transceiver is enabled using the signal DEN (DEN = 0)

• Since the data line is bidirectional, the signal named DT/ R is used to select direction of data


𝐷𝑇/ 𝑅 = 0 From memory to 8086

𝐷𝑇/ 𝑅 = 1 From 8086 to memory



AD15-AD08086

Memory(up to 1MB)

A19-A16 LATCH(8282)

TRANSCEIVER(8286)

Address

Data

ALE

DEN 𝐷𝑇/ 𝑅

𝐷𝐼𝑅

𝐸𝑁

𝐸𝑁


• The 1MByte memory is organized as two 512KByte banks called upper (odd) bank and lower (even) bank



• A memory bank to be accessed is selected using the signals A0 (AD0) and 𝐵𝐻𝐸


𝐁𝐇𝐄 A0 Access Indications

0 0 Whole word (16-bits)

0 1 Upper byte from odd address

1 0 Lower byte from even address

1 1 None



AD15-AD0

8086

Lower Bank

A19-A16 LATCH(8282)

TRANSCEIVER(8286)

ALE

DEN 𝐷𝑇/ 𝑅

𝐷𝐼𝑅

𝐸𝑁

𝐸𝑁

Upper Bank

𝐴0

𝐶𝑆

BHE

𝐶𝑆

D7

-D0

D1

5-D

8

D15-D0


S3 and S4• Time multiplexed with A17 and A16• Indicate which segment register is presently being used

for memory access

S5• Time multiplexed with A18• Shows the status of the interrupt enable flag bit and is

updated at the beginning of each clock cycle

Status Signals

S4 S3 Indications

0 0 ES

0 1 SS

1 0 CS or none

1 1 DS


Interrupt Signals

INTR (Interrupt request)

• This an interrupt request which is a high level triggered input internally synchronized to the CPU

• It can be internally masked (disabled) by resetting the interrupt enable flag

NMI (Non-Maskable Interrupt)

• Positive edge triggered interrupt

• Non maskable internally by software


Other Signals

CLK• The clock input provides the basic timing for processor

operation and bus control activity. It’s an asymmetric square wave with 33% duty cycle

𝑀𝑁/𝑀𝑋• Indicates whether the processor is to operate in either minimum

(single processor) or maximum (multiprocessor) mode

READY• This is the acknowledgement from the slow devices or memory

that they have completed the data transfer


Other Signals…cntd

VCC

• +5V power supply

GND

• Ground


I/O Addressing

• I/O devices contain registers to exchange data with the CPU

• These registers are assigned addresses just like memory locations

• 8086 can address up to a maximum of 64K I/O byte registers


Next Class

• 8086 Instruction Set


More Readings

1. Dr. Manoj’s Handout, Chapter 1

2. 8086 Datasheet, Intel


lecture3

Documents

none11dszelalem birhanu

intelzelalem birhanu

software zelalem birhanu

status lines zelalem

different timeszelalem

instruction setzelalem

d8d15d0zelalem birhanu

address lines