lecture21 matching 2up
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EECS240 – Spring 2012
Lecture 21: Matching
Elad AlonDept. of EECS
EECS240 Lecture 21 2
Offset
• To achieve zero offset, comparator devicesmust be perfectly matched to each other
• How well-matched can the devices be made?• Not arbitrary – direct function of design choices
Vi+ Vi-
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EECS240 Lecture 21 3
Device Mismatch Categories
• Die-to-die• All devices on same chip (or wafer) have same
characteristics
• Within die (long-range)• All devices within certain region have same
characteristics
• Local (short-range)• Every device different, random
• Usually most important source of mismatch
EECS240 Lecture 21 4
Sources of Local Variation• Deterministic sources:
• Local poly density
• Sub-90nm: stress, litho interactions, …
• Random sources:
• Dopant fluctuations
• Line-edge roughness
• Oxide traps
• Focus our modeling on random variations
• Deterministic handled with good layout practices
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EECS240 Lecture 21 5
References
• M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G.Welbers, "Matching properties of MOS transistors," IEEE
JSSC, vol. 24, pp. 1433 - 1439, Oct. 1989
• Mismatch model
• Statistical data for 2.5 m CMOS
• J. A. Croon, M. Rosmeulen, S. Decoutere, W. Sansen, and
H. E. Maes, “An easy-to-use mismatch model for the MOS
transistor,” IEEE JSSC, vol. 37, pp. 1056 - 1064, Aug. 2002
• 0.18 m CMOS data
EECS240 Lecture 21 6
Mismatch Statistics• Total mismatch set by composite of many
single, independent events
• Correlation distance << device dimensions
• E.g., number of dopant atoms implanted into the
channel
• Individual effects are small: linear superposition
holds
• Mismatch is zero mean, Gaussian distribution
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EECS240 Lecture 21 7
Parameter Mismatch Model
222
2
xP
P DS
WL
AP
2 : variance of P
: active gate area
: distance between device centers
: measured area proportionality constant
: measured distance proportionality constant,
:
x
P
P
P
WL
D
A
S
0 for "good" layout
EECS240 Lecture 21 8
VT Mismatch
2
2 2 2T
T
V
T V x
AV S D
WL
,
,
2.5μm CMOS process :
30 mV m
35 mV m
T
T
V N MO S
V P MO S
A
A
• Mismatch in VT between
two identical devices:
• Often largest source of
offset
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EECS240 Lecture 21 9
Drain Bias, VDS
VT largely independent of VDS
EECS240 Lecture 21 10
Back-Gate Bias, VSB
• Mismatch can
depend on VSB
• Why?
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EECS240 Lecture 21 11
Current Matching, ID /ID
Strong bias dependence (we knew that already)
EECS240 Lecture 21 12
Current Factor
L
W C
ox
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EECS240 Lecture 21 13
Sources of β Mismatch
• Mobility variations• E.g., due to dopant variations, random defects
• Oxide thickness variation
• Usually very well-controlled
• Edge roughness
EECS240 Lecture 21 14
Edge Model
For:
Simplifies to:
2
2
2
2
2
2
2
2
2
2
n
n
ox
ox
C
C
L
L
W
W
2222
2
2
2
2
2
2
DS WL
A
WL
A
LW
A
WL
Aox
C W L
W
L L
W 1 and 1 22
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EECS240 Lecture 21 15
Orientation Effects
• Si and transistors are not
(perfectly) isotropic
• keep direction of
current flow same!
EECS240 Lecture 21 16
Distance Effect
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EECS240 Lecture 21 17
Process Dependence
• AVt tends to scale
with technology
• Proportional to tox
• Also depends on
doping level
EECS240 Lecture 21 18
0.18 m CMOS
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EECS240 Lecture 21 19
Current Matching
EECS240 Lecture 21 20
Voltage Matching
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EECS240 Lecture 21 21
“Golden Rule” of Layout for Matching
• Everything you can think of might matter
• Even whether or not there is metal above the
devices
• How to avoid systematic errors?
Ref: A. Hastings, “The art of analog layout,” Prentice Hall, 2001
EECS240 Lecture 21 22
Common Centroid Layout• Cancels linear gradients
• Required for moderate matching
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EECS240 Lecture 21 23
Simulating Mismatch
• Brute force: Monte Carlo
• HSPICE “throws the dice”…
EECS240 Lecture 21 24
Simulating Mismatch