lecture05 datapath design - university of maryland...lecture05_datapath_design.pptx author: anwar...
TRANSCRIPT
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Single Cycle Datapath Design
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Datapath design steps
• Analyze ISA, Obtain datapath requirements • Select modules for datapath • Connect the modules and build and datapath • Generate control signals for each instrucDon • Combine control signals, create control logic
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MIPS Instruc6ons (1) • Unsigned addi6on and Subtrac6on
• Format
• Opera6on
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MIPS Instruc6ons (2) • Immediate type instruc6on
• Opera6on
• Format
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Hardware components
• ALU – OperaDons: add, sub, compare etc – Operands: Two 32-‐bit numbers from
registers or extended immediate number
• Immediate number extender • Program Counter
– One 32-‐bit register – Add 4 or an immediate number
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Hardware components
• Register File – 32 32-‐bit register – Read rs, rt – Write rt, rd
• Memory – Read only InstrucDons memory, 32-‐bit address – Data memory, read&write, 32-‐bit address
• Program Counter
– One 32-‐bit register – Add 4 or an immediate number
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Register File
• OrganizaDon – 32 32-‐bit registers
• Data Ports – busA,busB: Two 32-‐bit data output – busW: one 32-‐bit data input
• Read/Write Control – Ra(5-‐bit): select the register, copy content to busA – Rb(5-‐bit): select the register, copy content to busb – Rw(5-‐bit): select the register, at clock (clk) rising edge, if writeEnable==1, write the
content of busW to selected register
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Memory
• Data Port – Data In: 32-‐bit data input – Data-‐out: 32-‐bit data output
• Read/Write Control – Address: 32-‐bit address signal. Send the specified memory content to data-‐out
– Write-‐Enable: at clock rising edge, if write-‐enable is set, writes data-‐in content to specified address
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Instruc6on Requirements
• Fetch Instruc6on – PC: instrucDon address – Fetch instrucDon using PC
specified address • Update PC
– SequenDal • PC = PC + 4
– Branch • PC=Branch Target address
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Instruc6on Requirements
• Fetch Instruc6on – PC: instrucDon address – Fetch instrucDon using PC
specified address • Update PC
– SequenDal • PC = PC + 4
– Branch • PC=Branch Target address
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Instruc6on Requirements
• Fetch Instruc6on – PC: instrucDon address – Fetch instrucDon using PC
specified address • Update PC
– SequenDal • PC = PC + 4
– Branch • PC=Branch Target address
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Instruc6on Requirements
• Fetch Instruc6on – PC: instrucDon address – Fetch instrucDon using PC
specified address • Update PC
– SequenDal • PC = PC + 4
– Branch • PC=Branch Target address
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Add, Sub Requirements
Decoder generate RegWr, ALUCtr control signals
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ori Requirements
• Des6na6on is rt, not rd • ALU input is immediate number • Immediate number is 16-‐bit
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ori Requirements
Solu6on: Add two mul6plexer
• Des6na6on is rt, not rd • ALU input is immediate number • Immediate number is 16-‐bit
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• Load and Store a word (32-‐bit)
• Format
• OperaDon
MIPS Instruc6ons (3)
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Load Instruc6on Requirements
• How to sign extend? • Load data from where?
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Load Instruc6on Requirements
• ZeroExtender • -‐> Extender • Add memory
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Store Instruc6on Requirements
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So far we have
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Datapath design steps
• Analyze ISA, Obtain datapath requirements • Select modules for datapath • Connect the modules and build and datapath • Generate control signals for each instrucDon • Combine control signals, create control logic
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