lecture notes 7a 1

Lecture Notes # 6 EE455 - Prof. R. Bashir 1

Processing and Layout• Clean Room Requirements


Processing and Layout• Silicon Start Material - epitaxy (on-arrangement)

– Czochralski Method

– Bridgeman Method

– Current state of the art is 8” wafer dia.


Processing and Layout



• Thermal Oxidation– Si + O2 --> SiO2

– Si + 2H2O --> SiO2 + 2H2

– Gate Oxidation• as thin as 40Å for a L=0.18µm CMOS Technology

– Field Oxidation • thick 0.5µm to 1.5µm



• PhotoLithography– Photoresist: optically

sensitive polymer which when exposed to UV light changes its solubility in specific chemicals



• Photo Mask Generation



• Etching– Wet etching (isotropic)

• Use chemicals which react with underlying material but does not react with photoresist

– Dry Etching (anisotropic or isotropic)• Use ionized gases and which react with underlying material but does

not react with photoresist



• Doping Techniques - Diffusion– Wafers placed in a heated quartz tube (800°C to 1150°C)

– Thermal energy results in dopant species to diffuse in the silicon lattice



• Doping Techniques - Ion Implantation– Energetic Ions are bombarded onto the silicon wafer

– The depth and shape of the profile after implant can be modelled and depends on the energy and dose of the implant species


Processing and Layout• Chemical Vapor Deposition

– Silicon Nitride (Si3N4)

• 3SiH4 + 4NH3 ------> Si3N4+12H2

• resistant to oxidation

– Poly-Silicon• SiH4 -----> Si + 2H2

– Oxide• SiH4 +O2-----> SiO2 + 2H2


Processing and Layout• Device Isolation

– LOCOS (Local Oxidation of Silicon)

– Use Nitride as a mask during oxidation

lecture notes 7a 1

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