lecture 9 rtl design methodology. structure of a typical digital system datapath (execution unit)...
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Lecture 9
RTL Design Methodology
Structure of a Typical Digital System
Datapath(Execution
Unit)
Controller(Control
Unit)
Data Inputs
Data Outputs
Control Inputs
Control Outputs
Control Signals
StatusSignals
Hardware Design with RTL VHDL
Pseudocode
Datapath Controller
Block
diagram
Block
diagram
State diagram
or ASM chart
VHDL code VHDL code VHDL code
Interface
Steps of the Design Process
1. Text description2. Interface3. Pseudocode4. Block diagram of the Datapath5. Interface with the division into the Datapath and the Controller6. ASM chart of the Controller7. RTL VHDL code of the Datapath, the Controller, and the Top
Unit8. Testbench of the Datapath, the Controller, and the Top Unit9. Functional simulation and debugging10. Synthesis and post-synthesis simulation11. Implementation and timing simulation12. Experimental testing
Steps of the Design ProcessPracticed in Class Today
1. Text description2. Interface3. Pseudocode4. Block diagram of the Datapath5. Interface with the division into the Datapath and the Controller6. ASM chart of the Controller7. RTL VHDL code of the Datapath, the Controller, and the
Top Unit8. Testbench of the Datapath, the Controller, and the Top
Unit9. Functional simulation and debugging10. Synthesis and post-synthesis simulation11. Implementation and timing simulation12. Experimental testing
min_max_average
example
Circuit Interface
n
5
n
2
clk
reset
in_data
in_addr
write
START
DONE
out_data
out_addrMIN_MAX_AVR
Interface Table
Port Width Meaning
clk 1 System clock
reset 1 System reset – clears internal registers
in_data n Input data bus
in_addr 5 Address of the internal memory where input data is stored
write 1 Synchronous write control signal
START 1 Starts the computations
DONE 1 Asserted when all results are ready
out_data n Output data bus used to read results
out_addr 2 01 – reading minimum10 – reading maximum11 – reading average
Pseudocode
Begin:
SUM = SUM + CDATA;if (CDATA < MIN) then MIN = CDATA;endifif (CDATA > MAX) then MAX = CDATA;endif
endfor
AVR = SUM/32DONE = 1goto Begin
MAX = 0;MIN = 2n-1;SUM = 0;for i=0 to 31 do CDATA = M[i];
wait for START;
RTL Hardware Design by P. Chu
Chapter 10 10
• Difference between a regular flowchart and ASM chart:– Transition governed by clock – Transition done between ASM blocks
• Basic rules:– For a given input combination, there is one
unique exit path from the current ASM block– The exit path of an ASM block must always
lead to a state box. The state box can be the state box of the current ASM block or a state box of another ASM block.
RTL Hardware Design by P. Chu
Chapter 10 11
• Incorrect ASM charts:
RTL Hardware Design by P. Chu
Chapter 10 12
sorting
example
Sorting - Required Interface
Sort
Clock
Resetn
DataInN
DataOut
N
DoneRAdd
L
WrInit
S(0=initialization 1=computations)
Rd
Sorting - Required Interface
Simulation results for the sort operation (1)Loading memory and starting sorting
Simulation results for the sort operation (2)Completing sorting and reading out memory
Before
sorting
During Sorting After
sorting
Address
0
1
2
3
3 3 2 2 1 1 1 1
2 2 3 3 3 3 2 2
4 4 4 4 4 4 4 3
1 1 1 1 2 2 3 4
i=0 i=0 i=0 i=1 i=1 i=2
j=1 j=2 j=3 j=2 j=3 j=3
MiMj
Legend:position of memory
indexed by i
position of memory
indexed by j
Sorting - Example
Pseudocode
wait for s=1for i=0 to k-2 do
A = Mi
for j=i+1 to k-1 doB = Mj
if A > B thenMi = BMj = AA = Mi
end ifend for
end forDonewait for s=0go to the beginning
DIN
DOUT
ADDR
WE
CLK
ENCLK RST
ENCLK RST
A>B
01 s
WrInit
Clock
Clock
Clock
Resetn Resetn
Wr
1 0 Bout
Aen Ben
AgtB
Addr
s
0
10
1
DataIn RAdd
Rd
DataOut
Csel
ENCLK
LDRST
Resetn
ENCLK
LDRST
Resetn
LiEi
Clock
LjEj
Clock
= k-2 = k-1
zi zj
NL
L
LL
N N
N
N
N
ABMux
A B
i
j
ABData
Din
We
0
L
+1
Block diagram of the Execution Unit