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DEVICE DRIVERS AND INTERRUPTSSERVICE MECHANISM

Lecture #7

Interrupt Concept

• Interrupt means event, which invites attention

of the processor on occurrence of some action

at hardware or software interrupt instruction

event.

Action on Interrupt

• In response to the interrupt, the routine or

program, which is running presently interrupts

and an interrupt service routine (ISR)

executes.

Interrupt Service Routine

• ISR is also called device driver in case of the

devices and called exception or signal or trap

handler in case of software interrupts

Interrupt approach for the port or device functions

• Processor executes the program, called interruptservice routine or signal handler or trap handleror exception handler or device driver, related toinput or output from the port or device or relatedto a device function on an interrupt and does notwait and look for the input ready or outputcompletion or device-status ready or set

Interrupt service routine (ISR) or devicedriver function

• Example 1: An automatic chocolate vendingmachine (ACVM)

• The system awakens and activates on an interruptthrough a hardware or software signal. Thesystem on port interrupt collects the coin byrunning a service routine. This routine is calledinterrupt handler routine for the coin-port read.

Example 2: Digital camera system

• Has an image input device.

• The system awakens and activates on interrupt from a switch.

• When the system wakes up and activates, the device should grab

an image frame data.

• The interrupt is through a hardware signal from the device switch.

On the interrupt, an ISR (can also be considered as camera’s

imaging device driver function) for the read starts execution, it

passes a message (signal) to a function or program thread or task

Hardware interrupt

• Examples─ When a device or port is ready, a device or port

generates an interrupt, or when it completes the assigned

action or when a timer overflows or when a time at the

timer equals a pre-set time in a compare register or on

setting a status flag (for example, on timer overflow or

compare or capture of time) or on click of mice in a

computer.

• Hardware interrupt generates call to an ISR

Software Interrupt

Examples

• When software run-time exception condition (for examples, division

by 0 or overflow or illegal opcode detected) the processor-hardware

generates an interrupt, called trap, which calls an ISR

• When software run-time exception condition defined in a program

occurs, then a software instruction (SWI) is executed─ called

software interrupt or exception or signal, which calls an ISR

Software Interrupt

• When a device function is to be invoked, for example, open

(initialize/configure) or read or write or close , then a software

instruction (SWI) is executed─ called software interrupt to

execute the required device driver function for open or read or

write or close operations.

2008 Chapter-4 L10: "Embedded Systems - " , Raj Kamal, Publs.: McGraw-Hill Education 1

DEVICE DRIVERS AND INTERRUPTS SERVICE MECHANISMLessonLesson--10: 10: Context, context Switching Context, context Switching andandinterrupt latencyinterrupt latency


1. Context1. Context


An embedded system executes:• multiple tasks (processes). An

operating system facilitates this• perform multiple actions or functions

due to multiple sources of the interrupts. An interrupt service mechanism in the system facilitates this


� The multitasking and multiple ISRsexecute even though there is only one processor by first saving the one program context and retrieving another program context


Current program’s program counter, status Current program’s program counter, status word, registers, and other programword, registers, and other program--contextscontexts

� Before executing new instructions of the new function, the current program’s program counter are saved.

� Also status word, registers, and other program-contexts are saved, if not done automatically by the processor.

� Because the program counter, status word register and other registers are needed by the newly called function.


Program CounterProgram Counter-- a part of the context of a part of the context of presently running program presently running program

� Getting an address (pointer) from where the new function begins , and loading that address into the program counter and then executing the called function's instructions will change the running program at the CPU to a new program

� Program Counter- a part of the context of presently running program


• A context of a program must includeprogram counter as well as the program status word, stack pointer and may includethe processor registers. The context may be at a register set or at the separate memory block for the stack.

• A register set or memory block can hold context information

Context


• Present CPU state, which means registers and

• May include ID of the process interrupted and

• Function’s local variables.

Context


What should constitute the context?

� Depends on the processor of the system or operating system supervising the program.


Current Program ContextCurrent Program Context

Current Program context

PC (Program counter)

Other CPU registers

SP (stack pointer)Processor status register


An ExampleAn Example

� In an 8051 program, the program counter alone constitute the context for the processor interrupt service and multiple functions call mechanism.

� In 68HC11 program, the program counter, and CPU registers constitute the context for the processor interrupt service and multiple functions call mechanism.


2. Context Switching2. Context Switching


New program executes with new context of New program executes with new context of called routinecalled routine

Save current routine context on stack and load new routine context

Context Switching


Context Switching on Interrupts• Context switching means saving the

context of interrupted routine (or function) or task and retrieving or loading the new context of the called routine or taskto be executed next.


Context switching for new routine and another Context switching for new routine and another switch on return routineswitch on return routine

Save current routine context on stack and load new routine context

Steps

Execute new routine codes

1

2

3

Current routine

Context Switching

Context Switching

On return save new routine context and switch for the previous routine by retrieving the saved context

On switching for new routine


Context switching in case of multiple Context switching in case of multiple interruptsinterrupts

ISR or program

High priority

ISR

Starts after time t1+ t’ where t’ is context switch timeContext

Switching at t1 Higher

priority ISR

Starts after time t2 + t’where t’is context switch time

Context Switching at t2


Fast Context Switching in ARM7 on Interrupt

• The interrupt mask (disable) flags set [Disable low priority interrupts.]

• Program Counter (PC) saved• Current Program Status Register, CPSR

copies into one for the saved program status register (SPSR), and CPSR stores the new status (interrupt source data or information).


• PC gets the new value as per the interrupt source from the vector table.


On return from the ISR, the context switching back to previous context

(i) Program Counter (PC) retrieves. (ii) The corresponding SPSR copies back into

CPSR. (iii)The interrupt mask (disable) flags are

reset. [Enable again the earlier disabled low priority interrupts.]


Operating systemOperating system� OS provides for memory blocks to be used

as stack frames if internal stack frames are not available at the processor being used in the system.


3. 3. Classification of Processors Interrupt Service Mechanism from Context Saving

Angle


80518051

� 8051 interrupt-service mechanism is such that on occurrence of an interrupt service, the processor pushes the processor registers PCH (program counter higher byte) and PCL (program counter higher byte) on to the memory stack.

� The 8051 family processors do not save the context of the program (other than the absolutely essential program counter) and a context can save only by using the specific set of instructions for that. For example, using Push instructions at the ISR.


Advantage of Saving PC only in 8051Advantage of Saving PC only in 8051

� It speeds up the start of ISR and returns from ISR but at a cost.

� The onus of context saving is on the programmer in case the context (SP and CPU registers other than PCL and PCH) to be modified on service of or on function calls during execution of the remaining ISR instructions.


68HC11 interrupt mechanism68HC11 interrupt mechanism� Processor registers save on to the stack whenever

an interrupt service occurs. These are in the order of PCL, PCH, IYL, IYH, IXL, IXH, ACCA, ACCB, and CCR.

� 68HC11 thus does automatically save the processor context of the program without being soany instructed in the user program.

� As context saving takes processor time, it slows a little at the start of ISR and returns from ISR but at the a great advantage that the onus of context saving is not there on the programmer and there is no risk in case the context modifies on service or function calls


• ARM7 provides a mechanism for fast context switching between the two tasks, one current and one at the stack.

ARM7 interrupt mechanismARM7 interrupt mechanism


SummarySummary


� Each running-program has a context at an instant.

� Context means a CPU state (program counter, stack pointer(s), registers and program state (variables that should not be modified by another routine). The context must be saved on a call to another ISR or task or routine

We learnt


We learnt :� Context-Switching� 8051, 68HC11 and ARM7 processors

provide for different mechanisms for the context saving and switching .


End of Lesson 10 of Chapter 4End of Lesson 10 of Chapter 4


DEVICE DRIVERS AND INTERRUPTS SERVICE MECHANISMLessonLesson--11: 11: Interrupt latency and Service Interrupt latency and Service deadlinedeadline


1. Interrupt Latency1. Interrupt Latency


Interrupt Latency

� A period between occurrence of an interrupt and start of execution of the ISR

� The time taken in context switching is also included in a period, called interrupt latency period, Tlat.


Minimum Interrupt-latency period� Tlat, is the sum of the periods as

follows. � Time to be taken is for the response

and initiating the ISR instructions. � This includes the time to save or

switch the context (including the program counter and registers) plus the time to restore its context.


For example, in the ARM7 processor, this period equals two clock cycles plus zero to twenty clock cycles for finishing an ongoing instruction plus zero to three cycles for aborting the data.


Minimum Latency = context switching periodMinimum Latency = context switching period

� When the interrupt service starts immediately on context switching the interrupt latency = Tswitch = context switching period. When instructions in a processor takes variable clock cycles, maximum clock cycles for an instructions are taken into account for calculating latency


Latency in case of interrupt service starting Latency in case of interrupt service starting immediately immediately

ISR

Starts after time t0+ t’ only where t’ is context switch time

Processor interrupt at t0

Interrupt latency = t’ only where t’ is context switch time for saving the running program context and loading the new routine context


Latency on context switch to an higher Latency on context switch to an higher priority interrupt priority interrupt

� When the interrupt service does not starts immediately by context switching but context switching starts after all the ISRscorresponding to the higher priority interrupts complete the execution. If sum of the time intervals for completing the higher priority ISRs = ΣTexec , then interrupt latency = Tswitch + ΣTexec.


Latency in case of interrupt service starts after Latency in case of interrupt service starts after ISRsISRs of higher priority than the present of higher priority than the present

interrupt finish the executioninterrupt finish the execution

ISR of higher priority

ISRProcessor

Started at time t0+ t’

Interrupt latency = t2 – t1 + t’ where t’ is context switch time for saving the running program context and loading the new routine context

High priority interrupt event Occurs at t1after t0

Starts after time t2+ t’ only where t’ is context switch time

Finishes at time t2


Latency due to execution of Disable Interrupt Latency due to execution of Disable Interrupt Instruction in a critical sectionInstruction in a critical section

� Tdisable is the period for which a routine is disabled in its critical section. The interrupt service latency from the routine with interrupt disabling instruction (due to presence of the routine with critical section) for an interrupt source will be Tswitch + ΣTexec + Tdisable


Interrupt latency as sum of the periods for Interrupt latency as sum of the periods for TTswitchswitch, , ΣΣTTexecexec and and TTdisabledisable when presently running routine to when presently running routine to

be interrupted is executing critical section codesbe interrupted is executing critical section codes

ISRISR

Critical section codes (Time spent = Tdisable)

Interrupt latency = ΣTexec + Tdisable + Tswitch where Tswitch is context switch time for saving the running program context and loading the new routine context , Tdisable is time for which interrupts remained disabled in critical period and ΣTexec is time for which other high priority routines executed


Worst case latency

� Sum of the periods Tswitch , ΣTexec and Tdisable where sum is for the interrupts of higher priorities only.


Minimum latencyMinimum latency

� Sum of the periods Tswitch and Tdisable when the interrupt is of highest priority.


2. 2. ISR or Task Deadline


ISR or Task Deadline

� For every source there may be a maximum period only up to which the service of its all ISR instructions can be kept pending. This period defines the Deadline period, Td during which the execution must be completed.


Interrupt latency period and deadline for an Interrupt latency period and deadline for an interruptinterrupt

New event ISR

Must finish at time td

Execution time of a routine

Interrupt latency should be such that a deadline of a new event ISR is not missed

Context switch time


Short ISR and functions, which run at later Short ISR and functions, which run at later instances so that the other ISR deadlines are instances so that the other ISR deadlines are

not missednot missed

New event ISR

Routine 1

Interrupt latency = T should be such that a deadline of a new event ISR is not missed

Context switch time

Function Next Routine

Period T

Context switch time Context switch time


ExampleExample

� Video frames in video conferencing reach after every 1 ÷15 s. The device on getting the frame interrupts the system and the interrupt service deadline is 1 ÷15 s, else the next frame will be missed


ExampleExample� A 16-bit timer device on overflow raises TF

interrupt on transition of counts from 0xFFFF to 0x0000.

� To be responded by executing an ISR for TF before the next overflow of the timer occurs, else the counting period between 0x0000 after overflow and 0x000 after next to next overflow will not be accounted.

� If timer counts increment every 1µs, the interrupt service deadline is 216 µs = 65536 µs.


To keep the ISR as short as possibleTo keep the ISR as short as possible

� In case of multiple interrupt sources � To service the in-between pending

interrupts and leave the functions that can be executed afterwards later for a later time.

� Use of interrupt service threads, which are the second level interrupt handlers.

� When this principle is not adhered to, a specific interrupting source may not be serviced within in the deadline (maximum permissible pending time) for that


3. 3. Assignment of priorities to Meet Service Deadlines


Assignment of priorities to Meet Service Deadlines

• By following an EDF (Earlier Deadline First) strategy for assigning the priorities to the ISRs and Tasks, the service deadlines are met.


Software overriding of Hardware Priorities to Software overriding of Hardware Priorities to Meet Service Deadlines Meet Service Deadlines

� It is first decided among the ISRs that have been assigned higher priority by in the user software. If user assigned priorities are , and then if these equal then among the that highest priority, which is pre-assigned by at the processor internal- hardware.


SummarySummary


We learnt :� Interrupt Latency─ Each running-

program when interrupts, the interrupting source service routine takes some time before starting the servicing codes.

� It is sum of execution time of higher priority interrupts and context switching period.


� If the interrupted routine is in critical section (interrupts disabled), the interrupt latency increases by the period equal to interrupts disabled period

� Use of processor, which saves the context fast, use of priority assignments, enabling and disabling of interrupts are resorted to meet the deadlines to finish all the ISRs and tasks within the deadlines.

We learnt


End of Lesson 11 of Chapter 4End of Lesson 11 of Chapter 4

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