lecture 6 register transfer methodology -...
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Pinit Kumhom ENE 434 Digital System Design and Implementation 1
Lecture 6Register Transfer Methodology
Pinit Kumhom
VLSI LaboratoryDept. of Electronic and Telecommunication Engineering (KMUTT)
Faculty of EngineeringKing Mongkut’s University of Technology Thonburi
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Motivation
• Many problems can be solved algorithmically – performing a sequence of actions
• Algorithmic problem solving techniques become the cornerstone in computer science.– If a problem can be solved algorithmically, it can be implemented on a
computer.• An algorithm can be implemented as
– Software on a general computer (software implementation)– Hardware (hardware implementation)
• A hardware implementation of an algorithm is a digital system designed specifically to work following the steps of the algorithm.
• A register transfer methodology (RT methodology) is– a design methodology that describes system operation
• by a sequence of data transfers and • manipulations among register.
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What is an algorithm?
• Informally– a detailed sequence of actions or steps to accomplish a task
or solve a problem.• Formally in computer science
– a sequence of unambiguous instructions for solving a problem
• That is for obtaining a required output for any legitimate input in a finite amount of time
• Examples– Algorithm for setting up a home theatre set– Algorithm for adding (multiplying, dividing, etc) two
numbers– Algorithm for computing discrete Fourier transform (DFT)
of N points.
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How can we represent (describe) an algorithm?
• Using a natural language such as English, Thai, Loas, etc.
• Using a computer programming language such as C/C++, Java, etc
• Using pseudocode (chosen)
• Using a graphical representation such as flowchart
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Implementation of an AlgorithmSoftware implementation(Process of transforming the
algorithm to machine codes)• Choosing a machine and a
programming language• Coding a program: Translate the
algorithm representation to the chosen programming language
• Compiling and linking: Use a compiler software to translate the program to target machine codes and linked multiple codes together as one executable machine codes
• Running or executing: feed in an input and give the command for running or executing the program.
Hardware implementation(Process of transforming the
algorithm to a digital circuit)• Choosing a target technology
(ASIC/FPGA)• Follow the steps in a hardware
design methodology (design flow)
We’ll focus on a design methodology for algorithms that can be implemented on a conceptual hardware architecture composing from operating and transferring of data between registers (register transfer level abstraction)
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An example of transforming an algorithm to hardware
• Psuedocode representation of an algorithmAlgorithm Alg1Input: a -- an array of 4 elementsOutput: outp -- integer >= (sum of all elements)/8size = 4;sum = 0;for i in 0 to size-1 do {sum = sum + a(i);
}q = sum/8;r = sum rem 8;If r > 3 {
q = q+1;}outp = q;
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An example of transforming an algorithm to hardware
• Psuedocode representation of an algorithmAlgorithm Alg1Input: a -- an array of 4 elementsOutput: outp -- integer >= (sum of all elements)/8size = 4;sum = 0;for i in 0 to size-1 do {sum = sum + a(i);
}q = sum/8;r = sum rem 8;If r > 3 {
q = q+1;}outp = q;
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An example of transforming an algorithm to hardware
• The example shows– The use of variables
• Interpreted as a memory location with a symbolic address
• Used to store intermediate computation result
– Sequential execution• The execution of algorithm is performed sequentially
• Order of steps in the algorithm is important
• VHDL treat variables and sequential statements as a special case inside a process
– When synthesized to hardware, a variable is not interpreted as “a memory location” but as a signal.
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An example of transforming an algorithm to hardware
• Structural dataflow implementation– Transforming sequential
execution into structural dataflow
• Unroll the loop
• Interpreted variables as signals
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An example of transforming an algorithm to hardware
• Drawbacks of structural dataflow implementation
– It is not general and can apply to only a simple, trivial applications
• Larger size of array more hardware
• Variable size of array difficult to implement as structural dataflow
– Let n is another variable holding the size of the array.
– Hardware can not shrink or expand dynamically.
– Have to construct hardware for all possible n and use a multiplexer to route the desired value to output.
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Register Transfer Methodology
• Need hardware construct that resemble the variables and sequential execution model.
• The register transfer methodology (RT methodology) is aimed for this purpose.
• The key characteristics
– Use registers to store intermediate data and to imitate the variables used in algorithm
– Use a custom data path to realize the required register operation
– Use a custom control path to specify the order of register operation
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Register Transfer Methodology
• Registers are used as general storages that keep the intermediate computed values.Algorithm RT a = a + b use two registers, a_reg, b_reg
to store intermediate value of variables aand b respectively
• Necessary data manipulation and data routing are performed by dedicated hardware– the data manipulation circuit, routing network, and registers together are
known as the data path.
• Need a circuit to control when and what RT operations should take place.– the circuit is known as the control path, which can be realized by a
finite state machine (FSM).
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Register Transfer Methodology
• Typical RT implementation includes– a data path and
– a control path.
• We can use an extended FSM to describe the overall operations of RT implementation of algorithm – it is known as the FSM with a data path (FSMD)
• RT methodology – method of design
• RT level – module-level representation
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Overview of FSMD
Basic RT operation
• basic action in RT methodology is a register transfer operation– Notation: rdest ← f(rsrc1, rsrc2, ...,rsrcn)rdest: destination register (its content)rsrc1, rsrcn: source registers (their contents)
f(.) : a operation to be performed (must be realized by a combinational circuit)
‘←’ is not defined in VHDL
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Overview of FSMD
Basic RT operation• Few RT operations
– r ←1: the constant 1 is stored into the r register
– r ←r: the content of r register is stored back into itself – the content remains unchanged.
– r ←r << 3: the content of r register is shifted left by 3 positions and the result is stored back into itself.
– r0 ←r1 : the content of r1 register is stored (or transferred) into r0 register .
– n ←n-1 : the content of n register is decremented by 1 and the result is stored back into itself.
– y ←a ⊕b⊕c⊕d: the content of a,b,c,d registers are xored 1 and the result is stored into y register.
– s ←a2+b2: the contents of a and b are squared, the results are added, and the sum is stored into s register.
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Overview of FSMD
Basic RT operation
• The major difference between a variable of an algorithm and a register is that the system clock is embedded implicitly in an RT operation.
rdest ← f(rsrc1, rsrc2, ...,rsrcn)
1. At rising edge of the clock, new data from source registers are available after the clock-to-q delay of source registers
2. The data is computed by a combinational circuit that realizes the function f(.). We assume that the clock period is long enough to accommodate the propagation delay of the combinational circuit and setup time of the rdest register. The result is routed to input of the rdest register.
3. At the next rising edge of clock, the result will be sampled and stored into the rdest register.
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Overview of FSMD
Basic RT operation• Notations for discussing sequential circuits
– Use suffixes _reg, and _next for current output and next input to the register
r1 ← r1+r2 means
– r1_next <= r1_reg + r2_reg;
– r1_reg <= r1_next at the rising edge of the clock.
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Overview of FSMD
Basic RT operation
• Realization of a single RT operation
r1 ← r1+r2 = r1_next <= r1_reg + r2_reg;
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Overview of FSMDMultiple RT operations with data path• A destination register is not always loaded with the same data.
– r1 ← 1;– r1 ← r1+r2;– r1 ← r1+1;– r1 ← r1;
• A design with RT methodology normally involves many registers
• We can repeat this procedure for every register.
• The result constitutes the basic, unoptimizeddata path
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Overview of FSMD
FSM as the control path• A control path can be realized by a FSM• Naturally, FSM is matched for this task.
– The state of FSM is performed by a clock-by-clock basis –an RT operation can be specified in a state of the FSM
– An FSM can enforce a specific sequence of actions– FSM can branch to different paths depending on input
conditions – this can be used to implemented various branch constructs such as if and loop statements in an algorithm
• Since an RT operation is performed in each state, we can extend to FSMD to indicate the desired RT operations in each states.
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Overview of FSMD
ASM chart
• State representation and state transition of FSMD is similar to those of FSM
• In addition, RT operations are specified in states or transition arcs
• FSM can be represented by a state diagram or an algorithm state machine (ASM) chart
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Overview of FSMD
Basic FSMD block diagram
Data path: 3 major parts
- Data registers- Functional units- Routing networks
Input signals- data input- control signal
Output signals- data output- internal status
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Overview of FSMD
Basic FSMD block diagram
Control path: 3 major parts
- State registers- Next-state logic- Output logic
Input signals- command- internal status
Output signals- control signal- external status
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FSMD Design Example: A Repetitive-Addition Multiplier
1. Converting an algorithm to ASMD chart
1.1 Converting while loop using ifand goto statements
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FSMD Design Example: A Repetitive-Addition Multiplier
1. Converting an algorithm to ASMD chart
1.2 Defining its input and output signals
Input signals
• a_in and b_in: input operands. 8-bit
signal interpreted as unsigned integers
• start : command
• clk : system clock
• reset : asynchronous reset signal
for system initializationOutput signals
• r_out : the product. 16-bit unsigned integer
• ready : external status signal
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FSMD Design Example: A Repetitive-Addition Multiplier
1. Converting an algorithm to ASMD chart
1.3 Draw the ASMD chart
• How many states? What does it do in each states?
- Data operations output
- External status
- State transition
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FSMD Design Example: A Repetitive-Addition Multiplier
2. Construction of FSMDDerive more detailed conceptual diagram from the ASMD chart
• Separating data path and control path
• The construction of the control path is the FSM already described in the ASM
• The construction of the data path
1. List all possible RT operations in the ASMD chart
2. Group RT operations according to their destination registers
3. For each group derive the circuit (see slide 18-19)
4. Add necessary circuits to generate the status signal
(a) Construct the destination register(b) Construct combinational circuit involved in each RT operations(c) Add multiplexing and routing circuits if destination register is associated with multiple RT operations
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FSMD Design Example: A Repetitive-Addition Multiplier
2. Construction of FSMDDerive more detailed conceptual diagram from the ASMD chart
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Derive more detailed conceptual diagram from the ASMD chart
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FSMD Design Example: A Repetitive-Addition Multiplier
2. VHDL Description of a FSMD: Multi-segment
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FSMD Design Example: A Repetitive-Addition Multiplier
2. VHDL Description of a FSMD: Multi-segment
Control path: state register
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FSMD Design Example: A Repetitive-Addition Multiplier
2. VHDL Description of a FSMD: Multi-segmentControl path: next-state logic/output logic
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FSMD Design Example: A Repetitive-Addition Multiplier
2. VHDL Description of a FSMD: Multi-segmentData path: data registers
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FSMD Design Example: A Repetitive-Addition Multiplier
2. VHDL Description of a FSMD: Multi-segmentData path: Network routing
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FSMD Design Example: A Repetitive-Addition Multiplier
2. VHDL Description of a FSMD: Multi-segment
Data path: functional units/ internal status
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FSMD Design Example: A Repetitive-Addition Multiplier
Use of a register value in decision box• Key to realizing RT methodology is to derive an efficient and correct ASMD
• The most subtle part of deriving is using a register in Boolean expressions of the decision box.
• We intentionally avoided this in the previous ASMD of the example – using signals namely a_is_0, b_is_0 and count_0
• For the case of a_is_0 and b_is_0, it is easily improved by using a_in = 0 and b_in = 0, respectively.
• For the case of count_0, it is more subtle.
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FSMD Design Example: A Repetitive-Addition Multiplier
Use of a register value in decision box•.The count_0 is ‘1’ when the counter output reaches 0.
• In pseudocode, it is expressed as
Translated directly to a ASM box as
Problems with this translation
• the old value of register n is used in the decision box because the new value, n-1, is updated when exiting the box.
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FSMD Design Example: A Repetitive-Addition Multiplier
Use of a register value in decision box•.The count_0 is ‘1’ when the counter output reach 0.
• In pseudocode, it is expressed as
Translated directly to a ASM box as Solution 1: Check whether n=1 instead of n=0
Problem: may not work with other algorithms when the condition of the previous condition may not be determined.
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FSMD Design Example: A Repetitive-Addition Multiplier
Use of a register value in decision box•.The count_0 is ‘1’ when the counter output reach 0.
• In pseudocode, it is expressed as
Translated directly to a ASM box as Solution 2: add an artificial wait statement
Problem: introduce one extra clock cycle.
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FSMD Design Example: A Repetitive-Addition Multiplier
Use of a register value in decision box•.The count_0 is ‘1’ when the counter output reach 0.
• In pseudocode, it is expressed as
Translated directly to a ASM box as Solution 3: Use the next value of the register for checking
- assigned the next value of n to a signal, n_next
- the n_next is updated to register n when exiting.
Stress that this operation is a combinational circuit.
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FSMD Design Example: A Repetitive-Addition Multiplier
Four-segment coding styleControl path
1. Keep the state registers the same
2. Combing next-state and output logic
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FSMD Design Example: A Repetitive-Addition Multiplier
Four-segment coding style
Data path
1. Keep the data registers the same
2. Combing data operation and the network routing
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FSMD Design Example: A Repetitive-Addition Multiplier
Two-segment coding style1. Register segment: Combining the state and data registers
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FSMD Design Example: A Repetitive-Addition Multiplier
Two-segment coding style2. Combinational segment:Combining the next-state logic, output logic, data operations, and networking routing
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FSMD Design Example: A Repetitive-Addition Multiplier
Shared resource via FSMD
• ปกตแลว Functional blocks จะซบซอน
• สามารถใชทรพยากรรวมดวย time-multiplexing
• ตองม scheduling ทจะไมทาใหการกระทาทตองใชรวมกนเกดขน ณ. สถานะเดยวกน
• สาหรบตวอยาง การคณดวยการบวกตวตงซา ๆ เราม Functional blocks คอ 16-bit adder และ 8-bit decrementor
• สามารถใชทรพยากร 16-bit adder เพยงตวเดยว แตตองแยกสถานะ op ออกเปน 2 สถานะ
op1: ใช 16-bit adder เพอการบวกซา (r_reg + a_reg)
op2: ใช 16-bit adder เพอการลดคาของ n_reg ลงไปหนงคา
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FSMD Design Example: A Repetitive-Addition Multiplier
Shared resource via FSMD
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FSMD Design Example: A Repetitive-Addition Multiplier
Shared resource via FSMD
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FSMD Design Example: A Repetitive-Addition Multiplier
Shared resource via FSMD
ใช two-segment coding style แตแยกสวนของ function block ทมการใชรวมออกตางหาก
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FSMD Design Example: A Repetitive-Addition Multiplier
Shared resource via FSMD Next-state/output logic และ data path routing
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FSMD Design Example: A Repetitive-Addition Multiplier
Shared resource via FSMD
แยกสวนของ function block ทมการใชทรพยากรรวมออกมา
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FSMD Design Example: A Repetitive-Addition Multiplier
Mealy-controlled RT operations
• Mealy output เปนเอาทพทเหมาะกบการควบคมแบบ edge-sensitive
• เนองจาก data path และ control path ตองทางานสอดคลองกนภายใตสญญาณนาฬกาเดยวกน สญญาณควบคมจาก control path ไปควบคม data path จะตองเปน edge-sensitive control signal จงเหมาะทใช Mealy output
• ใน FSMD การใช Mealy output ในการควบคมหมายถง ม RT operations ททางออกของ decision box
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FSMD Design Example: A Repetitive-Addition Multiplier
Mealy-controlled RT operations
แสดง RT operations ททางออกของ decision box
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FSMD Design Example: A Repetitive-Addition Multiplier
Mealy-controlled RT operations ตวอยาง การคณแบบบวกตวตงซา ๆ
• ใน ASMD chart เดมนนการโหลด a_in และ b_in จะเกดขนใน ab0 หรอ load ซงหมายความวาคาของ a_in และ b_in จะอยใน a_reg และ b_reg หลงจากสถานะทงสอง
• เราตองการนาคาเหลานมาเชค นนหมายความวา หนวยภายนอกทเปนตวสงอนพทมาใหตวคณจะตองรกษาคาของอนพทนไว 2 clocks ตดกน
• แกไขโดยการรวบเอา idle, ab0, และ load ไวเปน state เดยวแลวใช mealy-type control ในการแยกการกระทาทแตกตางกน
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FSMD Design Example: A Repetitive-Addition Multiplier
Mealy-controlled RT operations ตวอยาง การคณแบบบวกตวตงซา ๆ
ใช two-segment coding style
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FSMD Design Example: A Repetitive-Addition Multiplier
Mealy-controlled RT operations ตวอยาง การคณแบบบวกตวตงซา ๆ
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Timing and Performance Analysis of FSMD
• FSMD เปน synchronous circuit จงตองอยภายใตเงอนไขทางเวลาของรจสเตอรคอ Tcq, Tsetup และ Thold เชนเดยวกบ FSM
• สงท FSMD แตกตางจาก FSM ธรรมดาคอการทางานทสมบรณของ FSMD หมายถง RT operations ทางานตามลาดบจนไดเอาทพททตอบสนองตออนพท เชน FSMD ของตวคณจะสมบรณเมอผลคณทถกตองปรากฏทเอาทพท ซงโดยทวไปตองใชหลาย clock
• ตววดสมรรถนะของ FSMD จงไมใชอตราความเรวของ clock เพยงอยางเดยว เราตองดจานวน clock ทใชกวาจะไดเอาทพทดวย
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Timing and Performance Analysis of FSMD
Maximal clock rate
• ถาดจาก basic block diagram ของ FSMD และ FSM ธรรมดาตางกนท FSMD ม feedback loop 2 loops ซงเปน feedback loop ทตอบโตกน
• ในทางทฤษฎทงสอง loop สามารถรวมเปน 1 ไดแลววเคราะหเหมอนกบ FSM
• ในทางปฏบต เปนการยากทจะวเคราะหวงจรทรวม loop นดวยมอ ตองอาศยซอฟทแวรชวยวเคราะหดานเวลา และอตราความเรวสญญาณนาฬกาสงสด
• แมการวเคราะหดวยมอจะไมสามารถบอกอตราความเรวสงสดของสญญาณนาฬกา แตเราสามารถหาขอบเขตของมนได
• การวเคราะหดวยมอเชนนสามารถชวยเราเหนเชงลกของสงทเราออกแบบ และชวยใหเราสามารถปรบปรงประสทธภาพใหดขนได
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Timing and Performance Analysis of FSMD
Timing parameters ของ control path (เชนเดยวกบ FSM ทวไป)
Timing parameters ของ data path
Maximal clock rate: วเคราะหดวยมอสาหรบ best-case และ worst-case
Tc: clock period
โดยทวไป Tfunc จะเปนตวทมคาสงสด (เราจะใชสมมตฐานนในการวเคราะห)
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Timing and Performance Analysis of FSMD
Maximal clock rate: วเคราะหดวยมอสาหรบ best-case
Toutput และ Tnext overlap กบ Tdp
Tc = Tcq(data) + Tdp + Tsetup(data)
เงอนไข• ตองการ control signal ทหลง
• สราง status signal ไดกอน
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Timing and Performance Analysis of FSMD
Maximal clock rate: วเคราะหดวยมอสาหรบ best-case
Toutput และ Tnext อนกรม กบ Tdp
Tc = Tcq(state) +Toutput+ Tdp +Tnext+ Tsetup(state)
เงอนไข• ตองการ control signal กอน
• ได status signal ทหลง
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Timing and Performance Analysis of FSMD
ขอบเขตของคาบของสญญาณนาฬกา
Maximal clock rate: วเคราะหดวยมอสาหรบ best-case และ worst-case
ซงจะไดขอบเขตของความเรวของสญญาณนาฬกา
โดยทวไปแลว Tdp >> Toutput + Tnext อตราความเรวสงสดกบตาสดไมตางกนมากนก
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Timing and Performance Analysis of FSMD
• สมรรถนะของ FSMD วดจากเวลาทใชทางานใหเสรจ 1 งาน ซงคานวณไดจาก
Ttotal = K*Tc
เมอ Tc เปนคาบของสญญาณนาฬกาและ K เปนจานวนของสญญาณนาฬกาทใชเพอทางานใหเสรจ
• คา K ขนอยกบ algorithm
• การวเคราะหหาคา K เปนแบบ ad hoc (ไมมระบบ)
- บางครงวเคราะหยากมาก
- บางกรณ K และ Tc เปนคาทขนตอกน เชน ลด Tc จะเพม K
Performance Analysis
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Timing and Performance Analysis of FSMD
• วงจรแรก: คา K ของวงจร repetitive-addition multiplier จะไมคงทเพราะขนอยกบคาของตวคณ (K = B + 2, เมอ B เปนคาของตวคณ)
- กรณทดทสดคอ B=0, K=2
- กรณทแยทสดคอ B=2n-1 (n = จานวนบทของขอมล), K = 2n + 1
• วงจรทสอง (resource sharing): คา K = 2B + 2
- กรณทแยทสด K = 2*2n+1
• วงจรทสาม (Mealy control): คา K = B + 1
Performance Analysis: Repetitive-addition multiplier
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Sequential Add-and-Shift Multiplier
• สมรรถนะของ repetitive addition multiplier แปรตาม 2n, เมอ n เปนจานวนบทของอนพท ซงใชไมไดในทางปฏบตเมอ n มคามาก
• Sequential add-and-shift multiplier สามารถปรบปรงสมรรถนะของตวคณเลขจานวนเตมใหแปรตาม n
ขนตอนการคณ
1. คณแตละบทของตวคณ (b3, b2, b1, b0) กบตวตง (A) ทละตวเพอทจะได b3*A, b2*A,
b1*A, b0*A การคณนทาไดดวย bitwise AND
2. Shift bi*A ไปทางซาย i ตาแหนง
bi*A = (bia3, bia2, bia1, b0a0)
3. บวกเทอม bi*A ท shift ไปแลวเขาดวยกน
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Sequential Add-and-Shift Multiplier
1. เปลยนขนตอนการคณเปน pseudocode ดงน
Initial Design
pseudocode ทดกวา
เปลยน while loop เปน goto
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Sequential Add-and-Shift Multiplier
Pinit Kumhom ENE 434 Digital System Design and Implementation 67
Sequential Add-and-Shift Multiplier
Pinit Kumhom ENE 434 Digital System Design and Implementation 68
Sequential Add-and-Shift Multiplier
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Sequential Add-and-Shift Multiplier
Initial Design Conceptual hardware
Performance analysis: Ttotal = KTc
- Worst case (multiplicand = “11..1”) (add-shift in every iteration): K = 2n + 1
- Best case (multiplicand = “00..0”) (no adding in every iteration): K = n + 1
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Sequential Add-and-Shift Multiplier
1. RT operation ในสถานะ add และ shift เปนอสระตอกน สามารถรวมไปอยในสถานะเดยวกนได โดยการนา p ← p + a ไปไวหลง decision box ทาใหสามารถทาแตขน iteration ไดภายใน 1 clock
2. ใน initial design เราตองใชตวบวกขนาด 2n บทเพราะ p มขนาด 2n บท แตในการบวก p + a นน มการบวกจรงเพยง n บท จงสามารถใช (n+1)-bit adder (ตองเพมอก 1 บทเพอรองรบการทดในบทสดทาย) ในการบวกไดซงเปนการเพมประสทธภาพของ data path
- ใช routing network ซบซอน เปลอง ไมคม
- ใชการ shift p ทละบทใหตรงกบ a (ประหยด เรว ด)
Refined Design
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Sequential Add-and-Shift Multiplier
Refined Design
Conceptual hardware
ปรบปรงตอไดโดยใชสวนดานขวาของ p ในการเกบ b แทนทา
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Sequential Add-and-Shift Multiplier
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Sequential Add-and-Shift Multiplier
Refined Design
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Sequential Add-and-Shift Multiplier
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Comparison of the three sequential multipliers
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Synthesis Guidelines
• ทาตาม guidelines สาหรบ FSM• Guidelines เพมเตม
– แยกรจสเตอรของ FSMD ออกมาจาก combinational circuits– จาไวเสมอวา RT operation มพฤตกรรมเปน delay-stored การใช
register ภายใน decision box ควรจะตองตรวจสอบอยางถถวน– ตวแปรทใชใน Boolean expression ของอลกอรธม มกจะเทยบเทา
กบ คาตอไปของรจสเตอรทใชเกบตวแปรนน– Function units มกจะเปนหนวยทมความซบซอนสงสดของ FSMD
เราอาจจาเปนตองแยกสวนนออกจาก combination circuit อน ๆ– ถาจาเปนตองการ optimization ของ FSM ภายหลง ใหแยกสวนของ
control path ออกจาก data path