lecture 5 static cmos gates jack ou, ph.d.. 2-input nor gate f can only be pulled up if a=b=0 v f...
TRANSCRIPT
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Lecture 5
Static CMOS GatesJack Ou, Ph.D.
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2-Input NOR Gate
F can only be pulled upif A=B=0 V
F can be pulled down byeither A=1 or B=1. (Or Both)
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2-Input NAND Gate
F can only be pulled down if both A=B=1.
F will be pulled up if either A or B is 0 V.
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NAND Gates
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NOR Gates
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2-Input AND GateNAND
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2-Input OR GateNOR
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Alternative Implementation for High Fanin Gates
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Steps for Generating Non-Trivial Static CMOS Logic Circuits
1. Implement the pull-down (NMOS)circuit using –Useful technique: DeMorgan’s Theorem
2. Synthesize the dual of the pull-down circuits using PMOS
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DeMorgan’s Theorem
• The complement of a function can be obtained by– Replacing each variable with its complement– Exchange the AND and OR functions
• Example– +
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Dual
• The dual of any logic function can be obtained by exchanging the AND and OR operations.– ab ↔a+b– (a+b)c ↔ab+c
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A fictional AND Circuit
The current flows only when both A and B are closed.
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Fictional OR Circuit
The current flows when either A or B is closed.
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Implementation
• Use transistors in series to implement a logical AND function
• Use transistors in parallel to implement a logical OR function
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OAI Circuit ()
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XOR/XNOR
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Mux
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Determine a Boolean Expression a Schematic
1. Determine implemented by a NMOS pull-down network.
2. Complement to obtain F.
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2-Input XOR
𝐴 0 𝐴1
𝐴 0 𝐴1
(A0+A1)
𝐴 0 𝐴1(A0+A1XNOR
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CMOS Gate Sizing
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Device Sizing
• Obtain the same delay as the inverter for the rise/fall cases.– ReffN=12.5 Kohm/SQ, ReffP=30 Kohm/SQ
– Reff=Reff(L/W)
– ReffP/ReffN=2.4
– To achieve the same delay, (assume LP=LN, WP=2.4WN, WP/WN is approximately 2.
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Size Devices for the Worst Case
• Series transistors: Increase W to reduce Reff.
• Parallel transistors: assume the worst case, i.e. only one of the parallel transistor is ON.
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Transistor Sizing Without Velocity Saturation
Figure 5.2Assumption: Equal rise delay and fall delayConsideration: Effective Resistance
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Inverter
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Inverter tPHL
tPHL=64.045 pS
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NAND2 Test Circuit
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NAND2 tPHL
tPHL=66.01 pS
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Effective Width
• Transistors in Series– W1||W2||W3
• Transistors in Parallel– W+W2+W3
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Trade-Off
Increase W to reduce the effectiveResistance for the pull down network.
The area is increased.
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FO4
Fanout ratio: total capacitance driven by a gate dividing by its input capacitance
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VTC of Gates
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Adjust VS
• Knob:– χ as defined in EQ. 4.15– Increase WNLP/LNWP to decreased VS.
– Decrease WNLP/LNWP to increased VS.
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Switching Voltage of a NAND Gate
Both inputs tied together: effective WN=W, WP=4W, VS shifts to the right.Both input A=high, sweep VB: effective WN=2W, WP=2W, VS shifts to the left.
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Switching Voltage of a NOR Gate
Both inputs tied together: effective WN=2W, WP=2W, VS shifts to the left.Both input A=ground, sweep VB: effective WN=W, WP=4W, VS shifts to the right.