lecture 4 the cmos inverter...2018-09-13 lecture 4: cmos inverter dynamics 3 . . . and saturaon...

Lecture4TheCMOSInverter

Dynamicproper9es

Week2:TheCMOSinverter•  Tuesday

–  Sta9cproper9es•  Voltagetransfercurves(VTC)•  Noisemargins

–  Exercise(Kjell,1hour)•  Thursday

–  Dynamicproper9es•  Propaga9ondelay•  Drivinglargecapaci9veloadsw.op9malpropaga9ondelay

–  ExercisePOTW(Victor,2hours)•  Friday

–  Prelab1deadline1PM

2018-09-11 MCC092ICDesign-Lecture3:TheInverter 2

Last9me?Muddy?

•  Howswitchingvoltageiscalculated•  NOR/NANDgateVTC•  Noisemargins

– Howcalculatethem– Aretheyaccuratefromsimplifiedmodels?– Wheredoes1/8comefrominnoisemarginexample?–  Bu^erflydiagram

•  Coxwhatisthat?

2018-09-13 Lecture4:CMOSInverterdynamics 3

...andsatura9oncurrentsareequal:

VoltageTransferCharacteris9c-VTC

2017-09-05 MCC092ICDesign-Lecture3:TheInverter 6:3

VIN

VOUT

VDD

NMOSOFF

PMOSOFF

VDS

IDS

Satura&on:IDSP,N=IDSAT,P

( ) ( )2 22 2N P

IN TN DD IN TPk kV V V V V− = − +

1DD TP TN

swV V xVV

x+ +

=+

VSWVSW

Inverter

IDS

( )2, 2P

DSAT P DD IN TPkI V V V= − +

( )2, 2N

DSAT N IN TNkI V V= −

VSW VDD,VDD

SwitchingoccursinthegreenregionwherebothMOSFETsaresaturated...

VDD

Switchingmeans:VIN=VOUT

SolvingforVINusingx=kN/kPyields

Noisemargins


NoiseMargins–anexample


VINVDD

VOUT

VDD

00

VIL,max VIH,min

VOH,min

Valid”0”

Valid”1”

Formulascanbederived(forx=1):VOH,min=VDD-ΔV/8VOL,max=ΔV/8VIL,max=VSW-ΔV/8VIH,min=VSW+ΔV/8

0.28V 0.28VΔV=0.64V

ΔV/8

ΔV/8

ΔV/8ΔV/8Formulascanbederived(forx=1):VOH,min=VDD-ΔV/8=1.12VVOL,max=ΔV/8=80mVVIL,max=VSW-ΔV/8=0.52VVIH,min=VSW+ΔV/8=0.68V

Forx=1,VTN=0.28VandVTP=-0.28VwehaveVSW=0.28+0.64/2=0.60VandΔV=0.64V

VOL,max

Thesepointsyieldsnumbersfor(VOH,min,VIL,max)and(VOL,max,VIH,min)sothatNMHandNMLcanbecalculated!

NMH=VOH,min-VIH,minNML=VIL,max-VOL,maxNMH=VOH,min-VIH,min1.12-0.68=0.44VNML=VIL,max-VOL,max=0.52-0.08=0.44V

Let´sdefinevalidregionsfrompointswhereslopeAV=-1!

VDD=1.2V

Quickques9on

•  Haveyoutriedsolvingprelab3yet?


Sta9cvsdynamic


Last9me:staGc(DC)behaviorInput:DCvoltage,Output:DCvoltage

This9me:dynamicbehaviorThatis,with9meInput:voltagewaveformOutputvoltagewaveform

VDD

VIN

ON

OFF

VOUT

VDD

VIN

ON

OFF

VOUT

VOUT=1.2V VIN=0.2V

Incircuitsimula9on:DCanalysis Incircuitsimula9on:transientanalysis

CL

Outline•  Defini9ons

–  Rise9meandfall9me–  Propaga9ondelay:Risedelayandfalldelay

•  Propaga9ondelayes9ma9on–  Stepresponsemodel

•  Charginganddischargingtheloadcapacitor–  Rampresponsemodel

•  IntroducingtheMOSFETeffec9veresistance•  Invertercapacitances

–  Modelforscaledinverter:effec9veresistanceandcapac9ance•  Inverterpairdelay

–  Normalizingtheinverterdelaywrtτ=0.7RC•  Delayw.morethanoneinverter

–  Inverterpairdelay–  Thefanout-of-four(FO4)delay–  Thetaperedbuffer,findingsizesandnumberofinverters–  (Buffers/driverswithbranching)


Defini9onsforwaveforms


VIN

Time,t

100%

tr tf

20%

80%

0

Inputsignaldefini9ons:riseandfallGmes

FallingedgeRisingedge

Defini9onsfordelay


VIN

Time,t

100%

tpdf

50%

0

Propaga9ondelaydefini9ons:riseandfalldelays

VOUT

Time,t

100%

50%

0

tpdr

Propaga9ondelaysaredefinedatthe50%level!

Step-responsemodel


VIN

Time,t

100%

tpdf

50%

0

VOUT

Time,t

100%

50%

0

tpdr

Outputfalldelay Outputrisedelay

VSS

VDD VDD/2

IDS,P

VOUT

IDSAT,P

pMOScurrentflowindetail

VDD

VIN

ON

OFF

VIN=LOW VOUT

,OUT

DSAT P LdVI Cdt

=

CL

Step-responsemodel


1.Chargingtheloadcapacitorthroughthep-channelMOSFET

,

/ 2DDpdr L

DSAT P

Vt CI

=Outputrisedelay

VINgoesLOW

VOUTgoesHIGH

Step-responsemodel


VDD

VSS

CL

VIN VOUT

2.Dischargingtheloadcapacitorthroughthen-channelMOSFET

OFF

ON

VIN=HIGH

,

/ 2DDpdf L

DSAT N

Vt CI

=Outputfalldelay

,OUT

DSAT N LdVI Cdt

= −

VDD VDD/2

IDS,N

VOUT

nMOScurrentflowindetail

IDSAT,N

VINgoesHIGH

VOUTgoesLOW

Step-responsemodelaccuracy

•  Howgoodisthestep-responsemodel?–  Realworldinputvoltagesarenotstepfunc9ons–  Theyareoutputvoltagesfromothergates


StepresponsemodelaccuracyExperienceandhundredsofcircuitsimula9onsshowthatpropaga9ondelaysareabout40%longerindesignswhereinputandoutputedgeratesareequal


/ 2DDpd L

DSAT

Vt CI

=

0.7 DDpd LDSAT

Vt CI

=

Themostimportantequa9on


0.7 DDpd LDSAT

Vt CI

=

Rampinput–outputtrace


VGSrisesfrom0toVDDVIN:

VGS=0

VGS=VDD

Somedischargehappenswhileinputrisesfrom0toVDDMostdischarges9llhappenswithIDSAT,max

Effec9veresistances:65nmMOSFETs


Reff=VDD/IDSAT,maxReff=VDD/IDSAT,max

RN,eff=2kΩ.µm RP,eff=4kΩ.µm

IDSAT,max=

600µA/µm

VDD=1.2V

N-channeldevice P-channeldevice

IDSAT,max=

300µA/µm

VDD=1.2V

IDS

VDS

IDS

VDSVDD VDD

0.7 DDpd LDSAT

Vt CI

= 0.7pd eff Lt R C=

Themostimportantequa9onrevisited


t pd = 0.7CLReff

RCdelay


0.7pd eff Lt R C=

VOUT

VSS

CL

VDD

Reff

ThisRCcircuithasanoutputvoltagedelaygivenby

Rampinput–outputresponse


Thetwocurveformsarenotthesame,buttheyyieldthesamedelay!

MOSFETcapacitances(fromlecture2)


STI STI

L,thechannellength

drain source

LD LS

Cbo^om

Csidewall

Cbo^om

Csidewall

L

Metalgate

Siliconsubstrate

W,thechannelwidth

Thereisadistributedgatecapacitancethatmustbelumpedtototheavailablecktnodes,thatis,sourceanddrain

Thereareparasi9ccapacitancesfromsource/draintosubstrate

LS

LD

W

65nmCMOScapacitances

September2018 MCC092-TheMOSFET 24

GatecapacitancePlatecapacitancebetweengateandchannel(butherewemodelitbetweengateandsource)CG=WLCoxCox≈20fF/μm2(correspondsto1.2nmeffec9veoxidethickness,tox)60nmeffec9vechannellengthyields:CG=1.2fF/μmDrain/sourceparasiGccapacitancesSameorderofmagnitudeasthegatecapacitance,CS=CD=pinvCGGenericapproachistousepinv=1forsimplicityButsome9mespinv=0.5orpinv=0.8!

channel length,L

ElectricalmodelforsaturatedMOSFET(fromlecture2)


VG VD

VS VS

IDSAT

ModelforsaturatedMOSFETValidforbothnMOSandpMOStransistors

CD CG

Theinverteranditselectricalmodel


ReplacetheMOSFETswiththeirequivalentelectricalcircuits!

VIN VOUT

VSS

VDD

NMOS

( )22N

DSN IN TNkI V V= −

VIN VOUT

VSS

CGN

CDN

VSS

IDSN

IDSN

IDSP = −kP2VIN −VDD −VTP( )

2

PMOS

VDD

CGP

CDP

VDD

IDSP



VIN VOUT

VSS

VDD

NMOS

( )22N


VIN VOUT

VSS

CGN

CDN

VSS

IDSN

IDSN

ISDP =kP2VDD −VIN +VTP( )

2

PMOS

VDD

CGP

CDP

VDD

ISDP

ChangethesignofthepMOScurrentsothatallcurrentsareposi9ve(WealsomadethepMOSvoltagesposi9ve,althoughitisnotnecessary)


Placeallcapacitorstosignalground!Bothrailsareconstantvoltages,nodV/dt

VIN VOUT

VSS

VDD

( )22N


VIN VOUT

VSS VSS

IDSN

IDSN

ISDP =kP2VDD −VIN +VTP( )

2

VDD VDD

ISDP

CG=CGN+CGP

Inverterinputcapacitance:CG=CGN+CGP;MOSFETgatecapacitancesadd!Inverterparasi9coutputcapacitance:CD=CDN+CDP.Draincapsalsoadd!


CD=CDN+CDP



EliminateVDDrailbyinser9ngpowersupplytosignalground!

VIN VOUT

VSS VSS

IDSN


VIN VOUT

VSS

VDD

CG=CGN+CGP

CD=CDN+CDP

ISDP VDD



ReplaceMOSFETconstant-currentsourceswiththeireffec9veresistances!

VIN VOUT

VSS VSS

RN,eff


VIN VOUT

VSS

VDD

CG=CGN+CGP

CD=CDN+CDP

RP,eff

VDD




Toocumbersometohavedifferentriseandfalldelays! Replaceeffec9veresistanceswithoneaverageeffec9veresistance!

VIN VOUT

VSS VSS


VIN VOUT

VSS

VDD

CG=CGN+CGP CD=CDN+CDP

VDD


Reff=3kΩ.µmW=1

W=1



Toocumbersometohavedifferentriseandfalldelays! Replaceeffec9veresistanceswithoneaverageeffec9veresistance!

VIN VOUT

VSS VSS

RN,eff=2kΩ.µm


VIN VOUT

VSS

VDD

CG=CGN+CGP CD=CDN+CDP

VDD

Orevenbe^er!Designtheinverterforequaleffec9veresistances,RP,eff=RN,eff,bymakingp-channelMOSFETtwiceaswideasthen-channel

MOSFETtocompensateforthelowerholemobility W=2

W=1

Invertercapacitances


VIN VOUT

VSS

VDD

VIN VOUT

VSS VSS

CG=3.6fF/µm CD=pinvCG VDD

W=2

W=1

Task:CalculateCGandCDwithpMOSFETistwiceaswideasnMOSFETexpressedinthewidthofthenMOStransistor.

Answer:AssumingL=60nmandCox=20fF/µm2weobtainCGN=1.2fF/µmandCGP=2.4fF/µm.HenceCG=3.6fF/µm.ConcerningCDweassumeCD=pinvCG=3.6fF/µmwithpinv=1.

RN,eff=2kΩ.µm

Weno9cethatCG×RN,effisaconstant.Itwillsoonreturn!

Morethanoneinverter


Inverterpairdelay


Reff

VDD

Task:Calculatetheinverterpairdelay!

Inverterpairdelay


CG

Reff

VDD

Putonyour“two-portglasses”andlooktowardstheloadinginverter!Youwillonlyseetheinputcapacitanceoftheloadinginverter

Inverterpairdelay


Reff

CD

VDD

CD

Haveyour“two-portglasses”onandlooktowardsthedrivinginverter!Youwillseeavoltagesourcewithacertainsourceresistance,andyouwillsee

theparasi&ccapacitanceoftheloadinginverter

Inverterpairdelay


Reff

VDD

Inanidealinverterthe9meconstanttauisreallywhatthenamesays,aconstant;Itisindependentofinvertersize(aslongasWP/WN=2).

CG

CD

Propaga9ondelay:( ) ( )0.7 0.7 1 5 ps 2 10 pspd eff D G eff G invt R C C R C p= + = + = × =

Alldelaycalcula9onsaremadewrttothistechnology9meconstanttau(𝜏)

( ) ( )0.7 0.7 2 k µm 3.6 / µm 5 pseff GR C fFτ = = × Ω× × =

Inverterpairdelay


Reff

VDD

Propaga9ondelay:( ) ( )0.7 0.7 1 5 ps 2 10 pspd eff D G eff G invt R C C R C p= + = + = × =

Alldelaycalcula9onsaremadewrttothistechnology9meconstanttau(𝜏)

( ) ( )0.7 0.7 2 k µm 3.6 / µm 5 pseff GR C fFτ = = × Ω× × =

Equivalentelectricalcircuitforpropaga9ondelaycalcula9ons

CG

CD

VOUT

Importantconcept


Thetechnology9meconstanttau,𝜏:

⌧ = 0.7Re↵CG

Quiz9me!


– Gotosocra9ve.com– SelectStudentlogin– Gotoroom:“MCC0922018”

InverterFO4delay


TheFO4propaga9ondelayinour65nmprocess:

t pd = 0.7Reff CD + 4CG( ) = 0.7ReffCGtau

! "# $#p+ 4( ) = 5 ps×5= 25 ps

X1

X1

X1

Reff

CD

VDD

X1X1

CG

CG

CG

CG

Oneinverterdrives4iden9calinverters

NormalizedFO4delay


⌧ = 0.7Re↵CG

tpd = (pinv + 4)⌧ ⇡ 5⌧Normalizeddelaymeansnormalizedto𝜏

X1

X1Reff CD

VDD

X1X1

CG

CG

CG

CG

d ⌘ tpd⌧

d ⇡ 5SoFO4normalizeddelay:

X1

Importantconcept


Thenormalizeddelay,d:

d ⌘ tpd⌧

Wheretau,𝜏,isthetechnology9meconstant,𝜏

FO4delaytrendsvs.featuresize


1µm 1/4µm 0.13µm 65nm 22nm0.5µm 32nm

Microprocessorcycle9metrends


From Weste & Harris.

InverterSize

•  Inmostvendorcelllibraries,invertersandotherlogicgatescomeinanumberofdifferentvarie9esconcerningtheirdrivingcapability(Reff)andinputcapacitance(CG).

•  Inthefollowingallinvertersandlogicgatesofacertainsize,e.g.sizeX=8,willhavethesameinputcapacitance,and,asanexample,thisinputcapacitancewillbeonlyhalftheinputcapacitanceofagateofsizeX=16.


Minimizingdelaythroughmul9pleinverters


Pathdefini9ons


Reff/x1 Reff Reff/x2 CL=HC

x1C x2C Histhepathelectricaleffort C

Pathelectricaleffort:H=CL/CINStageelectricaleffortorfanoutforinvertern:hn=CINn+1/CINn=xn+1/xnNormalizeddelayforinvertern:dn=hn+pinvNormalizedpathdelaywithNstages:D=N×pinv+h1+h2+…+hN

Thetaperedbufferwith3stages


Referenceinverter... andtwoinsertedbufferinverters

C

Normalized path delay: D = 3 pinv + h1 + h2 + h3 where h1=x1, h2=x2/x1 and h3=H/x2. But only h1 and h2 are independent variables, h3 becomes h3=H/h1h2:

D = 3 pinv + h1 + h2+ H/h1h2

Show that minimum delay is obtained for h1=h2=3√H, which gives:

Dmin = 3 pinv + 3 × 3√H

Sizex1 Size=1 Sizex2

Reff/x1 Reff Reff/x2 CL=HC

x1C x2C Histhepathelectricaleffort

Hint: ddh1D h1,h2( ) = 0, and

ddh2

D h1,h2( ) = 0

yields h1 = h2 and h3 = H / h1h2 → h = h1 = h2 =h3 = H3

ExamplewithpathelectricaleffortH=64

Thetaperedbufferwith3stages


Referenceinverter... andtwoinsertedbufferinverters

C

Normalized path delay: D = 3 pinv + h1 + h2 + h3 where h1=x1, h2=x2/x1 and h3=H/x2. But only h1 and h2 are independent variables, h3 becomes h3=H/h1h2:

D = 3 pinv + h1 + h2+ H/h1h2 Example: H = 64

Minimum delay is obtained for h1=h2=3√64=4 gives D = 3(pinv+4)=15 with pinv=1

Sizex1=4 Size=1 Sizex2=16

Reff/4 Reff Reff/16 CL=64C

4C 16C

ThetaperedbufferwithNstages

•  Whatifthepathelectricaleffort,forsomereason,isverylarge,e.g.H=4096.

•  Howmanyinverters,N,areneededtominimizethedelay?


CL=HC C

Size=1 LargepathelectricaleffortH=4096=212

MinimumpathdelayD=N(pinv+h)?DeterminebestNandh!

Besth&N?

•  Op9malhwithpinv=0canbeshownanaly9callytobeh=e=2.72forNopt=ln(H)

•  Withlargerpinvnumericalsolu9ongivesh≈4– ThatiswhytheFO4delayissoimportant!

•  Theminimumis,soabitlargerhdoesonlyincreasedelaymarginallyandsubstanciallysmallerarea


Quickques9on

•  Ifyouweretodesignataperedbufferwheretheloadcapacitanceis15009meslargerthantheinputcapacitance,andyouarenotallowedtoinvertthesignal,howmanyinverterswouldyouchoose?

•  Whatwouldbetheresul9ngnormalizeddelayforthebuffer?


H-treeclockdistribu9on


x3 x3

x2

x1

x2

x2

x2

x3

x3x3 x3x3

x3

x3x3 x3x3

x3 x3 x3 x3

b2 b2

b2 b2

b1

CL

CL

CL

CL

CL

CL

CL

CL

CL CL CL CL

CL CL CL CL

CIN

H-treeclockdistribu9on•  Whatisthe9mingpathelectricaleffort?•  WhatsizestochooseforinvertersintheH-tree?


Criticalpathpropagationdelay

b1 b2

x2

x2

x2

x2

x3

x3

x3

x1

CL

CL

CL

CL

x3

CIN

Shortsummary


0.7 DDpd LDSAT

Vt CI

= t pd = 0.7CLReff

⌧ = 0.7Re↵CG

Thetechnology9meconstant,tau

Theinverterpropaga9ondelay,witheffec9veresistance

Thenormalizeddelay

Normalizedinverterpairdelay Normalizedfanout-of-four(FO4)delay

TaperedbufferwithpathfanoutHandNstages(Disnormalizedpathdelay)

Dmin

= N(pinv

+ hopt

)hopt

=NpH

d = pinv + 1 d = pinv + 4

d ⌘ tpd⌧

Op9malhisaround4

Longsummary•  Definedriseandfalldelaysatthe50%level(VDD/2)andriseandfall9mesbetween

20%and80%levels•  Calculatedpropaga9ondelayinresponsetoasquare-waveinputsignalassuming

MOSFETsbeingsaturatedduringdelay•  Improvedthedelaymodelbyadding40%

–  assumingarampinputsignaland–  assumingequalinputandoutputedgerates

•  Replacedsatura9oncurrentsourcesbyeffec9veresistances•  MadethepMOSFETtwiceaswidetocompensateforlowerholemobility

–  BothMOSFETsnowhavethesameeffec9veresistanceof2kΩ.µm–  However,p-channeldevicenowhastwicetheinputcapacitanceofthen-channelMOSFET

•  Obtainedanelectricaltwo-portmodeloftheinverterfordelaycalcula9ons–  weknowwhatthismodellookslikeseenfromtheinputport,andseenfromtheoutputport

•  CalculatedtheFO4delay,andwefoundtheReffCGproductbeingindependentoftheinvertersize(aslongaswekeepsamera9obetweenWPandWN)

•  Introducedtechnology9meconstant,tau,andnormalizeddelay,d•  Foundbestinvertersizesofataperedinverterbufferforminimumdelay.Fanouth=

4istheop9mum.


lecture 4 the cmos inverter...2018-09-13 lecture 4: cmos inverter dynamics 3 . . . and saturaon...

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