1

Lecture 4: Advanced Pipelines

• Data hazards, control hazards, multi-cycle in-order pipelines

(Appendix A.4-A.10)

2

A 5-Stage Pipeline

3

Conflicts/Problems

• I-cache and D-cache are accessed in the same cycle – it

helps to implement them separately

• Registers are read and written in the same cycle – easy to

deal with if register read/write time equals cycle time/2

(else, use bypassing)

• Branch target changes only at the end of the second stage

-- what do you do in the meantime?

• Data between stages get latched into registers (overhead

that increases latency per instruction)

4

Hazards

• Structural hazards: different instructions in different stages

(or the same stage) conflicting for the same resource

• Data hazards: an instruction cannot continue because it

needs a value that has not yet been generated by an

earlier instruction

• Control hazard: fetch cannot continue because it does

not know the outcome of an earlier branch – special case

of a data hazard – separate category because they are

treated in different ways

5

Structural Hazards

• Example: a unified instruction and data cache

stage 4 (MEM) and stage 1 (IF) can never coincide

• The later instruction and all its successors are delayed

until a cycle is found when the resource is free these

are pipeline bubbles

• Structural hazards are easy to eliminate – increase the

number of resources (for example, implement a separate

instruction and data cache)

6

Data Hazards

SUB R2 R1, R3

Uses R2

Uses R2

Uses R2

Uses R2

7

Bypassing

• Some data hazard stalls can be eliminated: bypassing

8

Example

add R1, R2, R3

lw R4, 8(R1)

9

Example

lw R1, 8(R2)

lw R4, 8(R1)

10

Example

lw R1, 8(R2)

sw R1, 8(R3)

11

Summary

• For the 5-stage pipeline, bypassing can eliminate delays

between the following example pairs of instructions:

add/sub R1, R2, R3

add/sub/lw/sw R4, R1, R5

lw R1, 8(R2)

sw R1, 4(R3)

• The following pairs of instructions will have intermediate

stalls:

lw R1, 8(R2)

add/sub/lw R3, R1, R4 or sw R3, 8(R1)

fmul F1, F2, F3

fadd F5, F1, F4

12

Control Hazards

• Simple techniques to handle control hazard stalls:

for every branch, introduce a stall cycle (note: every

6th instruction is a branch!)

assume the branch is not taken and start fetching the

next instruction – if the branch is taken, need hardware

to cancel the effect of the wrong-path instruction

fetch the next instruction (branch delay slot) and

execute it anyway – if the instruction turns out to be

on the correct path, useful work was done – if the

instruction turns out to be on the wrong path,

hopefully program state is not lost

13

Branch Delay Slots

14

Slowdowns from Stalls

• Perfect pipelining with no hazards an instruction

completes every cycle (total cycles ~ num instructions)

speedup = increase in clock speed = num pipeline stages

• With hazards and stalls, some cycles (= stall time) go by

during which no instruction completes, and then the stalled

instruction completes

• Total cycles = number of instructions + stall cycles

• Slowdown because of stalls = 1/ (1 + stall cycles per instr)

15

Pipelining Limits

A B C

A B C

A B C D E F

A B C D E F

Assume that there is a dependence where the final result of the

first instruction is required before starting the second instruction

Gap between indep instrs: T

Gap between dep instrs: T

Gap between indep instrs:

T/3 + Tovh

Gap between dep instrs:

T + 2Tovh

Gap between indep instrs:

T/6 + Tovh

Gap between dep instrs:

T + 5Tovh

16

Pipeline Implementation

• Signals for the muxes have to be generated – some of this can happen during ID

• Need look-up tables to identify situations that merit bypassing/stalling – the

number of inputs to the muxes goes up

17

Situation Example code Action

No dependence LD R1, 45(R2)

DADD R5, R6, R7

DSUB R8, R6, R7

OR R9, R6, R7

No hazards

Dependence

requiring stall

LD R1, 45(R2)

DADD R5, R1, R7

DSUB R8, R6, R7

OR R9, R6, R7

Detect use of R1 during ID of DADD

and stall

Dependence

overcome by

forwarding

LD R1, 45(R2)

DADD R5, R6, R7

DSUB R8, R1, R7

OR R9, R6, R7

Detect use of R1 during ID of DSUB

and set mux control signal that accepts

result from bypass path

Dependence with

accesses in order

LD R1, 45(R2)

DADD R5, R6, R7

DSUB R8, R6, R7

OR R9, R1, R7

No action required

Detecting Control Signals

18

Multicycle Instructions

Functional unit Latency Initiation interval

Integer ALU 1 1

Data memory 2 1

FP add 4 1

FP multiply 7 1

FP divide 25 25

19

Effects of Multicycle Instructions

• Structural hazards if the unit is not fully pipelined (divider)

• Frequent RAW hazard stalls

• Potentially multiple writes to the register file in a cycle

• WAW hazards because of out-of-order instr completion

• Imprecise exceptions because of o-o-o instr completion

Note: Can also increase the “width” of the processor: handle

multiple instructions at the same time: for example, fetch

two instructions, read registers for both, execute both, etc.

20

Precise Exceptions

• On an exception:

must save PC of instruction where program must resume

all instructions after that PC that might be in the pipeline

must be converted to NOPs (other instructions continue

to execute and may raise exceptions of their own)

temporary program state not in memory (in other words,

registers) has to be stored in memory

potential problems if a later instruction has already

modified memory or registers

• A processor that fulfils all the above conditions is said to

provide precise exceptions (useful for debugging and of

course, correctness)

21

Dealing with these Effects

• Multiple writes to the register file: increase the number of

ports, stall one of the writers during ID, stall one of the

writers during WB (the stall will propagate)

• WAW hazards: detect the hazard during ID and stall the

later instruction

• Imprecise exceptions: buffer the results if they complete

early or save more pipeline state so that you can return to

exactly the same state that you left at

22

ILP

• Instruction-level parallelism: overlap among instructions:

pipelining or multiple instruction execution

• What determines the degree of ILP?

dependences: property of the program

hazards: property of the pipeline

23

Types of Dependences

• Data dependences: an instr produces a result for another

(true dependence, results in RAW hazards in a pipeline)

• Name dependences: two instrs that use the same names

(anti and output dependences, result in WAR and WAW

hazards in a pipeline)

• Control dependences: an instruction’s execution depends

on the result of a branch – re-ordering should preserve

exception behavior and dataflow

24

Title

• Bullet