lecture 4 8-bit+avr+instruction+setlec4
TRANSCRIPT
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Lecture 48-bit AVR Instruction Set
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Status Register (SREG)
SREG: Status Register
C: Carry Flag
Z: Zero Flag
N: Negative Flag V: Twos complement overflow indicator
S: N +V, For signed tests
H: Half Carry Flag
T: Transfer bit used by BLD and BSTinstructions.
I: Global Interrupt Enable/Disable Flag
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Registers and Operands
Rd: Destination (and source) register
Rr: Source Register
R: Result after instruction is executed
K: Constant data K: constant address
b: Bit in Register File or I/O Register (3-bit)
s: Bit in the Status Register (3-bit)
X, Y, Z: Indirect Address Register
(X=R27:R26, Y=R29:R28 and Z=R31:R30)
A: I/O location address
q: Displacement for direct addressing (6-bit)
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The program and Data addressing modes
RISC MC supports powerful and efficient
addressing modes for access to the
Program memory (Flash) and Datamemory (SRAM, Register file, I/O
Memory, and extended I/O Memory).
In the following figures, OP means the
operation code part of the instruction word.
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Register Direct, Single Register Rd
E.g. Inc Rd
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Register Direct, Two Registers Rd and Rr
Operands are contained in register r (Rr) and d(Rd).
The result is stored in register d (Rd).
E.G ADD Rd, Rs
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I/O Direct Addressing
Operand address is contained in 6 bits of the instructionword. N is the destination or source register address.
E.g In Rd, PORTADDRESS ; Out PORTADDRESS,Rs
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Direct Data Addressing
A 16-bit Data Address is contained in the 16 LSBs of atwo-word instruction. Rd/Rr specify the destination orsource register. E.g. LDS Rd, K;K is a 16-bit address.STS K, Rs.
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Data Indirect with Displacement
Operand address is the result of the Y- or Z-register contents
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Data Indirect Addressing
Operand address is the result of the X-, Y- or Z-register.
E.g. LD Rd, X. (X is the Pointer Register)
LD Rd, X+. X is pointer and is incremented after load.
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Data Indirect with Pre-decrement
The X-, Y-, or the Z-register is decremented before theoperation. Operand address is the decrementedcontents of the X-, Y-, or the Z-register.
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Data Indirect with Post-increment
The X-, Y-, or the Z-register is incremented after
the operation. Operand address is the content of
the X-, Y-, or the Z-register prior to incrementing
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Direct Program Addressing, JMP and
CALL
Program execution continues at the
address immediate in the instruction word.
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Indirect Program Addressing, IJMP and
ICALL
Program execution continues at addresscontained by the Z-register (i.e., the PC isloaded with the contents of the Z-register
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Relative Program Addressing, RJMP and
RCALL
Program execution continues at addressPC+k+1. The relative address k is from -2048 to2047.
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ADD Add without Carry
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ADD Add without Carry
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ADD Add without carry
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AND Logical AND
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AND Logical AND
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AND Logical AND
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BREQ Branch if Equal
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BRGE Branch if Greater or Equal
(Signed)
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BRLO Branch if Lower (Unsigned)
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BRNE Branch if not Equal
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CALL Long call to a subroutine
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CBR Clear Bits in Register
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CLR Clear Register
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COM Ones Complement
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CP - Compare
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DEC - Decrement
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IN Load an I/O Location to Register
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INC - Increment
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LD Load Indirect from Data Space to
Register using Index X
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LDI Load Immediate
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LDS(16-bit) Load Direct from Data
Space
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LSL Logical Shift Left
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LSR Logical Shift Right
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MOV Copy Register
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MUL Multiply Unsigned
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NEG Twos Complement
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OR Logical OR
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OUT Store Register to I/O Location
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POP Pop Register from Stack
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PUSH Push Register on Stack
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SBIS Skip if Bit in I/O Register is Set
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SBIC Skip if Bit in I/O Register is
Cleared
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ST Store Indirect from Register to Data
Space using Index X
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STS Store Direct to Data Space
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SWAP Swap Nibbles