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Lecture 3Machine Language

Speaking computer before voice recognition interfaces

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Instructions:

Language of the MachineMore primitive than higher level languages

e.g., no sophisticated control flowVery restrictive

e.g., MIPS Arithmetic Instructions

similar to other architectures developed since the 1980’sused by NEC, Nintendo, Silicon Graphics, Sony

Design goals: maximize performance and minimize cost, reduce design time

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Instruction Execution cycleInstruction

Fetch

Instruction

Decode

Operand

Fetch

Execute

Result

Store

Next

Instruction

Obtain instruction from program storage

Determine required actions and instruction size

Locate and obtain operand data

Compute result value or status

Deposit results in storage for later use

Determine successor instruction

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Key ISA decisions

operationshow many?which ones

operandshow many?locationtypeshow to specify?

instruction formatsizehow many formats?

y = x + b

operation

source operands

destination operand

how does the computer know what0001 0100 1101 1111means?

(add r1, r2, r5)

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In the end, we must have:

Operations

011010010

Sources

1010 01010010100

Destination

000010010

What an architect can change:type of operations: add, branch, find roots of ax2+bx+csources and destinations: memory, registers, I/Othe way we see memory: program and data or separated

To understand these trade-offs, let us makesome designs!

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Crafting an ISA-I

Memory CPU

instructions

Results of computations

a)code the instructions in a simple way, so that decoding them in theCPU takes less hardware;b)code instructions so that they use less memory.

Answer (b) seems to be in the good direction!

Suppose: memory is very slow, 100 X slower than CPU, andalso, REALLY expensive. What would you do:

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Crafting an ISA-II

And what seems more reasonable:a)have few instructions, so that there are not too many options to the

And again, what is more reasonable:

Remember

An architect should ALWAYS have an eye on the availabletechnology!

When silicon memory came, the time difference was reduced, and

Going to memory is easier, but there is still a large difference inspeed;memory is cheaper, can have lots of it!Compiler can not use complex instructions.People are less and less programming using assembly (only timecritical code or bad management)

Crafting an ISA-III

how those decisions were made in the designof the MIPS instruction set.MIPS, like SPARC, PowerPC, and Alpha AXP, isa RISC (Reduced Instruction Set Computer)ISA.

fixed instruction lengthfew instruction formatsload/store architecture

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Crafting an ISA-IV

RISC architectures worked because they enabledpipelining. They continue to thrive because theyenable parallelism (more on this in this course!).Changes on technology that allowed RISCs:

memory speed and costcompiler technology increase

New changes to come:many transistors more (increase cache, branchprediction, floating point, etc);low power applications: back to complex coding?extensive use of dynamic RAM: IRAM chips?reconfigurable devices?Java machines?

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Crafting an ISA-V

More on technology dependencies and design decisions during thecourse.

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How Many Operands?

Most instructions have three operands(e.g., z = x + y).

Well-known ISAs specify 0-3 (explicit) operands perinstruction.Operands can be specified implicitly or explicity.

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How Many Operands? (basic ISA classes)

Accumulator:1 address add A acc acc + mem[A]

Stack:0 address add tos tos + next

General Purpose Register:2 address add A B A A + B (addressing might be

more complex)3 address add A B C A B + C

Load/Store:3 address add Ra Rb Rc Ra Rb + Rc

load Ra Rb Ra mem[Rb]store Ra Rb mem[Rb] Ra

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Comparing the Number of Instructions

Code sequence for C = A + B for four classes of instruction sets:

Stack Accumulator Register Register

(register-memory) (load-store)

Push A Load A Load R1,A

Push B Add B Load R2,B

Add Store C

ADD C, A, B

Add R3,R1,R2

Pop C Store C,R3

Watch! For a sequence of operations, who is favored?Try: a*b+c*d*g+h; again with only 2 registers

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Instruction Length

Variable:

Fixed:

Hybrid:

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Instruction Length

Variable-length instructions (Intel 80x86, VAX) require multi-stepfetch and decode, but allow for a much more flexible and compactinstruction set.Fixed-length instructions allow easy fetch and decode, and simplifypipelining and parallelism (believe me by now; see for yourself in thelab!).

All MIPS instructions are 32 bits long.this decision impacts every other ISA decision we make because it

makes instruction bits scarce.

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Instruction Formats: the role of each bit

Having many different instruction formats...complicates decodinguses instruction bits (to specify the format)

VAX 11 instruction format

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MIPS Instruction Formats

the opcode tells the machine which formatso add r1, r2, r3 has

opcode=0, rs=2, rt=3, rd=1, sa=0, funct=32, 000000 00010 00011 00001 00000 100000

OP

OP

OP

rs rt rd sa funct

rs rt immediate

target

6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

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Accessing the Operands

operands are generally in one of two places:registers (32 int, 32 fp)memory (232 locations)

registers areeasy to specifyclose to the processor (fast access)

the idea that we want to access registers whenever possible led toload-store architectures.

normal arithmetic instructions only access registersonly access memory with explicit loads and stores

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Load-store architectures

can do:add r1=r2+r3

andload r3, M(address)

forces heavy dependence onregisters, which is exactly what

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A historical note

Once upon a time, a big companyinvented a new microprocessor. Ithad NO registers at all, alloperations were memory mapped.Since memory was slow, themicroprocessor never sold verymuch, because the overall systemperformance was low.Although heads rolled, someengineers claimed that thememory would become faster,and a whole set of problemsneeded too many memoryreferences.

The company used the samedesign strategy, applied toproblems that required too manymemory accesses and designed aprocessor tuned to a specific field:Digital Signal Processing. Theymade a fortune!

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MIPS arithmetic

All instructions have 3 operandsOperand order is fixed (destination first)

Example:

C code: A = B + C

MIPS code: add $s0, $s1, $s2

(associated with variables by compiler;)

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MIPS arithmetic

Design Principle: simplicity favors regularity. Why?Of course this complicates some things...

C code: A = B + C + D;E = F - A;

MIPS code: add $t0, $s1, $s2add $s0, $t0, $s3sub $s4, $s5, $s0

Operands must be registers, only 32 registers providedDesign Principle: smaller is faster. Why?

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Registers vs. Memory

Processor I/O

Control

Datapath

Memory

Input

Output

Arithmetic instructions operands must be registers,

Compiler associates variables with registersWhat about programs with lots of variables

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So, how do we get the operands?

- Register direct R3- Immediate (literal) #25- Direct (absolute) M[10000]

- Register indirect M[R3]- Base+Displacement M[R3 + 10000]

if register is the program counter, this is PC-relative- Base+IndexM[R3 + R4]- Scaled Index M[R3 + R4*d + 10000]- Autoincrement M[R3++]- Autodecrement M[R3 - -]

- Memory Indirect M[ M[R3] ]

Addressing modes!

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register direct

add $1, $2, $3

immediate

add $1, $2, #35

base + displacementlw $1, disp($2)

MIPS addressing modes

OP rs rt rd sa funct

OP rs rt immediate

rt

rs

immediate

register indirect disp = 0

absolute (rs) = 0

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Is this sufficient?

Measurements on the VAX show that theseaddressing modes (immediate, direct, registerindirect, and base+displacement) represent 88% ofall addressing mode usage.Similar measurements show that 16 bits is enoughfor the immediate 75 to 80% of the time;and that 16 bits is enough of a displacement 99% ofthe time.

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Memory Organization

Viewed as a large, single-dimension array, with an address.A memory address is an index into the array"Byte addressing" means that the index points to a byte of memory.

0

1

2

3

4

5

6

...

8 bits of data

8 bits of data

8 bits of data

8 bits of data

8 bits of data

8 bits of data

8 bits of data

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Memory Organization

For MIPS, a word is 32 bits or 4 bytes.

232 bytes with byte addresses from 0 to 232-1230 words with byte addresses 0, 4, 8, ... 232-4Words are aligned

i.e., what are the least 2 significant bits of a word address?

0

4

8

12

...

32 bits of data

32 bits of data

32 bits of data

32 bits of data

Registers hold 32 bits of data

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What have we got so far for the MIPS ISA:

Fixed 32-bit instructions3 instruction formats3-operand, load-store architecture32 general purpose registers (R0=0), all 32-bits wide(word)register, immediate, and base+displacementaddressing modes

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Instructions

Load and store instructionsExample (A=array 100 words, base address is in $s3):

C code: A[12] = h + A[8];

MIPS code: lw $t0, 32($s3)add $t0, $s2, $t0sw $t0, 48($s3)

Store word has destination lastRemember arithmetic operands are registers, not memory!

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More lw and sw

G = h + A[I]A has 100 elements;base=$s3G=$s1h=$s2I=$s4

add $t1, $s4, $s4 # temp reg $t1 = 2*Iadd $t1, $t1, $s4 # temp reg $t1 = 2*I# multiply y 4 because of byte addressingadd $t1, $t1, $s3 # $t1 = address of A[I] (4*i+$s3)lw $t0, 0($t1) # $t0=A[I]add $s1, $s2, $t0

Notice:offset + base addressing is good for structures:one register points to the base, the offset canselect the desired element.

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Exercise:

G[j]= h + A[I];G and A have 100 positions; use $t0-9 as scratch registers; baseaddress of G is in $s3, of A in $s4.

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Remember:

MIPS

Instruction Meaning

add $s1, $s2, $s3 $s1 = $s2 + $s3sub $s1, $s2, $s3