lecture #23 - state reduction and flip-flop input...
TRANSCRIPT
ECE 331 – Digital System Design
State Reductionand
Derivation Flip-Flop Input Equations
(Lecture #23)
The slides included herein were taken from the materials accompanying
Fundamentals of Logic Design, 6th Edition, by Roth and Kinney,
and were used with permission from Cengage Learning.
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Sequential Circuit Design1. Understand specifications
2. Draw state graph (to describe state machine behavior)
3. Construct state table (from state graph)
4. Perform state reduction (if necessary)
5. Assign a binary value to each state (state assignment)
6. Create state transition table
7. Select type of Flip-Flop to use
8. Derive Flip-Flop input equations and FSM output equation(s)
9. Draw circuit diagram
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State Reduction
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Equivalent States
● Two states, p and q, of a sequential logic circuit, are equivalent iff for every input X,
– the outputs are equal
– the next states are equivalent.
● λ(p, X) = λ(q, X)
– Specifies the output given the present state and the input
● δ(p, X) == δ(q, X)
– Specifies the next state given the present state and the input
● Note: the next states do not need to be equal, just equivalent.
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Determination of Equivalent States
a ≡ b iff
d ≡ f and c ≡ h
a ≡ d iff
a ≡ d and c ≡ e
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Example: Design a sequence detector.
FSM Design: Mealy
serial bit stream (input)
output (serial bit stream)
The circuit (again) is of the form:
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Example: Sequence Detector (Mealy)
The sequential circuit has one input (X) and one output (Z).
It examines groups of four consecutive inputs and produces
an output Z = 1 if the input sequence 0101 or 1001 occurs.
The circuit resets after every four inputs.
A typical input and output sequence is:
X = 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0
Z = 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0
(time: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15)
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Example: Sequence Detector (Mealy)
State Table
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Example: Sequence Detector (Mealy)
Eliminating Redundant States
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Example: Sequence Detector
Since states H and I
have the same next
states and the same
outputs, there is no way
of telling states H and I
apart.
We can replace I with H.
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Example: Sequence Detector (Mealy)
Reduced State Table
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Example: Sequence Detector
Reduced State Graph
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State Reduction using an Implication Chart
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State Reduction using an I.C.
1.Construct an Implication Chart which contains a square for each pair of states (i, j).
2.Compare each pair of rows in the State Table.
– If outputs for states i and j are different, put an X in the corresponding square of the I.C.
– If outputs for states i and j are the same, indicate the implied pairs in the corresponding square of the I.C.
– If outputs and next states for states i and j are the same, put a check in the corresponding square of the I.C.
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State Reduction using an I.C.
3.If square i-j contains the implied pair m-n, and square m-n contains an X, then i<>j, and an X must be placed in the corresponding square of the I.C.
4.If X's were added in step 3, repeat step 3 until no more X's are added.
5.For each square i-j, which does not contain an X, i==j.
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Example: State Reduction using an I.C.
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Example: State Reduction using an I.C.
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Example: State Reduction using an I.C.
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Example: State Reduction using an I.C.
After first pass.
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Example: State Reduction using an I.C.
After second pass.
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Example: State Reduction using an I.C.
d = = ae = = c
d and e are removed from the State Table
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Future site of another example.
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Derivation of Flip-Flop Input Equations
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Derivation of FF Input Equations
1. Assign a binary value to each state in the reduced state table (state assignment).
2. Construct the state transition table.
Include in the state transition table, columns for the Flip-Flop inputs.
3. Construct the K-maps for the Flip-Flop inputs.
4. Derive the minimized FF input equations.
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Derivation of FF Input Equations
Example #1:
Derive the Flip-Flop input equations for the following sequential logic circuit.
Assume that D Flip-Flops are used in the design.
Excitation Equation: D = Q+
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Example #1: FF Input Equations
State Table
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Example #1: FF Input Equations
1. Assign a binary value to each state.2. Construct the state transition table.
A+B+C+ DADBDC Z
ABC X = 0 X = 1 X = 0 X = 1 X = 0 X = 1
000
001
010
011
100
101
110
111
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Example #1: FF Input Equations
3. Construct K-maps for Flip-Flop inputs.4. Derive the minimized FF input equation.
DA = DB =
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Example #1: FF Input Equations
DC =
3. Construct K-maps for Flip-Flop inputs.4. Derive the minimized FF input equation.
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Derivation of FF Input Equations
Example #2:
Derive the Flip-Flop input equations for the following sequential logic circuit.
Assume that JK Flip-Flops are used in the design.
Excitation Table:
Q Q+ J K
0 0 0 x
0 1 1 x
1 0 x 1
1 1 x 0
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Example #2: FF Input Equations
State Table
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Example #2: FF Input Equations
1. Assign a binary value to each state.2. Construct the state transition table.
A+B+C+ JAKA JBKB JCKC
ABC X = 0 X = 1 X = 0 X = 1 X = 0 X = 1 X = 0 X = 1
000
001
010
011
100
101
110
111
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Example #2: FF Input Equations
3. Construct K-maps for Flip-Flop inputs.4. Derive the minimized FF input equation.
JA = KA =
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Example #2: FF Input Equations
3. Construct K-maps for Flip-Flop inputs.4. Derive the minimized FF input equation.
JB = KB =
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Example #2: FF Input Equations
3. Construct K-maps for Flip-Flop inputs.4. Derive the minimized FF input equation.
JC = KC =
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Derivation of FF Input Equations
Example #3:
Derive the Flip-Flop input equations for the following sequential logic circuit.
Assume that SR Flip-Flops are used in the design.
Excitation Table:
Q Q+ S R
0 0 0 x
0 1 1 0
1 0 0 1
1 1 x 0
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Example #3: FF Input Equations
State Table
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Example #3: FF Input Equations
1. Assign a binary value to each state.2. Construct the state transition table.
A+B+ SARA SBSB
AB X=00 X=01 X=11 X=10 X=00 X=01 X=11 X=10 X=00 X=01 X=11 X=10
00
01
11
10
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Example #3: FF Input Equations
3. Construct K-maps for Flip-Flop inputs.4. Derive the minimized FF input equation.
SA = RA =
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Example #3: FF Input Equations
3. Construct K-maps for Flip-Flop inputs.4. Derive the minimized FF input equation.
SB = RB =
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Questions?