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Field Effect Transistors EE 21 – Fundamentals of Electronics

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EE

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Field Effect Transistor (FET)

• Voltage-Controlled Device

• Two types: N-channel and P-channel

• The output current is dependent on the applied voltage.

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JFET Schematic Symbols

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Field Effect Transistor (FET)

• Unipolar Device, unlike the BJT… (why is it called unipolar?)

• Another question: why is it called “field-effect” transistor?

• Have very high input impedance (1-100MΩ), but have considerably less gains compared to BJTs.

• Also referred to as Junction Field Effect Transistor (JFET)

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JFET Construction

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JFET Operation: The water analogy Electron flow : Water

flow

(From source to drain)

Gate control: similar to applied potential

Source and drain : opposite ends of the channel

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JFET Operation, Case 1: VGS = 0, VDS = some (+) value… • Application of potential

draws e- towards drain, causing a drain current.

• e- flow is limited by the “resistance” of n-channel b/w drain and source (represented by the depletion region thickness).

• Question: Why isn’t the d.r. thickness constant??

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Varying Resistances and IG = 0

• Assuming uniform resistance for N-channel, voltage divisions occur along the channel

• The PN junctions are all reverse biased, but by different voltage levels.

• NOTE: IG = 0 in JFETs. (WHY??)

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Pinch-off condition

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A few more things about IDSS

• IDSS is the maximum drain current possible for a JFET

• It is defined at VGS = 0 and VDS > |VP|

• The value of IDSS is usually specified in datasheets.

• This value is constant even if VGS is applied, though it will not be reached if VGS is present…

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Case 2: Applied VGS < 0

• When applying VGS, it is always < 0 for N-channel JFET!

• VGS is applied to establish D.Rs at a lower level of VDS.

• This is similar to how a BJT’s IB can vary the levels of VCE & IC.

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For increasing (-) VGS values…

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Ohmic Region

• The region to the left of the pinch-off locus is known as the ohmic region or the voltage-controlled resistance region.

• ro is the resistance at VGS = 0, rd is the resistance at a voltage level VGS.

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Summary of Operation

1. Maximum Drain Current = IDSS, occurs at VGS = 0 and VDS ≥ |VP|.

2. Maximum possible

ID is reduced by application of VGS voltage, and ID = 0 for |VGS| > |VP| (VGS is more negative than VP).

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Summary of Operation

3. For |VP| ≥ |VGS| ≥ 0 V, 0 mA ≤ ID ≤ IDSS.

Meaning, for varying levels of VGS, the drain current varies accordingly.

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Note that we used N-Channel JFETs in this discussion. For P-channel JFETs, the biasing polarities , current directions, and thresholds will just be reversed!

Summary of Operation

• Recall that for a BJT, IC = βIB; i.e. IC = f(IB)

• In the same manner, a JFET’s ID and VGS are related as defined by

SHOCKLEY’S EQUATION:

• This will help us construct the input characteristics of the JFET under bias.

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Shockley Curve

• The curve of the input characteristics as defined by the Shockley’s equation.

• For decent approximation, four points are chosen for the graphical solution.

1. VGS = 0 ID = IDSS

2. VGS = VP ID = 0

3. VGS = ½ VP ID = ¼ IDSS

4. VGS = 0.3VP ID = IDSS/2

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Example: Shockley Curve

• Sketch the transfer curve for an N-channel JFET defined by IDSS = 12mA and Vp = -6 Volts by using the graphical (four-point) method.

• Sketch the transfer curve for a P-channel JFET with IDSS = 4 mA and Vp = 3 V.

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