lecture 2 - university of california, berkeleyee290d/fa13/lecturenotes/lecture2.pdf · lecture 2...
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Lecture 2• Short-Channel MOSFET Electrostatics
– MOSFET Performance Metrics– Short-Channel Effects
Reading: - Taur & Ning, “Fundamentals of Modern VLSI Devices,”
Cambridge Univ. Press, 1998.- multiple research articles (reference list at the end of this lecture)
Courtesy of V. Moroz (Synopsys)
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Simple MOSFET Performance MetricsOutput CharacteristicsTransfer Characteristics
0.0 0.2 0.4 0.6 0.8 1.0 1.20.0
0.2
0.4
0.6
0.8
1.0
1.2VGS : 0V - 1V, 0.1V step
Dra
in C
urre
nt I D
S (m
A/u
m)
VDS (V)0.0 0.2 0.4 0.6 0.8 1.0 1.2
10-9
10-8
10-7
10-6
10-5
10-4
10-3
VGS (V)
Dra
in C
urre
nt I D
S (A
/um
)
0.0
0.4
0.8
1.2
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Review of Long Channel MOSFET• Threshold Voltage (VTH)
• Sub-threshold Swing (SS)
incr
easi
ng E
n(E) exp (-E/kT)
SourceDrain
Body
Gate
Drain
CoxCdep Source
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Short Channel Effect (SCE)
Long Channel:
S D
DS
Short Channel:
• The smaller Lg is, the greater percentage of depletion charge balanced by the S/D PN junctions
• 1st Order Analysis
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Quantitative Derivation of SCE:Yau’s Model
• Depletion charge (Qdep) reduction:
• Threshold Voltage Lowering:
• Yau’s model’s assumptions: Uses geometry relations instead of solving
Poisson’s equation Assumes channel potential is linear along lateral
(i.e. channel) direction9/9/2013 Nuo Xu EE 290D, Fall 2013 5
L.-D. Yau, SSE (1974)
Drain Induced Barrier Lowering (DIBL)- Qualitative
6
In short-Lg MOSFET:• x- and y- components of the electric field are coupled Drain bias will affect the barrier at source/channel More band bending at given gate bias VT decreases
C. Hu, Modern Semiconductor Devices for Integrated Circuits, Figure 7-5
Long Channel
Short Channel
y
x
9/9/2013 Nuo Xu EE 290D, Fall 2013
Derivation for DIBL- A Quasi-2D Model
7
Steps:1. Develop Poisson’s equation in the channel region, including x- and y-components.
2. Solve as a function of position (y)
3. Calculate the peak of , which corresponds to VTH.
9/9/2013 Nuo Xu EE 290D, Fall 2013
Scale Length – A Simplified Knob1. Tells how closely a MOSFET approaches a “short-channel”
device.
2. Provides the guideline to scale a MOSFET while maintaining its electrostatic integrity.
e.g. for Planar Technology:
Bulk Ultra-Thin-Body Double-Gated FinFET
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VTH vs. Lg Plots: SCE + DIBL
Lg
∆|VTH|
Long channel
SCE limited
DIBL limited
Increasing Vds
9/9/2013 9Nuo Xu EE 290D, Fall 2013
State-of-the-Art MOSFET’sVTH vs. Lg Plots
Intel’s 32nm Bulk Samsung’s 20nm Bulk
P. Packan, IEDM (2009) H.-J. Cho, IEDM (2011)
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Sub-threshold Swing Degradation
11
• A 2-D Capacitor Network Model
DrainSource
Gate
• Impact of Lg Scaling on SS
(after Prof. M. Lundstrom)
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IOFF vs. ION Plots
ION
logIOFFBaseline
High Gm
ION
logIOFFBaseline
Low SS
ION
logIOFFBaseline
Combined
• Generated by “shifting” a device’s VTH under a fixed VDD• To benchmark the effectiveness of technology advancement.
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Gate Induced Drain Leakage (GIDL)
13
Id vs. Vgs CharacteristicsIllustration and Band Profiles
T.-Y. Chan, IEDM (1987)
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Intel’s 32nm Bulk CMOSIOFF vs. ION Plots
PMOS
45nm
32nm
NMOS
45nm
32nm
P. Packan, IEDM (2009)9/9/2013 14Nuo Xu EE 290D, Fall 2013
IBM’s 20nm Bulk CMOSIOFF vs. ION Plots
NMOS PMOS
H. Shang, VLSI-T (2012)
28nm
20nm
28nm
20nm
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GIDL-Limited IOFF vs. ION Plots
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100 200 300 400 500 600 700
10-12
10-11
10-10
10-9
10-8
10-7
10-6
10-5
10-4
I off (
A/u
m)
Ion (uA/um)
Leff=172nm Leff=92nm Leff=62nm Leff=52nm
Vdd=1.2V
GIDL-limited
FWD Vb
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Narrow Width Effects
• Narrow Width Effect is caused by LOCOS process.• Reverse Narrow Width Effect is caused by STI process.• Introduce problems as transistor systematic variations.
17
Reverse Narrow Width EffectNarrow Width Effect- A “Quasi-planar” MOSFET !
9/9/2013 Nuo Xu EE 290D, Fall 2013
State-of-the-Art MOSFET’sNarrow Width Effects
Samsung’s 20nm CMOS
H.-J. Cho, IEDM (2011)
IBM’s 20nm CMOS
H. Shang, VLSI-T (2012)
• Thanks to advanced isolation techniques, narrow width effects are no longer problematic.
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Summary
19199/9/2013 Nuo Xu EE 290D, Fall 2013
Id vs. Vg Id vs. Vd Vg vs. Lg IOFF vs. ION
SCEDIBLSS DegradationPunchthroughGIDLNarrow WidthEffects
• How bad a planar bulk MOSFET is, regarding electrostatics?
References
20
Short Channel Effects1. (SCE) L.-D. Yau, “A Simple Theory to Predict the Threshold Voltage of Short-Channel IGFET’s,” Solid State Electronics, Vol.17, pp. 1059-1063, 1974.2. (Scale Length) R.-H. Yan, A. Ourmazd, K.F. Lee, “Scaling the Si MOSFET: from Bulk to SOI to Bulk,” IEEE Transactions on Electron Devices, Vol. 39, Issue 7, pp. 1704-1710, 1992.3. (2D Capacitor) M. Lundstrom, “2D MOS Electrostatics,” NanoHub Online Resources at http://nanohub.org/resources/15617/download/nanoHUB-U-Lundstrom-L2.5.pdf, 2012.4. (GIDL) T.-Y. Chan, J. Chen, P. K. Ko, C. Hu, “The Impact of Gate-Induced Drain Leakage Current on MOSFET Scaling,” IEEE International Electron Devices Meeting Technical Digest, pp. 87-90, 1987.
Industry Bulk CMOS Platforms5. (Intel 32nm HP) P. Packan, S. Akbar, M. Armstrong, D. Bergstrom, M. Brazier et al., “High Performance 32nm Logic Technology Featuring 2nd Generation High-k + Metal Gate Transistors,” IEEE International Electron Devices Meeting Technical Digest, pp. 659-662, 2009.6. (Samsung 20nm) H.-J. Cho, K.-I. Seo, W.C. Jeong, Y.-H. Kim, Y. D. Lim et al., “Bulk Planar 20nm High-K/Metal Gate CMOS Technology Platform for Low Power and High Performance Applications,” IEEE International Electron Devices Meeting Technical Digest, pp. 350-353, 2011.7. (IBM 20nm) H. Shang, S. Jain, E. Josse, E. Alptekin, M. H. Nam et al., “High Performance Bulk Planar 20nm CMOS Technology for Low Power Mobile Applications,” Symposium on VLSI Technology Digest, pp. 129-130, 2012.
9/9/2013 Nuo Xu EE 290D, Fall 2013