lecture 2 - forwardmy.fit.edu/~earles/ece4311/ch2-1_lpcvd.pdf · silicon nitride applications: for...
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2.1 CVD of polysilicon anddielectric thin films
Lecture 2
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2B1242 SPRING 2006
Mikael Östling KTH
Basic definitionsReactor designsPolysiliconSilicon oxideSilicon nitrideModeling
Basic definitionsReactor designsPolysiliconSilicon oxideSilicon nitrideModeling
Polysilicon and deposited oxides in a conventional NMOSFET:
(Fig. 9.1 Sze)
CVD of polysilicon and dielectric thin films
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2B1242 SPRING 2006
Mikael Östling KTH
Chemical vapor deposition (CVD)
Thermal CVD typically between 400-900°C : Low-pressure CVD (LPCVD): 0.1- 1 torrAtmospheric-pressure CVD (APCVD)
Lower temperature budget by:Plasma-enhanced CVD (PECVD)Photon-induced CVD: Photon generation by UV or laser.
Present CVD trends:Rapid Thermal CVD (RTCVD) > 10 torrHigh-density PECVD (HDPCVD)
CVD parameters important for film properties:Reactor designTemperaturePressure
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2B1242 SPRING 2006
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Increased Increasedsupersaturation temp.
Fundamental CVD aspects
Thermodynamics and kineticsTransport phenomenaNucleation and thin film growth
Effect of supersaturation and temperature on thin film structure:
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2B1242 SPRING 2006
Mikael Östling KTH
CVD basic reactor design
Hot wall
Cold wall
Trend is from hot-wall batch reactors to cold-wall single-wafer tools
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2B1242 SPRING 2006
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Thermal CVDLPCVD hot-wall. Most common in production. Both horizontal and vertical
deisgn.APCVD. Not very common today.
(Fig. 6.1 VLSI Techn. p. 236)
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2B1242 SPRING 2006
Mikael Östling KTH
PECVD
Parallel-plate: Common in productionHot-wall: Not very common today
(Fig. 6.2 VLSI Techn. p. 237)
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2B1242 SPRING 2006
Mikael Östling KTH
Characteristics of various CVD processes
(Table 1. ULSI Technology p. 211)
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2B1242 SPRING 2006
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The LPCVD workhorse system for Si3N4, silicon oxide and polysilicon
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Centura poly process (Applied Materials)
Modern RTCVD process
Deposition module in cluster tool
Similar to LT epi process:
Single-wafer system > 10 torrHydrogen as carrier gas In situ dopingIn situ cleaning (HCl or NF3)
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Polysilicon
Used in VLSI for:n+ or p+ gate electrode material in CMOS (see below)n+ emitter contact in BIP (see below), so-called polysilicon emitter technologyDiffusion source (double-poly bipolar process for formation of E and B) (see below)Local interconnectsDeep-trench filling (see below)Resistances
Also poly-SiGe of interest as common p+-gate electrode in CMOS(so-called mid bandgap material)
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p- substrate
pp+
n
n+ epi
p+
n+
LOCOS
E B C
n+ polyn+ poly
p+ poly Oxide
Poly-Si filled trench
n+
p+
n- epi n- epi (SIC)
Double-poly bipolar structure:
Also many other applications of polysilicon: Solar cells, TFTs etc
CMOS structure with poly gate electrode:
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2B1242 SPRING 2006
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Conventional LPCVD process
Polysilicon deposition using silane at 600-650°C
SiH4 ⇔ SiH2 + H2SiH2 ⇔ Si + H2
Alternative: Si2H6 (disilane). Permits lower deposition temperatures.
(VLSI Tech. Fig. 5 p. 243)
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Arrhenius plot of SiH4 deposition at different partial pressures of SiH4
Activation energy of 1.7 eV
(VLSI Tech. Fig. 5 p. 240)
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2B1242 SPRING 2006
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Exact microstructure depends on a number of factors:Pressure, dopants, temperature, thickness, recrystallization etc
Grain growth important for final electrical properties
(Plummer Fig 9-32 p. 560)
Microstructure of polysilicon
T > 625°C Columnar growth.Preferential (110) orient.
T < 575°C Amorphous
T ~ 600°C Microcrystallinepolysilicon
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2B1242 SPRING 2006
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Doping by diffusion, ion implant or in situ during CVD deposition resistivity < 1 mWcm after annealing
Ion implantation most common today
(VLSI Techn, Fig. 8 p. 245)
Dopant diffusion is typically around 1000x faster in grain boundaries than inside the grains
Doping of polysilicon
Complex behavior of dopants in polysilicon during subsequent procesing: Segregation of Ph and As (but not B) to the grain boundaries
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2B1242 SPRING 2006
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In situ doping of polysilicon
Difficult process in batch furnace, in particular during n-type doping.Non-uniformities and very low deposition ratesRequires quartz cage for wafers in LPCVD tubePreferably deposited in amorphous phase and subsequently crystallized
(VLSI Techn, Fig. 6 p. 243)
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2B1242 SPRING 2006
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Epitaxial re-alignment of deposited poly
Polysilicon on monosilicon can be re-alignedDemonstrated for suppressing 1/f noise in polyemitters of HF BIP transistors (STM)
Example: KTH double-poly bipolar process (BIP#2) exhibiting re-grown base-poly
Fluorine from ex-base BF2 implant acts to break up thin SiO2 interface between poly-mono
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2B1242 SPRING 2006
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Silicon dioxideImportant for isolation in active devices as well as between metal layersEssential reactions for SiO2 depositions:
LPCVD:Tetraethylorthosilicate (TEOS): (liquid source!)Si(OC2H5)4 650-750°C
Low-temperature oxide (LTO):SiH4 + O2 400-450°C
Note: Dichlorosilane (DCS): SiCl2H2 + N2O uncommon today
PECVD:SiH4 + 2N2O 200 - 350°CPlasma TEOS 300 - 360°C
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2B1242 SPRING 2006
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Sub-atmospheric CVD (SACVD):TEOS + O3 300-550°C
Typically TEOS results in porous films which may need densification. Also C in films!
PECVD films generally contains a lot of H or N
(VLSI Techn. p. 259)
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Comparison of TEOS and LTO: Arrhenius plots
(VLSI Techn. p.252)
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2B1242 SPRING 2006
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Comparison of TEOS and LTO: Step coverage
(a) typical for TEOS(c) typical for LTO
Difference rather due to different sticking than surface transport (sticking of TEOS lower than for LTO)
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2B1242 SPRING 2006
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P-glass flowSo-called phosphosilicate glass (PSG)
Phosphorous introduced in SiO2 for gettering of impurities in intermetallicdielectric and for permitting glass flow at high temperature around 1000-1100°C
Glass flow improves poor step coverage of LTO:
By adding B B-PSG = BPSG
B will help to reduce softening point to 800°C
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2B1242 SPRING 2006
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Silicon nitrideApplications:
For mask in LOCOS process (barrier against oxygen diffusion)Passivation layer: (barrier against H2O, sodium)
LPCVD3SiH2Cl2 + 4NH3 Si3N4 + 6 HCl + 6H2 650-800°C (most common)
3SiH4 + 4NH3 Si3N4 + 12H2 700-900°C
Excess of NH3 used in reaction!
PECVDSi3N4 used for passivation using silane and NH3 at 200-400°CContains much H! Usually non-stoichiometric!Stress can be tuned by plasma parametersNew trend: High-density plasma systems
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Properties of silicon nitride
Large tensile stress.
Typically max 2000 Å Si3N4 can bedeposited on Si
(VLSI Techn. p. 263)
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Refractive index andstoichiometry of silicon nitride tuned by PECVD process
Results in “low-stress” silicon nitride (Si-rich). Important for many MEMS processes
Dual frequency tuning of plasma another solution for controlling film properties
(ULSI technology p245)
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Simulations: Topography modeling in PVD and CVD. Def. step coverageTopography modeling of LPCVD depositionsDefine aspect ratio = height/width = h/w of a feature Highly desirable with so-called conformal step coverage
(Plummer p 510)
Physically-based models for simulation of depositions in topographical structures
Models based on sum of fluxes arriving or leaving the surface for each point, see discussion paragraph 9.5.1.1. Plummer
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Modeling for direct and indirect atom fluxes reaching the surface at point i:
Fnet = Fdirect(neutrals) + Fredep + Femitted
(Plummer p 582)
Important modeling parameters:Sticking coefficient SC defined as Freacted/FincidentExponent n in cosnq which describes the distribution of arriving fluxes impinging on a surface.
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2B1242 SPRING 2006
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Influence of modeling parameters of various processes
(Pliummer p 588)
n=1 in LPCVD (isotropic flux)
Sc the important factor in LPCVD.Low Sc desirable, see simulation example:
(Plummer p 593)
Explains why TEOS has much better step coverage than LTO.