Lecture 14

Flip-FlopsSection 5.5-5.6

Schedule3/24 Monday Analysis of clocked sequential circuit

(1), 5.5

3/26 Wednesday Analysis of clocked sequential circuit (2)

5.5

3/27 Thursday Clocked sequential circuit  3/31 Monday Shift register (1) 6.1-6.24/2 Wednesday Shift register (2) 6.1-6.24/3 Thursday Universal shift register  4/7 Monday Counters (1) 6.34/9 Wednesday Counter (2) 6.34/10 Thursday Counter  4/14 Monday Review  

Please bring a functional random number generator to class on Thursday(3/27).

Outline

• Review of Flip-flops– D flip-flops– JK flip-flops– T flip-flop

• Analysis of a simple sequential circuit

Symbol of D Flip-Flops

reset and preset

• When power is first turned on, the state of the flip-flops is unknown.– Reset is used to initialize the output to a

0.– Preset is used to initialize the output to

a 1.

D Flip-flop with reset

Typo in the book. Should be 1 instead.

JK Flip-FlopsD=JQ’+K’Q

The next value of D is determined by JQ’+K’Q.At the rising edge of D Flip-flop, Q is updated with the value of D.

Positive edge D flip-flop

D=JQ’+K’Q

• J=1,K=1→D=Q’• J=0, K=0 →D=Q• J=0, K=1 →D=0• J=1, K=0 →D=Q’+Q=1

Verilog Implementation

T Flip-Flop

T Flip-Flop from a D Flip-Flop

DT=TQ’+T’Q

If T=1, D=Q’If T=0, D=Q.

Q is updated with D at the next rising edge.

𝑄DT

rst

Verilog Implementation of a T-FF

𝑄DT

rst

Example of a Sequential Circuit

D flip-flops

Example of a Sequential Circuit

D flip-flops

Construction of a State Table

Example: Start with A=0, B=0, x=0.A(next)=0B(next)=0Y(next)=0

Construction of a State Table

Example: Start with A=0, B=0, x=0.A(next)=0B(next)=0Y(next)=0

What are A(next), B(next) and y(next) given that A=1, B=1 and X=1?

D flip-flops

Alternate State Table

Alternate State Table

State Diagram

Each circle is a state

When x=1, y=0.

State Diagram

Each circle is a state

When x=0, y=1.

Detects 0 in the bit stream of data

Output is a 0 as long as input is a 1. The first 0 after a string of 1s transfers the circuit back to 00.

Detects 0 in the bit stream of data

Output is a 0 as long as input is a 1. The first 0 after a string of 1s transfers the circuit back to 00.

Detects 0 in the bit stream of data

Output is a 0 as long as input is a 1. The first 0 after a string of 1s transfers the circuit back to 00.

Summary

Model a Clocked Sequential Circuit with Verilog

1. Use parameter to represent each state2. Form the next state from x (the input)and the current state3. Form the output4. fork.....join construction

S0

S1

S2

S3

Parameter

S0

S1

S2

S3Define states with parameter

Update States

S0

S1

S2

S3

If reset is 0, set state to S0.

If reset is 1, update state with next_state.

Syntax for always

Implement the States Using State Diagram

S0

S1

S2

S3

The always statement will be initiatedif there is a change in state or x_in

fork....join

Statements within fork….join block executein parallel, so the time delays are relative to t=0.

Valid Mealy Output

S0

S1

S2

S3

Mealy Glitches

S0

S1

S2

S3

Glitiches occur because x changes before the next rising clock edge

Synthesizable Verilog

• http://www.youtube.com/watch?v=YTId6cpTEFM