lecture 13 flip-flops section 5.4. schedule 3/10mondaylatches (1)5.1-5.3 3/12wednesdayflip-flops5.4...
TRANSCRIPT
Lecture 13
Flip-FlopsSection 5.4
Schedule3/10
Monday Latches (1) 5.1-5.3
3/12
Wednesday Flip-flops 5.4
3/13
Thursday Flip-flops, D-latch
3/17
Monday Spring break
3/19
Wednesday Spring break
3/20
Thursday Spring break
3/24
Monday Analysis of clocked sequential circuit (1) 5.5
3/26
Wednesday Analysis of clocked sequential circuit (2) 5.5
3/27
Thursday Clocked sequential circuit
Please bring a functional random number generator to class on Thursday(3/13).
Outline
• Review– D latch
• Applications• Flip-flops– D flip-flops• Reset
– JK flip-flops– T flip-flop
D Latch
Using a Latch as a Memory Element
Caution for a D latch: once a clock enables a D latch, the outputchanges as soon as the input changes – this is not desirable if you do notwant the output to change continuously and all the latches use a common clock.
Uses of Flip-flops
D Flip-Flop
Negative Edge triggered D Flip-FlopClk=1
1 0
Y=D
hold
Negative Edge triggered D Flip-FlopClk=0
0 1
Q=Yhold
Negative Edge triggered D Flip-FlopClk=1
1 0
Y=1
hold
1 0
Negative Edge triggered D Flip-FlopClk=0
0 1
Q=Yhold
1 0->1
Verilog Modeling
I1 I2
𝐶𝑙𝑘𝑏
Positive Edge Triggered D Flip-flop
I1 I2
𝐶𝑙𝑘𝑏
D-Type Positive Edge Triggered Flip-Flop (CLK=0)
0
0
1
1
CLK =0, maintain the present state
D-Type Positive Edge Triggered Flip-Flop
0
0→ 1
1
1 → 0
Q changes to 01
10
D=0 as Clk=0→ 1
D-Type Positive Edge Triggered Flip-Flop
1
0→ 1
1 → 0
1 → 1
Q changes 10
01
D=1 as Clk=0→ 1
D-Type Positive Edge Triggered Flip-Flop
0 → 1
1
S
The flip-flop is unresponsive to changes in D1
1
D=0→ 1 as Clk=1
S’
S’
Please explore different possible value of S on your own.This will work even for S=R=1 and S=R=0.revise
Symbol of D Flip-Flops
reset and preset
• When power is first turned on, the state of the flip-flops is unknwon.– Reset is used to initialize the output to a
0.– Preset is used to initialize the output to
a 1.
Reset Feature
0
1
1
0
0
When Reset is 0, Q is set to 0.
D Flip-flop with reset
Typo in the book. Should be 1 instead.
JK Flip-FlopsD=JQ’+K’Q
The next value of D is determined by JQ’+K’Q.At the rising edge of D Flip-flop, Q is updated with the value of D.
Positive edge D flip-flop
D=JQ’+K’Q
• J=1,K=1→D=Q’• J=0, K=0 →D=Q• J=0, K=1 →D=0• J=1, K=0 →D=Q’+Q=1
Verilog Implementation
T Flip-Flop
T Flip-Flop from D Flip-Flop
D=TQ’+T’Q
If T=1, D=Q’If T=0, D=Q.
Q is updated with D at the next rising edge.
𝑄DT
rst
Verilog Implementation of a T-FF
𝑄DT
rst