lecture 12 dram

8/19/2019 Lecture 12 Dram

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EE1411

MemorySTMicro/Intel/UCSD/THNU

DRAM: Dynamic RAM DRAM: Dynamic RAM Store their contents as charge on a capacitor rather

than in a feedback loop.

1T dynamic RAM cell has a transistor and a capacitor


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EE1412


DRAM Read DRAM Read

1. bitline precharged to VDD/2

2. wordline rises, cap. shares it

charge with bitline, causing a

voltage V

3. read disturbs the cell

content at x, so the cell must be

rewritten after each read

bit cell

cell DD

C C

C V

V +

=∆2


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EE1413


DRAM writeDRAM writeOn a write, the bitline is driven

high or low and the voltage is

forced to the capacitor


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EE1414


DRAM Array DRAM Array


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EE1415


DRAM DRAM

Bitline cap is an order of magnitude

larger than the cell causing !ery small

!oltage s"ing. A sense amplifier is used.

Three different bitline architectures

open folded and t"isted offer differentcompromises bet"een noise and area.


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EE1416


DRAM in a nutshell DRAM in a nutshell

Based on capaciti!e #non$regenerati!e%

storage

&ighest density #'b(cm)%

*arge e+ternal memory #'b% or embedded

,RAM for image graphics multimedia-

eeds periodic refresh $/ o!erhead slo"er


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7MemorySTMicro/Intel/UCSD/THNU


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Classical DRAM OrganizationClassical DRAM Organization

(square)(square)r ow

de

coder

rowaddress

Column Selector & I/O Circuits Column

Address

data

RAM Cell Array

word (row) select

bit (data) lines

ach intersection represents

a 1!" D#$% &ell


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DRAM logical organization (4DRAM logical organization (4

Mbit)Mbit)


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EE14110


DRAM hysical organization (4 Mbit!"#$)DRAM hysical organization (4 Mbit!"#$)


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EE14111MemorySTMicro/Intel/UCSD/THNU

AD

OE_L

2'() x *

D#$%9 8

WE_L

0ontrol Signals #RAS* 0AS* 2E* 3E*% are all acti!e lo"

,in and ,out are combined #,%

2E* is asserted #*o"% 3E* is disasserted #&igh%

5 , ser!es as the data input pin

2E* is disasserted #&igh% 3E* is asserted #*o"%

5 , is the data output pin

Ro" and column addresses share the same pins #A% RAS* goes lo" 6ins A are latched in as ro" address

0AS* goes lo" 6ins A are latched in as column address

RAS(0AS edge$sensiti!e

CAS_LRAS_L%ogic Diagram o& a 'yical DRAM %ogic Diagram o& a 'yical DRAM


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DRAM OerationsDRAM Oerations 2rite

Charge bitline HIH or !O" and set wordline HIH Read

#it line is $recharged to a %oltage halwaybetween HIH and !O"' and then theword line is set HIH

e$ending on the charge in the ca$' the

$recharged bitline is $ulled slightly higher or lower

Sense Am$ etects change

E+plains "hy 0ap can7t shrink *eed to suiciently dri%e bitline

Increase density +, increase $arasiticca$acitance

Word

Line

Bit Line

C

SenseAmp

.

.

.


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AD

OE_L

2'() x *

D#$%9 8

WE_LCAS_LRAS_L

O+

$ #ow $ddress

-+

un

#ead $ccess

"ime

Output nable

Dela0

&$+

#$+

&ol $ddress #ow $ddress un &ol $ddress

D igh Data Out

D#$% #ead &0cle "ime

arl0 #ead &0cle4 O+ asserted before &$+ ate #ead &0cle4 O+ asserted after &$+

E!ery ,RAM access begins at

The assertion of the RAS*

) "ays to readearly or late !. 0AS

un Data Out igh

DRAM Read 'imingDRAM Read 'iming


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AD

OE_L

2'() x *

D#$%9 8

WE_LCAS_LRAS_L

-+

$ #ow $ddress

O+

un

-# $ccess "ime -# $ccess "ime

&$+

#$+

&ol $ddress #ow $ddress un &ol $ddress

D un un Data 5n Data 5n un

D#$% -# &0cle "ime

arl0 -r &0cle4 -+ asserted before &$+ ate -r &0cle4 -+ asserted after &$+

E!ery ,RAM access begins at

The assertion of the RAS*

) "ays to "riteearly or late !. 0AS

DRAM rite 'imingDRAM rite 'iming


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A 89 ns #tRA0% ,RAM can

perform a ro" access only e!ery 119 ns #tR0%

perform column access #t0A0% in 1: ns but timebet"een column accesses is at least ;: ns #t60%.

5


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#*'ransistor Memory Cell (DRAM)#*'ransistor Memory Cell (DRAM)

2rite

1. ,ri!e bit line

).. Select ro"

Read

1. 6recharge bit line

).. Select ro"

;. 0ell and bit line share charges

5 @ery small !oltage changes on the bit line

4. Sense #fancy sense amp%

5 0an detect changes of 1 million electrons

:. 2rite restore the !alue

Refresh

1. ust do a dummy read to e!ery cell.

row select

bit


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DRAM architectureDRAM architecture


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Cell read: correct re&resh is goal Cell read: correct re&resh is goal

b s

s

BLSN BL BL

C C

C V V V V V

+−=−=∆ )('


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+ense Amli&ier +ense Amli&ier


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DRAM technological requirementsDRAM technological requirements

Cnlike SRAM large 0b must be charged by small sense DD. Thisis slo".

Make 0b small backbias unction cap. limit blocksiFe

Backbias generator reGuired. Triple "ell.

6re!ent threshold loss in "l pass @' / @ccsH@Tn

ReGuires another !oltage generator on chip

ReGuires @Tn"l/ @tnlogic and thus thicker o+ide than logic

Better dynamic data retention as there is less subthreshold

loss.

,RAM 6rocess unlike *ogic processI

Must create >large? 0s #19..;9fD% in smallest possible area

#$/ ) poly$/ trench cap $/ stacked cap%


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Re&reshing O,erhead Re&reshing O,erhead *eakage

unction leakage e+ponential "ith tempI

)-: msec J =99 0

,ecreases noise margin destroys info

All columns in a selected ro" are refreshed "hen read

0ount through all ro" addresses once per ; msec. #no

"rite possible then%

3!erhead J 19nsec read time for =1K)L=1K)84Mb

=1K)L1e$=(;e$; ).NO

ReGuires additional refresh counter and


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RAM-.n 0chi$

RAMController

address

Memory1imingController

#us ri%ers

n

n/-

w

1c + 1cycle 2 1controller 2 1dri%er

DRAM Memory +ystemsDRAM Memory +ystems


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EE141 24MemorySTMicro/Intel/UCSD/THNU

DRAM er&ormanceDRAM er&ormance

DRAM (Read/Write) Cycle Time

DRAM (Read/Write)

Acce!! Time

! 2"1# $%y&

DRAM (Read/Write) Cycle Time"

! '$ re*+e,t ca, y+

i,itiate a, acce!!&

DRAM (Read/Write) Acce!!

Time"

! '$ *+ic-ly $ill y+ .et$%at y+ $a,t ,ce y+

i,itiate a, acce!!&

DRAM a,d$idt% imitati,"

! imited y Cycle Time

"ime$ccess "ime

&0cle "ime


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-ast age Mode-ast age Mode

OerationOeration

Dast 6age Mode ,RAM + M >SRAM? to sa!e a ro"

After a ro" is read into the register

3nly 0AS is needed to access

other M$bit blocks on that ro"

RAS* remains asserted "hile

0AS* is toggled

$ #ow $ddress

&$+

#$+

&ol $ddress &ol $ddress

1st %!bit $ccess

N r

o # $

N col$

D#$%

&olumn

$ddress

%!bit Output

M %it$

6 x % 7#$%8

#ow

$ddress

&ol $ddress &ol $ddress

2nd %!bit 3rd %!bit 9th %!bit


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age Mode DRAM .andwidth /"amleage Mode DRAM .andwidth /"amle 6age Mode ,RAM E+ample

18 bits + 1M ,RAM chips #4 nos% in 84$bit module #= MBmodule%

89 ns RASH0AS access timeP ): ns 0AS access time

*atency to first access89 ns *atency to subseGuentaccesses): ns

119 ns read("rite cycle timeP 49 ns page mode access time P):8 "ords #84 bits each% per page

Band"idth takes into account 119 ns first cycle 49 ns for 0AS cycles

Band"idth for one "ord = bytes ( 119 ns 8K.;: MB(sec

Band"idth for t"o "ords 18 bytes ( #119H49 ns% 191.N; MB(sec

6eak band"idth = bytes ( 49 ns 1K9.N; MB(sec

Ma+imum sustained band"idth #):8 "ords L = bytes% ( # 119ns H):8L49ns% 1==.N1 MB(sec


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4 'ransistor Dynamic Memory 4 'ransistor Dynamic Memory

Re&o'e te MOS/re$i$tor$

*ro& te SRAM &e&or+ cell

,-l.e $tore

on te r-in o* M0 -n M21.t it i$ el tere onl+ %+

te c--cit-nce on to$e

noe$

Le-3-4e -n $o*t5error$ &-+e$tro+ '-l.e


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-irst #' DRAM (40 Density)-irst #' DRAM (40 Density)

Te6-$ In$tr.&ent$

TMS7 intro.ce

09:

NMOS; 0M0; TTL I/O 0T Cell; Oen 1it Line;

Di**erenti-l Sen$e A&

,


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#$1 DRAM (Double oly Cell)#$1 DRAM (Double oly Cell)

Mo$te3M>700?;intro.ce 09::

Are$$ &.ltile6

-4e &oe

NMOS; 20M

,


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$40 DRAM$40 DRAM

Intern-l,%%4ener-tor

1oo$te Worline-n Acti'eRe$tore@ ! eli&in-te ,tlo$$ *or

0B

67 ino.t


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23$0 DRAM 23$0 DRAM

ole %itline-rcitect.re ! Co&&on &oe noi$e to

co.lin4 to 1/L$ ! E-$+ 5-cce$$

NMOS 20M ! ol+ 0 l-te

! ol+ 2 (ol+cie) 54-te;W/L

! &et-l 51/L

re.n-nc+


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#M DRAM #M DRAM

Trile ol+ l-n-r cell;

0M

! ol+0 54-te; W/L

! ol+2 !l-te

! ol+ (ol+cie) 51/L

! &et-l 5W/L $tr-

,/2 %itlinere*erence; ,/2 cell

l-te


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On*chi oltage 5eneratorsOn*chi oltage 5enerators

o#er $.lie$ ! *or lo4ic -n &e&or+

rec-r4e 'olt-4e

! e4 ,DD/2 *orDRAM 1itline

%-c34-te %i-$

! re.ce le-3-4e WL $elect o'erri'e

(DRAM)


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Charge um Oerating rincileCharge um Oerating rincile

23in

3in

4 23in

23in

3in d@

d@3o

3in + d3 5 3in 2 d3 23o

3o + -63in 2 -6d3 4 -63in

Charge Phase

Discharge Phase


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oltage .ooster &or %oltage .ooster &or %

C C!

3hi d@ 3+3hi

C!C

3c 4 3hi

3hi 3c(7) 4 3hi2

3 4 3hi 2

3hi

d


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.ac1gate bias generation.ac1gate bias generation

8se charge $um$

#ac9gate bias:

Increases 3t ;, reduces lea9age

< reduces C= o nMOS1 when a$$lied to $;well

(tri$le well $rocess>)'

smaller C= ;, smaller Cb ? larger readout @3


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dd 6 2 5enerationdd 6 2 5eneration)!

1!

1!

9.:!

9.:!

1.:!

1!

9.:!

1

!

@tn Q@tpQ9.:!

u ) u6


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4M DRAM 4M DRAM

D $t-c3e or trenc cell

CMOS 70M

60? intro.ce Sel* Re*re$

1.il cell in 'ertic-li&en$ion 5$rin3 -re-

#ile &-int-inin4 *cell c--cit-nce


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+tac1ed*Caacitor Cells+tac1ed*Caacitor Cells

6oly plate

&itachi 84Mbit ,RAM 0ross Section

Samsung 84Mbit ,RAM 0ross Section


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/,olution o& DRAM cell structures/,olution o& DRAM cell structures


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.uried +tra 'rench Cell .uried +tra 'rench Cell


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./+' cell Dimensions./+' cell Dimensions

,eep Trench etch "ith

!ery high aspect ratio


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23$0 DRAM 23$0 DRAM

ole %itline-rcitect.re ! Co&&on &oe noi$e to

co.lin4 to 1/L$

! E-$+ 5-cce$$

NMOS 20M ! ol+ 0 l-te

! ol+ 2 (ol+cie) 54-te;W/L

! &et-l 51/L

re.n-nc+


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+tandard DRAM Array Design+tandard DRAM Array Design

/"amle/"amle


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49MemorySTMicro/Intel/UCSD/THNUB* direction col

2* direction

#ro"%

B cells

(-D-D)

0M cells +

B0

lobal "! decode 2 dri%ers

!ocal "!

ecode

C o

l u m n $ r e d e c o d e

2

DRAM Array /"amle (cont7d)DRAM Array /"amle (cont7d)


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DRAM Array /"amle (cont d)DRAM Array /"amle (cont d)

D0- Array *mat+0 ( -D "! -7BE SA)

Interlea%ed S A & Hierarchical Row ecoder/ri%er

(shared bit lines are not shown)

)94=

-D

):8+):8

B


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+tandard DRAM Design -eature+tandard DRAM Design -eature

・ &ea!y dependence on technology・ The ro" circuits are fully different

from SRAM.・ Almost al"ays analogue circuit

design・ 0A, Spice$like circuits simulator

Dully handcrafted layout

lecture 12 dram

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