Lecture 10:

Sequential Networks: Timing and

Retiming

CSE 140: Components and Design Techniques for

Digital Systems

Diba Mirza

Dept. of Computer Science and Engineering

University of California, San Diego

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So far ….

Combinational

CLK

Logic-level analysis

This lecture …

• Our seemingly logically correct design can go wrong

• How can we design a circuit that works under real constraints?

Combinational

CLK

Timing Constraints of flip flops

DQ

Q’

CLK

4

• The input to a flip-flop should be stable for a period of time

around the rising edge of the clock

Input Constraints: Set up and hold time

5

CLK

tsetup

D

thold

ta

I. Setup time: tsetup

Time before the clock edge that data must be stable (i.e.

not change)

II. Hold time: thold

Time after the clock edge that data must be stable

Aperture time: ta

Time around clock edge that data must be stable (ta = tsetup + thold)

D

Q

Q’

PIQ: Which of the following signals can cause a setup-time

violation for this flip flop?

A. The input signal D(t)

B. The output signal Q(t)

C. Both A and B

D. None of the above

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DQ

Q’

D(t)

CLK

Q(t)

Output characteristics of flip flops

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I. Minimum delay of Q

Time after the clock edge for which Q is sure to not

change

II. Maximum delay of Q

Time after the clock edge following which Q is sure to

have stabilized

D

Q

Q’

Output characteristics of flip flops

I. Min delay of flip flop, also called Contamination delay or min CLK to Q

delay: tccq

Time after clock edge that Q might be unstable (i.e., start changing)

II. Max delay of flip flop, also called Propagation delay or maximum CLK to

Q delay: tpcq

Time after clock edge that the output Q is guaranteed to be stable (i.e., to

stop changing)

CLK

tccq

tpcq

Q

8

D

Q

Q’

Fact 1: Once a flip flop has been ‘built’ we are stuck with its

timing characteristics: tsetup , thold, tccq, tpcq

Now let’s look at the timing characteristics of the combinational

part

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R1 Combinational

CLK

R2

CLK

D1 Q1 D2

Combinational Logic Timing

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I. Min delay of a gate, also called Contamination delay: tcd

Minimum time from when an input changes until the output starts to change

II. Max delay of a gate, also called Propagation delay: tpd

Maximum time from when an input changes until the output is guaranteed to

reach its final value (i.e., stop changing)

Combinational Logic: Output timing constraints

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A

B

C

D

Y

PI Q: Which path in the above circuit determines the contamination delay of

the circuit (assuming the delay of all the gates is the same)?

A. Green path

B. Red path

C. Both

D. Neither

Combinational Logic: Output timing constraints

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A

B

C

D

Y

PI Q: Which path in the above circuit determines the propagation delay of

the circuit (assuming the delay of all the gates is the same)?

A. Green path

B. Red path

C. Both

D. Neither

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• If the input to a flip flop doesn’t stabilize in time BEFORE the

rising edge of the clock we have a setup time violation

CL

CLKCLK

R1 R2

Q1 D2

(a)

CLK

Q1

D2

(b)

Tc

Timing Issues

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Why would the input (D2) not stabilize in time? •D2 changes because of Q1

•Flip flop has maximum delay, Q1 stabilizes after this maximum

delay from the clock edge

•The combinational circuit has a maximum delay, so even after Q1

has stabilized, D2 takes a while to stabilize

•If D2 doesn’t stabilize on time we have a setup violation

CL

CLKCLK

R1 R2

Q1 D2

(a)

CLK

Q1

D2

(b)

Tc

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• If the input to a flip flop changes too quickly AFTER the rising

edge of the clock we have a hold time violation

CL

CLKCLK

R1 R2

Q1 D2

(a)

CLK

Q1

D2

(b)

Tc

Timing Issues

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Why would the input (D2) change too quickly? • D2 changes because of Q1

• Flip flop has minimum delay, Q1 will start changing only after this

minimum delay

• The combinational circuit has a minimum delay, after which the

output of CL (D2) will start reacting to a changing input.

• If D2 starts changing too quickly we have a hold time violation

CL

CLKCLK

R1 R2

Q1 D2

(a)

CLK

Q1

D2

(b)

Tc

Why timing in Sequential Circuits can go wrong?

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CL

CLKCLK

R1 R2

Q1 D2

(a)

CLK

Q1

D2

(b)

Tc

Which of the following violations would occur if the min delay of

R1 was 0 and the combinational circuit was just a wire?

A. Hold time violation for R2

B. Setup violation for R2

C. Hold time violation for R1

D. Setup violation for R1

E. None of the above

Meeting the hold time constraint

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To meet the hold time constraint:

CL

CLKCLK

R1 R2

Q1 D2

(a)

CLK

Q1

D2

(b)

Tc thold < min delay(flipflop) +

min delay(combinational)

• Input to a flip-flop comes from the output of another flip flop,

through a combinational circuit

• The flipflop and combinational circuit have a min and max delay

Why timing in Sequential Circuits can go wrong?

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• Input to a flip-flop comes from the output of another flip flop,

through a combinational circuit

• The flipflop and combinational circuit have a min and max delay

CL

CLKCLK

R1 R2

Q1 D2

(a)

CLK

Q1

D2

(b)

Tc

Which of the following violations would

occur if the max delay of R1 was 0 and the

max delay of the combinational circuit

was equal to the clock period

A. Hold time violation for R2

B. Setup violation for R2

C. Hold time violation for R1

D. Setup violation for R1

E. None of the above

Meeting the setup time constraint

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To meet the setup time constraint:

CL

CLKCLK

R1 R2

Q1 D2

(a)

CLK

Q1

D2

(b)

Tc Tc ≥ max delay(flipflop) +

max delay(combinational)+ tsetup

• Input to a flip-flop comes from the output of another flip flop,

through a combinational circuit

• The flipflop and combinational circuit have a min and max delay

Formalizing the hold time constraint in

Sequential Circuits

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To meet the hold time constraint:

thold < min delay(flipflop) +

min delay(combinational)

thold < tccq + tcd

CLK

Q1

D2

tccq

tcd

thold

CL

CLKCLK

Q1 D2

R1 R2

Formalizing the setup time constraints in

Sequential Circuits

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To meet the setup time constraint:

Tc ≥ max delay(flipflop) +

max delay(combinational)+ tsetup

Tc ≥ tpcq + tpd + tsetupCLK

Q1

D2

Tc

tpcq

tpd

tsetup

CL

CLKCLK

Q1 D2

R1 R2

Timing Analysis

CLK CLK

A

B

C

D

X'

Y'

X

Y

Timing Characteristics

tccq = 30 ps

tpcq = 50 ps

tsetup = 60 ps

thold = 70 ps

tpd = 35 ps

tcd = 25 pstpd (CL)=

tcd (CL)=

Setup time constraint:

Tc ≥

fc = 1/Tc =

Hold time constraint:

tccq + tcd (CL)> thold ?

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Timing Analysis

CLK CLK

A

B

C

D

X'

Y'

X

Y

Timing Characteristics

tccq = 30 ps

tpcq = 50 ps

tsetup = 60 ps

thold = 70 ps

tpd = 35 ps

tcd = 25 pstpd = 3 x 35 ps = 105 ps

tcd = 25 ps

Setup time constraint:

Tc ≥ (50 + 105 + 60) ps = 215 ps

fc = 1/Tc = 4.65 GHz

Hold time constraint:

tccq + tcd > thold ?

(30 + 25) ps > 70 ps ? No!

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Fixing Hold Time ViolationTiming Characteristics

tccq = 30 ps

tpcq = 50 ps

tsetup = 60 ps

thold = 70 ps

tpd = 35 ps

tcd = 25 pstpd =

tcd =

Setup time constraint:

Tc ≥

fc =

Hold time constraint:

tccq + tcd > thold ?

CLK CLK

A

B

C

D

X'

Y'

X

Y

Add buffers to the short paths:

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Fixing Hold Time ViolationTiming Characteristics

tccq = 30 ps

tpcq = 50 ps

tsetup = 60 ps

thold = 70 ps

tpd = 35 ps

tcd = 25 pstpd = 3 x 35 ps = 105 ps

tcd = 2 x 25 ps = 50 ps

Setup time constraint:

Tc ≥ (50 + 105 + 60) ps = 215 ps

fc = 1/Tc = 4.65 GHz

Hold time constraint:

tccq + tcd > thold ?

(30 + 50) ps > 70 ps ? Yes!

CLK CLK

A

B

C

D

X'

Y'

X

Y

Add buffers to the short paths:

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Midterm review

• SR latch

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SR latch timing diagrams

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What do inputs A & B do?

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30

FSM design example

• Design an overlapping finite string pattern

recognizer

– output is 1 whenever the input sequences 101 and 011

are observed

Sequential circuit design

Present

State

Next state Output

ZW=0 W=1

00 10 11 0

01 00 00 0

10 10 00 0

11 10 00 1

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FSM Design Example• Write the state table and implement the

following state machine:

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