Digital Systems Design

Lecture 03: Course Objectives and

Introduction (cnt’d)

The Catholic University of America

School of Engineering Department of Electrical Engineering and Computer

Science

CSC / EE 519 - Summer 2013

May 30th, 2013

Esam El-Araby

aly@cua.edu

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Outline

Introduction

Devices

HDLs (Hardware Description Languages)

HDLs and VHDL

Why Use VHDL?

Domains and Levels of Modeling

EDA (Electronic Design Automation) Tools

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HDLs and VHDL

With the maturity of PLDs in mid 70’s, the need for digital design automation made HDLs a necessity

Some HDLs with limited capabilities PALASM, ABEL, CUPL, and

Verilog from Synopsys

HDLs were originally used to describe H/W for the purpose of: modeling

simulation

documentation

Currently available software tools for HDLs include: Simulators for design verification

Synthesizers for automatic H/W generation

In search for a standard design and documentation tool for VHSIC project, the DoD established requirements for a standard HDL (VHDL)

The DoD requirements indicated that VHDL should be usable for: Design Documentation

High-Level Design

Simulation

Synthesis

Testing of H/W

A Driver for a Physical Design Tool

VHDL became the IEEE standard HDL in December 1987

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Why Use VHDL?

Power and Flexibility Language constructs for the description of complex control

logic

Multiple levels (Behavioral, Data flow, and Structural) of design

description for controlling design implementation

Design libraries and the creation of reusable components

support

Provision of design hierarchies to create modular designs

Device-Independent Design

Portability (Tool and platform neutral)

Benchmarking Capabilities using different device

architectures (CPLDs, and FPGAs) and different

synthesizers

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Why Use VHDL? (cnt’d)

Quick Time-to-Market and Low Cost

Quick design iterations

No fabrication costs

ASIC Migration

The efficiency that VHDL generates allows the

product to hit the market quickly if synthesized

to a CPLD or FPGA

When production volumes reach appropriate

levels, VHDL facilitates the development of an

ASIC

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Domains and Levels of Modeling

Functional Structural

Geometric

high level of

abstraction

low level of

abstraction

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Domains and Levels of Modeling (cnt’d)

Functional Structural

Geometric

Algorithm

(behavioral)

Register-Transfer

Language

Boolean Equation

Differential Equation

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Domains and Levels of Modeling (cnt’d)

Functional Structural

Geometric

Algorithm

(behavioral)

Register-Transfer

Language

Boolean Equation

Differential Equation

Processor-Memory

Switch

Register-Transfer

Gate

Transistor

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Domains and Levels of Modeling (cnt’d)

Functional Structural

Geometric

Algorithm

(behavioral)

Register-Transfer

Language

Boolean Equation

Differential Equation

Processor-Memory

Switch

Register-Transfer

Gate

Transistor Polygons

Sticks

Standard Cells

Floor Plan

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Outline

Introduction

Devices

HDLs (Hardware Description Languages)

EDA (Electronic Design Automation) Tools

Generic Design Flow

Basic Design Methodology

Synthesis

Place and Route

EDA Vendors

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Generic Design Flow

Download to FPGA

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Basic Design Methodology

Requirements

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Basic Design Methodology

RTL Model

Requirements

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Basic Design Methodology

Simulate RTL Model

Requirements

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Basic Design Methodology

Simulate

Synthesize

Gate-level

Model

RTL Model

Requirements

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Basic Design Methodology

Simulate

Synthesize

Gate-level

Model Simulate

RTL Model

Requirements

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Basic Design Methodology

Simulate

Synthesize

Gate-level

Model Simulate

Place & Route

Timing

Model

RTL Model

Requirements

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Basic Design Methodology

Simulate

Synthesize

Gate-level

Model Simulate

Place & Route

Timing

Model Simulate

RTL Model

Requirements

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Basic Design Methodology

Simulate

Synthesize

Gate-level

Model Simulate Test Bench

Place & Route

Timing

Model Simulate

RTL Model

Requirements

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Basic Design Methodology

Simulate

Synthesize

Gate-level

Model Simulate Test Bench

Place & Route ASIC or FPGA

Timing

Model Simulate

RTL Model

Requirements

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Synthesis (Mapping)

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Placing

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Routing

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EDA Vendors

ALDEC, Inc (www.aldec.com)

Ansoft (www.ansoft.com)

Artisan Components (www.artisan.com)

Avant! (www.avanticorp.com)

Cadence (www.cadence.com)

IKOS Systems, Inc. (www.ikos.com)

Innoveda, Inc. (www.innoveda.com)

Mentor Graphics (www.mentor.com)

Numerical Technologies, Inc. (www.numeritech.com)

Simplex Solutions, Inc. (www.simplex.com)

Synopsys (www.synopsys.com)

Synplicity, Inc. (www.synplicity.com)

TransEDA PLC (www.transeda.com)

Verisity Design (www.verisity.com)

Virage Logic (www.viragelogic.com)

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Suggested Readings

Title: Fundamentals of Digital Logic with VHDL Design (with CD-ROM) Authors: Stephen Brown, and Zvonko Vranesic Publisher: McGraw-Hill Science/Engineering/Math; 3 edition (April 14, 2008) ISBN-10: 0077221435 ISBN-13: 978-0077221430

Title: HDL Chip Design: A Practical Guide for Designing, Synthesizing and Simulating ASICs and FPGAs Using VHDL or Verilog Authors: Douglas J. Smith, and Alex Zamfirescu Publisher: Doone Publications (March 1998) ISBN-10: 0965193438 ISBN-13: 9780965193436

Title: The Design Warrior's Guide to FPGAs: Devices, Tools and Flows Author: Clive "Max" Maxfield Publisher: Newnes (April 26, 2004) ISBN-10: 0750676043 ISBN-13: 978-0750676045

Up-to-date FPD research appears in the published proceedings of several conferences:

Proc. IEEE Int'l Custom Integrated Circuits Conf., IEEE.

Proc. Int'l Conf. Computer-Aided Design (ICCAD), IEEE CS Press, Los Alamitos, Calif.

Proc. Design Automation Conference (DAC), IEEE CS Press.

Int'l ACM Symp. Field-Programmable Gate Arrays, Assoc. for Computing Machinery, New York.

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Terminology

CPLD (complex PLD): an arrangement of multiple SPLD-like blocks on a single chip. Alternative names are enhanced PLD (EPLD), superPAL, and megaPAL.

FPD (field-programmable device): any integrated circuit used for implementing digital hardware that allows the end user to configure the chip to realize different designs. Programming such a device often involves placing the chip into a special programming unit, but some chips can also be configured "in system." Another name for FPDs is programmable logic devices (PLDs); although PLDs are the same type of chips as FPDs, we prefer the term FPD because historically PLD denoted relatively simple devices.

FPGA (field-programmable gate array): an FPD featuring a general structure that allows very high logic capacity. Whereas CPLDs feature logic resources with a wide number of inputs (AND planes), FPGAs offer narrower logic resources. FPGAs also offer a higher ratio of flip-flops to logic resources than do CPLDs.

Interconnect: the wiring resources in an FPD.

Logic block: a relatively small circuit block replicated in an FPD array. A circuit implemented in an FPD is first decomposed into smaller subcircuits that can each be mapped into a logic block. The term occurs mostly in the context of FPGAs but can also refer to a block of circuitry in a CPLD.

Logic capacity: the amount of digital logic that we can map into a single FPD, usually measured in units of the equivalent number of gates in a traditional gate array. In other words, we measure an FPD's capacity as its comparable gate array size. Thus, we can refer to logic capacity as the number of two-input NAND gates.

Logic density: the amount of logic per unit area in an FPD.

PAL (programmable array logic): a relatively small FPD containing a programmable AND plane followed by a fixed-OR plane.

PLA (programmable logic array): a relatively small FPD that contains two levels of programmable logic an AND plane and an OR plane. (Although PLA structures are sometimes embedded into full-custom chips, we refer here only to user-programmable PLAs provided as separate integrated circuits).

Programmable switch: a user-programmable switch that can connect a logic element to an interconnect wire or one interconnect wire to another.

Speed performance: the maximum operable speed of a circuit implemented in an FPD. For combinational circuits, it is set by the longest delay through any path, and for sequential circuits, it is the maximum clock frequency at which the circuit functions properly.

SPLD (simple PLD): usually a PLA or a PAL.