lecture 0: introductionvlsi.hongik.ac.kr/lecture/이전 강의 자료/vlsi/2...lecture 0:...
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Introduction toCMOS VLSI
DesignDesign
Lecture 0: IntroductionLecture 0: Introduction
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Introduction Introduction (See Wikipedia)
Integrated circuits: many transistors on one chip Integrated circuits: many transistors on one chip. Very Large Scale Integration (VLSI): very many C l t M t l O id S i d t Complementary Metal Oxide Semiconductor
– Fast, cheap, low power transistors T d H t b ild i l CMOS hi Today: How to build your own simple CMOS chip
– CMOS transistorsB ildi l i f i– Building logic gates from transistors
– Transistor layout and fabrication Rest of the course: How to build a good CMOS chip
CMOS VLSI Design0: Introduction Slide 2
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Silicon LatticeSilicon Lattice Transistors are built on a silicon substrate Transistors are built on a silicon substrate Silicon is a Group IV material F t l l tti ith b d t f i hb Forms crystal lattice with bonds to four neighbors
Si SiSi
Si SiSi
S SS Si SiSi
CMOS VLSI Design0: Introduction Slide 3
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DopantsDopants Silicon is a semiconductor Silicon is a semiconductor Pure silicon has no free carriers and conducts poorly Addi d t i th d ti it Adding dopants increases the conductivity Group V: extra electron (n-type) G III i i l t ll d h l ( t ) Group III: missing electron, called hole (p-type)
As SiSi
Si SiSi
B SiSi
Si SiSi-
+
+
-
Si SiSi Si SiSi
CMOS VLSI Design0: Introduction Slide 4
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p n Junctionsp-n Junctions A junction between p type and n type semiconductor A junction between p-type and n-type semiconductor
forms a diode. Current flows only in one direction Current flows only in one direction
t tp-type n-type
anode cathode
CMOS VLSI Design0: Introduction Slide 5
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nMOS TransistornMOS Transistor Four terminals: gate source drain body Four terminals: gate, source, drain, body Gate – oxide – body stack looks like a capacitor
G t d b d d t– Gate and body are conductors– SiO2 (oxide) is a very good insulator
C ll d t l id i d t (MOS)– Called metal – oxide – semiconductor (MOS) capacitorEven though gate is
GateSource DrainPolysilicon
– Even though gate is no longer made of metal
SiO2
n+
p bulk Si
n+
CMOS VLSI Design0: Introduction Slide 6
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nMOS OperationnMOS Operation Body is commonly tied to ground (0 V) Body is commonly tied to ground (0 V) When the gate is at a low voltage:
P t b d i t l lt– P-type body is at low voltage– Source-body and drain-body diodes are OFF
N t fl t i t i OFF– No current flows, transistor is OFFGateSource Drain
Polysilicon
SiO2
0n+
p bulk Si
n+DS
CMOS VLSI Design0: Introduction Slide 7
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nMOS Operation ContnMOS Operation Cont. When the gate is at a high voltage: When the gate is at a high voltage:
– Positive charge on gate of MOS capacitorN ti h tt t d t b d– Negative charge attracted to body
– Inverts a channel under gate to n-typeN t fl th h t ili f– Now current can flow through n-type silicon from source through channel to drain, transistor is ON
GateSource DrainGateSource Drain
SiO2
Polysilicon
n+
p bulk Si
n+D
1
S
CMOS VLSI Design0: Introduction Slide 8
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pMOS TransistorpMOS Transistor Similar but doping and voltages reversed Similar, but doping and voltages reversed
– Body tied to high voltage (VDD)G t l t i t ON– Gate low: transistor ON
– Gate high: transistor OFFB bbl i di t i t d b h i– Bubble indicates inverted behavior
GateSource DrainPolysilicon
SiO2
n bulk Si
p+ p+
CMOS VLSI Design0: Introduction Slide 9
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Power Supply VoltagePower Supply Voltage GND = 0 V GND = 0 V In 1980’s, VDD = 5V V h d d i d VDD has decreased in modern processes
– High VDD would damage modern tiny transistorsL V– Lower VDD saves power
VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …
CMOS VLSI Design0: Introduction Slide 10
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Transistors as SwitchesTransistors as Switches We can view MOS transistors as electrically We can view MOS transistors as electrically
controlled switches Voltage at gate controls path from source to drain Voltage at gate controls path from source to drain
d
g = 0
d
g = 1
d
gs
d
s s
nMOS OFF ON
d d d
OFFgs s s
pMOS ON OFF
CMOS VLSI Design0: Introduction Slide 11
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CMOS InverterCMOS Inverter
A Y VDD0
1
A Y
A YGND
A Y
CMOS VLSI Design0: Introduction Slide 12
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CMOS InverterCMOS Inverter
A Y VDD0
1 0 OFFA=1 Y=0
ONA Y
GNDA Y
CMOS VLSI Design0: Introduction Slide 13
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CMOS InverterCMOS Inverter
A Y VDD0 1
1 0 ONA=0 Y=1
OFFA Y
GNDA Y
CMOS VLSI Design0: Introduction Slide 14
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CMOS NAND GateCMOS NAND GateA B Y
0 00 0
0 1 Y1 0
1 1A
B
CMOS VLSI Design0: Introduction Slide 15
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CMOS NAND GateCMOS NAND GateA B Y
0 0 1 ON ON0 0 1
0 1A=0
Y=1ON
1 0
1 1
A 0
B=0
OFF
B=0 OFF
CMOS VLSI Design0: Introduction Slide 16
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CMOS NAND GateCMOS NAND GateA B Y
0 0 1 OFF ON0 0 1
0 1 1A=0
Y=1OFF
1 0
1 1
A 0
B=1
OFF
B=1 ON
CMOS VLSI Design0: Introduction Slide 17
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CMOS NAND GateCMOS NAND GateA B Y
0 0 1 ON OFF0 0 1
0 1 1A=1
Y=1ON
1 0 1
1 1
A 1
B=0
ON
B=0 OFF
CMOS VLSI Design0: Introduction Slide 18
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CMOS NAND GateCMOS NAND GateA B Y
0 0 1 OFF OFF0 0 1
0 1 1A=1
Y=0OFF
1 0 1
1 1 0
A 1
B=1
ON
B=1 ON
CMOS VLSI Design0: Introduction Slide 19
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CMOS NOR GateCMOS NOR GateA B Y
0 0 1 A0 0 1
0 1 0A
B1 0 0
1 1 0
BYY
CMOS VLSI Design0: Introduction Slide 20
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3 input NAND Gate3-input NAND Gate Y pulls low if ALL inputs are 1 Y pulls low if ALL inputs are 1 Y pulls high if ANY input is 0
CMOS VLSI Design0: Introduction Slide 21
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3 input NAND Gate3-input NAND Gate Y pulls low if ALL inputs are 1 Y pulls low if ALL inputs are 1 Y pulls high if ANY input is 0
YA
Y
B
CC
CMOS VLSI Design0: Introduction Slide 22
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CMOS FabricationCMOS Fabrication CMOS transistors are fabricated on silicon wafer CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press O h t diff t t i l d it d On each step, different materials are deposited or
etched Easiest to understand by viewing both top and Easiest to understand by viewing both top and
cross-section of wafer in a simplified manufacturing processp
CMOS VLSI Design0: Introduction Slide 23
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Inverter Cross sectionInverter Cross-section Typically use p type substrate for nMOS transistors Typically use p-type substrate for nMOS transistors Requires n-well for body of pMOS transistors
S 14 i h iA
YGND VDD SiO2
See pp. 14 inverter schematic
n+ p+
ll
n+ p+
n+ diffusion
p+ diffusion
polysiliconp substrate
n well polysilicon
metal1
nMOS transistor pMOS transistor
CMOS VLSI Design0: Introduction Slide 24
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Well and Substrate TapsWell and Substrate Taps Substrate must be tied to GND and n well to V Substrate must be tied to GND and n-well to VDD
Metal to lightly-doped semiconductor forms poor connection called Shottky Diodeconnection called Shottky Diode
Use heavily doped well and substrate contacts / taps (Ohmic Contact) A(Ohmic Contact) A
YGND VDD
n+ p+
n well
n+p+ n+ p+
p substraten well
substrate tap well tap
CMOS VLSI Design0: Introduction Slide 25
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Inverter Mask SetInverter Mask Set Transistors and wires are defined by masks Transistors and wires are defined by masks Cross-section taken along dashed line
A
GND V
Y
GND VDD
substrate tap well tapnMOS transistor pMOS transistor
CMOS VLSI Design0: Introduction Slide 26
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Detailed Mask ViewsDetailed Mask Views Six masks Six masks
– n-wellP l ili
n well
– Polysilicon– n+ diffusion
diff i
Polysilicon
– p+ diffusion– Contact
M l
n+ Diffusion
p+ Diffusion
– MetalContact
Metal
CMOS VLSI Design0: Introduction Slide 27
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Fabrication StepsFabrication Steps Start with blank wafer Start with blank wafer Build inverter from the bottom up Fi t t ill b t f th ll First step will be to form the n-well
– Cover wafer with protective layer of SiO2 (oxide)R l h ll h ld b b ilt– Remove layer where n-well should be built
– Implant or diffuse n dopants into exposed waferS i ff SiO– Strip off SiO2
p substrate
CMOS VLSI Design0: Introduction Slide 28
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OxidationOxidation Grow SiO on top of Si wafer Grow SiO2 on top of Si wafer
– 900 – 1200 C with H2O or O2 in oxidation furnace
SiO
p substrate
SiO2
CMOS VLSI Design0: Introduction Slide 29
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PhotoresistPhotoresist Spin on photoresist Spin on photoresist
– Photoresist is a light-sensitive organic polymerS ft h d t li ht– Softens where exposed to light
SiO2
Photoresist
p substrate
2
CMOS VLSI Design0: Introduction Slide 30
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LithographyLithography Expose photoresist through n well mask Expose photoresist through n-well mask Strip off exposed photoresist
SiO2
Photoresist
p substrate
2
CMOS VLSI Design0: Introduction Slide 31
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EtchEtch Etch oxide with hydrofluoric acid (HF) Etch oxide with hydrofluoric acid (HF)
– Seeps (groundwater, has oozed from the ground to the surface ) through skin and eats bone; nasty stuff!!!eats bone; nasty stuff!!!
Only attacks oxide where resist has been exposed
SiO2
Photoresist
p substrate
2
CMOS VLSI Design0: Introduction Slide 32
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Strip PhotoresistStrip Photoresist Strip off remaining photoresist Strip off remaining photoresist
– Use mixture of acids called piranah etch N i t d ’t lt i t t Necessary so resist doesn’t melt in next step
SiO2
p substrate
2
CMOS VLSI Design0: Introduction Slide 33
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n welln-well n well is formed with diffusion or ion implantation n-well is formed with diffusion or ion implantation Diffusion
Pl f i f ith i– Place wafer in furnace with arsenic gas– Heat until As atoms diffuse into exposed Si
I I l t ti Ion Implanatation– Blast wafer with beam of As ions
I bl k d b SiO l d Si– Ions blocked by SiO2, only enter exposed Si
SiO2
n well
2
CMOS VLSI Design0: Introduction Slide 34
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Strip OxideStrip Oxide Strip off the remaining oxide using HF Strip off the remaining oxide using HF Back to bare wafer with n-well S b t t i l i il i f t Subsequent steps involve similar series of steps
p substraten well
CMOS VLSI Design0: Introduction Slide 35
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PolysiliconPolysilicon Deposit very thin layer of gate oxide Deposit very thin layer of gate oxide
– < 20 Å (6-7 atomic layers) Ch i l V D iti (CVD) f ili l Chemical Vapor Deposition (CVD) of silicon layer
– Place wafer in furnace with Silane gas (SiH4)F ll t l ll d l ili– Forms many small crystals called polysilicon
– Heavily doped to be good conductor
Thin gate oxidePolysiliconThin gate oxide
p substraten well
CMOS VLSI Design0: Introduction Slide 36
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Polysilicon PatterningPolysilicon Patterning Use same lithography process to pattern polysilicon Use same lithography process to pattern polysilicon
Polysilicon
Thin gate oxidePolysilicon
p substrate
Thin gate oxide
n well
CMOS VLSI Design0: Introduction Slide 37
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Self Aligned ProcessSelf-Aligned Process Use oxide and masking to expose where n+ dopants Use oxide and masking to expose where n+ dopants
should be diffused or implanted N diffusion forms nMOS source drain and n well N-diffusion forms nMOS source, drain, and n-well
contact
p substraten well
CMOS VLSI Design0: Introduction Slide 38
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N diffusionN-diffusion Pattern oxide and form n+ regions Pattern oxide and form n+ regions Self-aligned process where gate blocks diffusion P l ili i b tt th t l f lf li d t Polysilicon is better than metal for self-aligned gates
because it doesn’t melt during later processing
n+ Diffusion
p substraten well
CMOS VLSI Design0: Introduction Slide 39
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N diffusion contN-diffusion cont. Historically dopants were diffused Historically dopants were diffused Usually ion implantation today B t i till ll d diff i But regions are still called diffusion
n wellp substrate
n+n+ n+
CMOS VLSI Design0: Introduction Slide 40
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N diffusion contN-diffusion cont. Strip off oxide to complete patterning step Strip off oxide to complete patterning step
n wellp substrate
n+n+ n+
CMOS VLSI Design0: Introduction Slide 41
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P DiffusionP-Diffusion Similar set of steps form p+ diffusion regions for Similar set of steps form p+ diffusion regions for
pMOS source and drain and substrate contact
p+ Diffusion
p substraten well
n+n+ n+p+p+p+
CMOS VLSI Design0: Introduction Slide 42
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ContactsContacts Now we need to wire together the devices Now we need to wire together the devices Cover chip with thick field oxide Et h id h t t t d d Etch oxide where contact cuts are needed
Contact
Thick field oxide
p substraten well
n+n+ n+p+p+p+
CMOS VLSI Design0: Introduction Slide 43
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MetalizationMetalization Sputter on aluminum over whole wafer Sputter on aluminum over whole wafer Pattern to remove excess metal, leaving wires
M etal
Metal
Thick field oxide
p substraten well
n+n+ n+p+p+p+
CMOS VLSI Design0: Introduction Slide 44
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LayoutLayout Chips are specified with set of masks Chips are specified with set of masks Minimum dimensions of masks determine transistor
size (and hence speed cost and power)size (and hence speed, cost, and power) Feature size f = distance between source and drain
Set by minimum width of polysilicon– Set by minimum width of polysilicon Feature size improves 30% every 3 years or so Normalize for feature size when describing design Normalize for feature size when describing design
rules Express rules in terms of = f/2 Express rules in terms of = f/2
– E.g. = 0.3 m in 0.6 m process
CMOS VLSI Design0: Introduction Slide 45
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Simplified Design RulesSimplified Design Rules Conservative rules to get you started Conservative rules to get you started
CMOS VLSI Design0: Introduction Slide 46
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Inverter LayoutInverter Layout Transistor dimensions specified as Width / Length Transistor dimensions specified as Width / Length
– Minimum size is 4 / 2sometimes called 1 unitI f 0 6 thi i 1 2 id 0 6– In f = 0.6 m process, this is 1.2 m wide, 0.6 m long
CMOS VLSI Design0: Introduction Slide 47
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SummarySummary MOS Transistors are stack of gate oxide silicon MOS Transistors are stack of gate, oxide, silicon Can be viewed as electrically controlled switches B ild l i t t f it h Build logic gates out of switches Draw masks to specify layout of transistors
Now you know everything necessary to start designing schematics and layout for a simple chip!designing schematics and layout for a simple chip!
CMOS VLSI Design0: Introduction Slide 48