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1ECE 368: CAD-Based Logic DesignLecture Notes # 5Sequential Circuit (Finite-State Machine) DesignSHANTANU DUTTDepartment of ECEUniversity of Illinois, ChicagoPhone: (312) 355-1314: e-mail: dutt@ece.uic.eduURL: http://www.ece.uic.edu/~dutt2Finite State Machine (FSM) Design FSMs are different from counters in the sense that they have external I/Ps, and state transitions are dependent on these I/Ps and the current state. Example : Problem StatementThere is a bit-serial I/P line. Design an FSM that outputs a 0if an even # of 1s have been received on the I/P line and the outputs a 1 otherwise.Note : If a synchronous sequential circuit is being designed, the counting of the # of 1s occur every clock cycle.FSMxO/p yCLKCLKx# of1seven(0)odd(1)even(2)odd(3)odd(3)Tlogic + TsetupSamplinginstancesApproach to determining states of an FSM: First determine the min # of useful information classes about past i/ps required to solve the problem (requires analytical thinking about the problem) Each info class a potential state From this 1st cut at possible states, determine if there are well-defined transitions from each state for all possible i/p values. If so then these states can be the final states; otherwise some states may need to be refined into multiple states to achieve well-defined transitions (see FSM word prob. 1). In this problem, only 2 classes of information are reqd: whether an even # of 1s have been received so far, or an odd # of 1s have been received so far & there are well-defined transitions between them. Thus these 2 classes become 2 states.Solution 1: (Mealy)0/0EvenOdd1/11/00/1ResetOutputInputTransition ArcO/P is dependenton current state andinput in MealyMealy Machine: Output is associated with the state transition, and appears before the state transition is completed (by the next clock pulse).0Even110Reset[0]Odd [1]OutputInputOutput is dependent only on current stateSolution 2: (Moore)Moore Machine: Output is associatedwith the state and hence appearsafter the state transition take place.4Determining a Reset State: A reset state is a state the the FSM (seq ckt) should be in when it is just powered on. In other words, a reset state is a state the FSM should be in, when it has recvd no i/ps Based on the above definition, decide if any of the states determined so far can be a reset state. E.g., in the parity detector problem, the even state qualifies to be the reset state, as in the reset state no i/ps recvd zero 1s recvd even # of 1s recvd it can be the even state If not, then need to have a separate reset state, and have the correct transitions from this state to the other states (depending on the problem solved by the FSM).Solution 1: (Mealy)0/0EvenOdd1/11/00/1ResetOutputInputTransition ArcO/P is dependenton current state andinput in MealyMealy Machine: Output is associatedwith the state transition, and appearsbefore the state transition is completed(by the next clock pulse).0Even110Reset[0]Odd [1]OutputInputOutput is dependent only on current stateSolution 2: (Moore)Moore Machine: Output is associatedwith the state and hence appearsafter the state transition take place.5FFsExternal I/PsExternal O/Psm1m2nnComb.LogicCLKFFsnCLKnOutputLogicm2Next StateComb.Logicm1ExternalI/PsExternal OutputsMealy Machine ModelMoore Machine Modeleven oddTime t : Even I/P = propagation delay of logic of Mealy M/Ctt+t+TCLKt+TCLK+2Evenx=1O/P=0O/P=1(Mealy)OddO/P=1(Moore)2 = propagation delay of O/Plogic unit of Moore M/C6State Transition Table(Even-Parity Checker)Even State: 0 ; Odd State: 1; State Variable AA x A+ y1 y2 DA TA0 0 0 0 0 0 00 1 1 0 1 1 11 0 1 1 1 1 01 1 0 1 0 0 1PresentStateInputNextStateMooreO/PMealyO/PD-FFExcit.T-FFExcit.Input variablesto comb. logicQFFN.S. & O/PLogicCLKxy2ADAOrFFsy1N.S.LogicO/PLogicDAAQxDA= Ax (same for Mooreand Mealy); TA= x (same for Mooreand Mealy);y1 = A for Moorey2 = Ax for MealyOutput functions7State=0EvenState=1Odd1/11/00/1Reset0State=0Even110Reset[0]State=1Odd [1]xFFN.S.LogicCLKQQDD-MealyMooreAssume single bit state information stored in a D-FFCLKxDQ(state)y2(Mealy O/P)y1 Moore O/P)State Transition is occurringState Transition is occurringS.T. is complete.S.T. is complete.oddoddevenevenoddeven0/08Moore M/C ImplementationD Q QRCLKy2x=1A0a) D-FFT Q QRA y2xCLKb) T-FFMoore O/P is synchronized with clock.Mealy M/C ImplementationD Q QR

CLKy1x=1A01T Q QRxCLKy1a) D-FFb) T-FFMealy O/P is not synchronized with clock.ResetResetResetResetDA= Ax ; TA= x; y1 = A for Moore; y2 = Ax for MealyNote: Here Moore and Mealy state transitionfunction is the same. Will not always be the case.9Difference Between Mealy and Moore Machine Mealy Moore (1) O/Ps depend on the present O/Ps depend only on the state and present I/Ps present state(2) The O/P changes asyn Since the O/Ps change -chronously with the when the state changes, enabling clock edge and the state change is synchronous with the enabling clock edge, O/Ps change synchronously with this clock edge(3) A counter is not a Mealy A counter is a Moore machine machine(4) A Mealy machine will have the same # or fewer states than a Moore machine 10Behavioral FSM Descriptions in VHDL 1st Cutentity fsm1_1 is port (x, reset:in bit; y: out bit:=`0)end entity fsm1_1

architecture behav of fsm1_1 istype states is (even, odd);beginstate_mc: process (x, reset) isvariable curr_state, next_state: states := even;-- initial state is reset statebeginif reset = 1 then curr_state := even; y y y