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ECE2030

Introduction to Computer Engineering

Lecture 4: CMOS Network

Prof. Hsien-Hsin Sean Lee

School of Electrical and Computer Engineering

Georgia Tech

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CMOS Inverter Connect the following terminals of a PMOS and an

NMOS Gates

Drains

Vin Vout

Vdd

Gnd

Vout

Vin

Vin

Vin = HIGHVout = LOW (Gnd)

ON

OFF

Vdd

Gnd

Vout

Vin

Vin

Vin = LOWVout = HIGH (Vdd)

ON

OFF

Vdd

PMOS

Ground

NMOS

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CMOS Voltage Transfer Characteristics

Vdd

Gnd

Vin Vout

PMOS

NMOS

OFF: V_GateToSource < V_Threshold

LINEAR(or OHMIC): 0< V_DrainToSource < V_GateToSource - V_Threshold

SATURATION: 0 < V_GateToSource - V_Threshold < V_DrainToSource

Note that in the CMOS Inverter V_GateToSource = V_in

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Pull-Up and Pull-Down Network

CMOS network consists of a Pull-UP Network (PUN) and a Pull-Down Network (PDN)

PUN consists of a set of PMOS

transistors PDN consists of a set of NMOS

transistors

PUN and PDN implementations

are complimentary to each other PMOS NOMS

Series topologyParallel topology

.

I0I1

In-1

OUPTUT

Vdd

PUN

Gnd

PDN

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PUN/PDN of a CMOS Inverter

A B

0 1

1 Z

A B

0 Z

1 0

A B

0 1

1 0

Pull-UpNetwork

Pull-DownNetwork

CombinedCMOSNetwork

Vdd

A

Gnd

B

CMOS Inverter

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Gate Symbol of a CMOS Inverter

Vdd

A

Gnd

B

CMOS Inverter

A B

B =

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PUN/PDN of a NAND GateA B C

0 0 1

0 1 1

1 0 1

1 1 Z

A B C0 0 Z

0 1 Z

1 0 Z

1 1 0

Pull-UpNetwork

Pull-DownNetwork

Vdd

A

B

A B

C

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PUN/PDN of a NAND GateA B C

0 0 1

0 1 1

1 0 1

1 1 Z

A B C0 0 Z

0 1 Z

1 0 Z

1 1 0

A B C

0 0 1

0 1 1

1 0 1

1 1 0

Pull-UpNetwork

Pull-DownNetwork

CombinedCMOSNetwork

Vdd

A

B

A B

C

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NAND Gate Symbol

A B C

0 0 1

0 1 1

1 0 1

1 1 0

Vdd

A

B

A B

C

A

B

C

Truth Table

BAC

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PUN/PDN of a NOR GateA B C

0 0 1

0 1 Z

1 0 Z

1 1 Z

A B C0 0 Z

0 1 0

1 0 0

1 1 0

Pull-UpNetwork

Pull-DownNetwork

Vdd

A

C

B

A B

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PUN/PDN of a NOR GateA B C

0 0 1

0 1 Z

1 0 Z

1 1 Z

A B C0 0 Z

0 1 0

1 0 0

1 1 0

A B C

0 0 1

0 1 0

1 0 0

1 1 0

Pull-UpNetwork

Pull-DownNetwork

CombinedCMOSNetwork

A

C

B

A B

Vdd

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NOR Gate Symbol

A B C

0 0 1

0 1 0

1 0 0

1 1 0

A

B

C

Truth Table

A

C

B

A B

BAC

Vdd

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How about an AND gate

Vdd

A

B

AVdd

Gnd

C

NAND

Inverter

B

C = A B

A

B

C

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An OR Gate

A

B

A B

Vdd

Vdd

Gnd

C

Inverter

NOR

A

B

C

BAC

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Whats the Function of the following CMOS Network?

A B C

0 0 Z

0 1 1

1 0 1

1 1 Z

A B C0 0 0

0 1 Z

1 0 Z

1 1 0

A B C

0 0 0

0 1 1

1 0 1

1 1 0

Pull-UpNetwork

Pull-DownNetwork

CombinedCMOSNetwork

Function =XOR

Vdd

A

B

A

A

A

B

B

B

C

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Yet Another XOR CMOS Network

Vdd

A

B

A A

A

B

BB

C

A B C

0 0 Z

0 1 1

1 0 1

1 1 Z

A B C0 0 0

0 1 Z

1 0 Z

1 1 0

A B C

0 0 0

0 1 1

1 0 1

1 1 0

Pull-UpNetwork

Pull-DownNetwork

CombinedCMOSNetwork

Function =XOR

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Exclusive-OR (XOR) Gate

Vdd

A

B

A A

A

B

BB

C

A B C

0 0 0

0 1 1

1 0 11 1 0

A

B

C

Truth Table

BABABAC

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How about XNOR Gate

A B C

0 0 1

0 1 0

1 0 0

1 1 1

A

B

C

Truth Table

BABABAC

How do we draw the

corresponding CMOS networkgiven a Boolean equation?

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How about XNOR Gate

A B C

0 0 1

0 1 0

1 0 0

1 1 1

A

B

C

Truth Table

BABAC

Vdd

A

B

A A

A

B

BB

C

Vdd

XOR

Inverter

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A Systematic Method (I)Start from Pull-Up Network

Each variable in the given Boolean eqncorresponds to a PMOS transistor in PUN and anNMOS transistor in PDN

Draw PUN using PMOS based on the Boolean eqn AND operation drawn in series

OR operation drawn inparallel

Invert each variable of the Boolean eqn as the gateinput for each PMOS in the PUN

Draw PDN using NMOS in complementary form

Parallel (PUN) to series (PDN) Series (PUN) to parallel (PDN)

Label with the same inputs of PUN Label the output

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A Systematic Method (II)Start from Pull-Down Network

Each variable in the given Boolean eqn corresponds to aPMOS transistor in PUN and an NMOS transistor in PDN

Invert the Boolean eqn With the Right-Hand Side of the newly inverted equation,

Draw PDN using NMOS

AND operation drawn in series OR operation drawn inparallel

Label each variable of the Boolean eqn as the gate input foreach NMOS in the PDN

Draw PUN using PMOS in complementary form Parallel (PUN) to series (PDN) Series (PUN) to parallel (PDN)

Label with the same inputs of PUN

Label the output

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Systematic Approaches

Note that both methods lead to exactly the sameimplementation of a CMOS network

The reason to invert Output equation in (II) isbecause Output (F) is conducting toground, i.e. 0, when there

is a path formed by input NMOS transistors Inversion will force the desired result from the equation

Example F=C + B: When (A=0 and C=1) or B=1, F=1.

However, in the PDN (NMOS) of a CMOS network,

F=0, i.e. an inverse result. Revisit how a NAND CMOS network is implemented

Inverting each PMOS input in (I) follow the samereasoning

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Example 1 (Method I)

BCAF

In series

In parallel

Vdd

(1) Draw the Pull-Up Network

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BCAF

In series

In parallelVdd

(2) Assign the complemented input

A

C

B

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BCAF

In series

In parallelVdd

(3) Draw the Pull-Down Network inthe complementary form

A

C

B

A C

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BCAF

In series

In parallelVdd

(3) Draw the Pull-Down Network inthe complementary form

A

C

B

A C

B

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BCAF

In series

In parallelVdd

Label the output F

A

C

B

A C

B

F

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BCAF

In series

In parallelVdd

A

C

B

A C

B

FA B C F

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 1

Truth Table

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Drawing the Schematic using Method II

BCAF

BC)A(F

BCAF

BCAF

Vdd

A

C

B

A C

B

F

This is exactly the sameCMOS network with theschematic by Method I

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An Alternative for XNOR Gate (Method

I)

A B C

0 0 1

0 1 0

1 0 0

1 1 1

A

B

C

Truth Table

BABAC

Vdd

A

B

A

B

A

A B

B

C

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Example 3

)C(ABDAF

Start from the innermost term

A

B D

AC

A D

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Example 3

)C(ABDAF


A

B D

AC

A D

A

C

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Example 3

)C(ABDAF


A

B D

AC

A D

A

C

B

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Example 3

)C(ABDAF


A

B D

AC

A D

A

C

B

Vdd

F

Pull-UpNetwork

Pull-DownNetwork

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Example 4

))C(ABDA()D(EF


A

B D

AC

A D

A

C

B

Vdd

F

E D

E

D

Pull-DownNetwork

Pull-UpNetwork

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Another Example

BCAF How ??

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