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ECEU530
ECE U530Digital Hardware Synthesis
• Lecture 8:• Homework 2 -- due Thursday October 5 by 2pm• Projects• Homework 3• VHDL arithmetic
• Reading: Sections 4.1, 4.2, 8.4, 8.5• Email me your project idea by Tuesday October 10!• Homework 3 due October 18• Project Proposals due October 18
ECE U530 F06lect08.ppt
Prof. Miriam [email protected] 4, 2006
ECE U530 F’062lect08.ppt
Homework 2
• Now due on Thursday October 5th by 4pm• Describe a seven segment decoder
• Implementing the equations using std_logic• Implementing the truth table using std_logic_vector• Submit simulation results for both• No need to do a structural description!• For std_logic_vector :
Create a four bit std_logic_vector for the inputs and a seven bit std_logic_vector for the outputs. These should be internal signals. Assign the inputs (A,B,C,D) to the input vector. In a case statement, choose a combination of inputs and for that combination assign outputs. To get the outputs in the entity youwill need to select each of the output bits and assign them to the approprate signal in the entity.
ECE U530 F’063lect08.ppt
Homework 2: Waveforms
• Submit a waveform for each• Waveforms should be complete:
• Show outputs for all combinations of 4 inputs: A, B, C and D
• Easier to do all combinations in a testbench• An example testbench was posted with Homework 1
solutions
• Submit waveform from Modelsim• Save as a bitmap file• Lab 2, page 5 explains how to save the waveform
ECE U530 F’064lect08.ppt
Debugging VHDL
• VHDL Errors can be cryptic!To debug: • synthesize your VHDL in Xilinx. Click on the Errors
tab at the bottom to see the error messages
• Click on the VHDL source code in Xilinx, then click on “launch Modelsim simulator”
• Sometimes Modelsim gives you better error messages, sometimes Xilinx does. Try looking in both places.
ECEU530
ECE U530 F’065lect08.ppt
Testbench from HW1ENTITY testbench IS END testbench;ARCHITECTURE behavior OF testbench IS signal input: std_logic_vector(7 downto 0);signal output : std_logic;COMPONENT aoi
PORT(a : IN std_logic; b : IN std_logic; c : IN std_logic;d : IN std_logic; e : IN std_logic; f : IN std_logic;g : IN std_logic; h : IN std_logic; y : OUT std_logic );
END COMPONENT;BEGINuut: aoi PORT MAP(a => input(0), b => input(1), c => input(2),
d => input(3), e => input(4), f => input(5), g => input(6),h => input(7), y => output);
tb : PROCESSvariable i : integer :=0;BEGINfor i in 0 to 127 loopinput <= conv_std_logic_vector(i,8);
wait for 10 ns; -- will wait foreverend loop;
END PROCESS;END;
ECE U530 F’066lect08.ppt
Projects• Individual project implementing a design in VHDL
• Team projects if the parts are well defined• Complexity about the same as the calculator in
ECEU323• Some project ideas:
• A simple computer• An elevator controller• A robot controller
• Deadlines:• October 9: Send me your idea• October 18: Write a short project proposal• Nov 8: Progress Report • Nov 20: Preliminary Project Report • Dec 13: Final Project Report Due
ECE U530 F’067lect08.ppt
Project Proposal (Handout 4)
• Description of what you will describe in VHDL• A detailed plan of how you will implement your
project• Several different implementations, each adding more
functionality• Example: Elevator controller
–1 elevator, 2 floors, only up and down buttons at each floor–add buttons inside the elevator–add open/close door functionality–add more floors, more elevators ...
• Specification of all inputs and outputs you anticipate• Entity in VHDL
• Schedule for the rest of the semester
ECE U530 F’068lect08.ppt
Homework 3 due Wed, October 18
• Write a VHDL description of the ALU from ECEU323 lab 3
• Your solution should include:• An entity that describes the interface of the ALU• Some ports are std_logic and some ports are std_logic_vector
• An architectural body for the ALU• You may use any technique you wish
• What is hard?• Getting the arithmetic right
• Carry, borrow and overflow
• Writing the testbench • Homework 4 will ask you to write a testbench for your ALU
ECEU530
ECE U530 F’069lect08.ppt
Package std_logic_1164library IEEE;
use IEEE.std_logic_1164.all;
• Defines types:std_ulogic
std_logic
std_ulogic_vector
std_logic_vector
• Defines logical, relation operations on these types
• Does NOT define arithmetic operations on these types
ECE U530 F’0610lect08.ppt
Types signed and unsigned
type unsigned is array (natural <>) of std_logic;type signed is array (natural <>) of std_logic;
• Defined in packages:• package std_logic_arith (signed)• package std_logic_unsigned (unsigned)
• These packages define arithmetic operations on type signed and unsigned
• Arithmetic is either unsigned or signed two’s complement
ECE U530 F’0611lect08.ppt
Numeric Packages
• If you want arithmetic operations, your code should start with:
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
orlibrary IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
The second option is what the Xilinx tools use by default
ECE U530 F’0612lect08.ppt
Representing Signed Values
Value Sign Magnitude one’s comp two’s comp+7 0111 0111 0111+6 0110 0110 0110+5 0101 0101 0101+4 0100 0100 0100+3 0011 0011 0011+2 0010 0010 0010+1 0001 0001 0001+0 0000 0000 0000-0 1000 1111 ------1 1001 1110 1111-2 1010 1101 1110-3 1011 1100 1101-4 1100 1011 1100-5 1101 1010 1011-6 1110 1001 1010-7 1111 1000 1001-8 ----- ---- 1000
ECEU530
ECE U530 F’0613lect08.ppt
Types Signed and Unsigned
Data Type Valueunsigned 0 to 2N - 1
signed -2(N-1) to 2(N-1) - 1 --signed two’s complement
signal A_unsigned: unsigned(3 downto 0);
signal B_signed: signed(3 downto 0);
signal C_slv: std_logic_vector(3 downto 0);
A_unsigned <= “1111”; -- value is ______
B_signed <= “1111”; -- value is ______
C_slv <= “1111”; -- value is _______
ECE U530 F’0614lect08.ppt
Types Signed and Unsigned
• definitions of types Unsigned and Signed are identical to definition of std_logic_vector:
type UNSIGNED is array (natural range <>) of std_logic;
type SIGNED is array (natural range <>) of std_logic;
• How are these types distinguished from one another?• How do these generate signed and unsigned
arithmetic?
ECE U530 F’0615lect08.ppt
Signed and Unsigned Arithmetic
• For each operator, a unique function is called:
function “+” (L,R: signed) return signed;
function “+” (L,R: unsigned) return unsigned;
• This is called operator overloading• A different “+” function is called depending on the types of
the operands
• VHDL uses operator overloading often• relational operators• logical operators• arithmetic operators
ECE U530 F’0616lect08.ppt
Signed and Unsigned Arithmetic
UNSIGNED’(“1000”) -- has value ______
SIGNED’(“1001”) -- has value ______
SIGNED’(“0101”) -- has value ______
SIGNED’(“1011”) -- has value ______
• What is difference?• how bits are interpretted• how +, - are defined• how relational operations are defined:• is “1011” < “1010” ?
ECEU530
ECE U530 F’0617lect08.ppt
More Operators
• Arithmetic operators (defined on types integer, signed, unsigned)• +, -, &• Unary (sign) operators: +, - on integers• Multiplying operators: * / mod rem• Other operators:
• ** raise to a power: must be 2**n to synthesize (for most CAD tools)
• abs defined on signed types only• not
• Note: mod and rem return the same result, but may differ in their sign depending on the sign of the divisor
ECE U530 F’0618lect08.ppt
Arithmetic Operators
• Logic operators are defined as bitwise on std_logic_vectors:signal A,D: std_logic_vector(3 downto 0);
signal B,C: std_logic_vector(1 downto 0);
signal check: Boolean;
D <= (not B) & (not C);
check <= ( D = (not (B & C)));
• Can’t add, subtract std_logic_vectors• Can add, subtract signed, unsigned
• Unless you use package std_logic_unsigned–Allows you to add, subtract slv using unsigned arithmetic
• Not recommended
ECE U530 F’0619lect08.ppt
Arithmetic Operators
• Convert std_logic_vectors to signed or unsigned first
signal A: std_logic_vector(3 downto 0);
signal A_unsigned: unsigned(3 downto 0);
A_unsigned <= unsigned’(A);
A <= std_logic_vector’(A_unsigned);
• unsigned’() and std_logic_vector’() are type conversion functions
• they are overloaded functions• std_logic_vector’() is defined differently for
parameters of type signed and unsigned
ECE U530 F’0620lect08.ppt
Types and Subtypes
• Users can specify new types and new subtypes• A subtype is a constrained version of an existing type
subtype small_int is integer range -128 to 127;
variable deviation: small_int;
variable adjustment: integer;
deviation := deviation + adjustment;
• This is legal VHDL. Can mix types small_int and integer. Result must be in the range -128 to 127.
• Can use all the operations of integer with a subtype based on integer
ECEU530
ECE U530 F’0621lect08.ppt
Types vs. Subtypes
• A new type is different from its base type• A subtype “inherits” all the functions of its base type
(including defined operators!)subtype four_bit is std_logic_vector(3 downto 0);
type four_array is array(3 downto 0) of std_logic;
• Cannot write:type four_array2 is std_logic_vector(3 downto 0);
• can add signals of type four_bit• cannot add signals of type four_array2:
• have to specify “+” function first
• Use subtypes for restricted data ranges• Use types for new, enumerated types
ECE U530 F’0622lect08.ppt
Numeric Packages• Your code should start with (default in Xilinx):
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
• std_logic_1164 defines std_logic, std_logic_vector• std_logic_unsigned defines unsigned arithmetic on
standard logic vector • std_logic_arith defines signed two’s complement
data types and arithmetic and unsigned data types and arithmetic
ECE U530 F’0623lect08.ppt
Signed and Unsigned Arithmetictype unsigned is array (natural <>) of std_logic;
type signed is array (natural <>) of std_logic;
type std_logic_vector is array (natural <>) of std_logic;
• How are these types distinguished from one another?• How do they generate unsigned and signed
arithmetic?
function ”+” (L, R: signed) return signed;
function “+” (L, R: unsigned) return unsigned;
Which function is used depends on types:A + B
ECE U530 F’0624lect08.ppt
Operator Overloading
Operator Left Right ResultLogic TypeA TypeA TypeA
Numeric Array Array ArrayArray Integer ArrayInteger Array Array
Array is unsigned, signed or std_logic_vectorTypeA is Boolean, std_logic, bit, bit_vector,
std_logic_vectorArray and TypeA types used in a single expression
must be the same
ECEU530
ECE U530 F’0625lect08.ppt
Overloading Examplessignal A_uv, B_uv, C_uv, D_uv: unsigned(7 downto 0);
signal R_sv, S_sv, T_sv, U_sv: signed (7 downto 0);
signal J_slv, K_slv, L_slv: std_logic_vector (7 downto 0);
signal Y_sv: signed (8 downto 0);
--Permitted
A_uv <= B_uv + C_uv; -- Unsigned + Unsigned = Unsigned
D_uv <= B_uv + 1; -- Unsigned + Integer = Unsigned
R_sv <= S_sv + T_sv; -- signed + signed = signed
U_sv <= S_sv + 1; -- signed + Integer = signed
J_slv <= K_slv + L_slv; -- if using std_logic_unsigned
--Illegal
Y_sv <= A_uv - B_uv; -- why ? what if want -- signed result ?
ECE U530 F’0626lect08.ppt
Strong Typing
• Size and type of left hand side of signal assignment must match size and type of right hand side
• Each operation returns a result that has a specific size based on rules of the operation
• A’length is length of array A• ’length is a VHDL attribute: Not synthesizable
• Idea behind strong typing=> catch errors early
ECE U530 F’0627lect08.ppt
Strong Typing Examples
Operation Size of Y = Size of ExpressionY <=“10101010”; number of digits in literal
Y <= X”AA”; 4 * (number of digits)Y <= A and B; A’length = B’lengthW <= A > B; Boolean
Y <= A + B; Maximum(A’Length, B’Length)Y <= A + 10; A’Length
V <= A * B; A’Length + B’Length
ECE U530 F’0628lect08.ppt
Types and Additionsignal A8, B8, Result8 : unsigned(7 downto 0);
signal Result9 : unsigned(8 downto 0);
signal Result7 : unsigned(6 downto 0);
...
-- Simple addition, no carry out
Result8 <= A8 + B8;
-- For smaller result choose part of inputs
Result7 <= A8(6 downto 0) + B8(6 downto 0);
ECEU530
ECE U530 F’0629lect08.ppt
Carry out
• Suppose want carry out from result?• Need to make result one bit longer than inputs• but type of RHS and LHS must match.• Extend RHS signals by one bit using concatenation:•signal A8, B8, Result8 : unsigned(7 downto 0);
signal Result9 : unsigned(8 downto 0);
-- Carry out in result
Result9 <= (‘0’ & A8) + (‘0’ & B8);
• What about signed values?• Will this work ?
ECE U530 F’0630lect08.ppt
Type Conversion Functions
• VHDL is dependent on overloading operators and on type conversions
• Conversion functions needed:• Signed and unsigned <=> std_logic_vector• signed and unsigned <=> integer• std_logic_vector <=> integer
• These conversion functions are built in to the arithmetic packages
• You need to explicitly use them • Types convert automatically if one is the subtype of
another
ECE U530 F’0631lect08.ppt
Subtracting unsigned vectors
• What if I want to subtract:unsigned – unsigned and get a signed result?
signal X_uv, Y_uv: unsigned ( 6 downto 0);
signal Z_sv: signed (7 downto 0);
Z_sv <= signed’(’0’ & X_uv) – signed’(’0’ & Y_uv);
ECE U530 F’0632lect08.ppt
Functions in std_logic_arithfunction ”+” (L, R: signed) return signed;
function ”+” (L:signed, R: unsigned) return signed;
function “+” (L:unsigned, R: signed) return signed;
• What if I write:
Z_sv <= A_sv + “1010”;
is “1010”
unsigned? value ______
signed? value ______
ECEU530
ECE U530 F’0633lect08.ppt
Std_logic_arith: literalsZ_sv <= A_sv + signed’(“1010”);
• Note you need the ’ for the type conversion function• alternatively, use an integer
Z_sv <= A_sv – 6;
ECE U530 F’0634lect08.ppt
Addition Operators• Arithmetic with unsigned numbers
Add_uv <= A_uv + B_uv;
Sub_uv <= C_uv – D_uv;
• Size of result =• size of largest RHS operand• Size of ADD = maximum (A, B)• Shorter array is extended
• Unsigned with IntegersInc_uv <= Base_uv + 1;
Y_uv <= A_uv + 45;
• Integers must fit into an array the same size as the result
• Extra MSB digits are lost
ECE U530 F’0635lect08.ppt
Use integers with care
• Synthesis tool creates 32 bit wide registers, adders, etc for unconstrained integers:
signal Y_int, A_int, B_int: integer;
Y <= A_int + B_int;
• Better:signal A_int, B_int: integer range -8 to 7;
signal Y_int: integer range -16 to 15;
Y_int <= A_int + B_int;
• Recommendation: Use integers only as constants and literals:Y_uv <= A_uv + 17;
ECE U530 F’0636lect08.ppt
Carry Out and Overflow
• If you add two unsigned numbers, you may get a carry out from the MSB• Carry out means that you have overflowed the range of an
unsigned value• Two inputs, A, B are 4 bits, Result is too big for 4 bits
• If you add two signed numbers you may get an overflow from the MSB• Overflow means that you have overflowed the range of a
signed value• Overflow is different from Carry Out• You can have overflow and no carry out, carry out and no
overflow
ECEU530
ECE U530 F’0637lect08.ppt
Carry out and overflow
• 5, 7, -5, -7 represented as 4 bit, signed values:• 0101 0111, 1011, 10015 + 7
111
0101
0111
1100 overflow, no carry out
5 -7
1
0101
1001
1110 no overflow, no carry out
ECE U530 F’0638lect08.ppt
Carry out and overflow
• 5, 7, -5, -7 represented as 4 bit, signed values:• 0101 0111, 1011, 1001- 5 + 7
111
1011
0111
10010 no overflow, carry out
-5 -7
11
1011
1001
10100 overflow, carry out
ECE U530 F’0639lect08.ppt
Detecting overflow and carry out
• Detecting carry out is easy• convert signals to unsigned• extend inputs by concatenating a zero to the MSB• if MSB of result is 1 then you have carry out
• How do you detect overflow?
ECE U530 F’0640lect08.ppt
Adder with Carry Out
want to calculate:
CarryOut, Result(3:0) <= A(3:0) + B(3:0)
this is NOT legal VHDL
signal A, B, Result : unsigned(3 downto 0);
signal Y5 : unsigned(4 downto 0);
signal Co : std_logic;
-- Carry out and Result in Y5
Y5 <= (‘0’ & A) + (‘0’ & B);
Result <= Y5( 3 downto 0);
Co <= Y5(4);
ECEU530
ECE U530 F’0641lect08.ppt
Adder with Carry In
want to calculate:
??? <= A(3:0) + B(3:0) + CarryIn
signal A, B, Result : unsigned(3 downto 0);
signal Y5 : unsigned(4 downto 0);
signal CarryIn : std_logic;
-- Carry out and Result in Y5
Y5 <= (A & ‘1’) + (B & CarryIn);
Result <= Y5( 4 downto 1);
This gives the correct result
ECE U530 F’0642lect08.ppt
User defined integer types - Examples
type day_of_month is range 0 to 31;type year is range 0 to 2100;
type set_index_range is range 999 downto 100;
constant number_of_bits: integer :=32;type bit_index is range 0 to number_of_bits-1;
Values of bounds can be expressions, butneed to be known when the model is analyzed.
ECE U530 F’0643lect08.ppt
User-defined enumeration types - Examples
type state is (S0, S1);
type alu_function is(nop, add, subtract,multiply, divide);
type octal_digit is (‘0’, ‘1’, ‘2’, ‘3’, ‘4’, ‘5’, ‘6’, ‘7’);
type mixed is (lf, cr, ht, ‘-’, ‘/‘, ‘\’);
Each value in an enumeration type must be eitheran identifier or a character literal
ECE U530 F’0644lect08.ppt
Floating point types• Used to represent real numbers• Numbers are represented using a mantissa and an exponent• Conform to the IEEE standard 754 or 854
Minimum size of representation that must besupported by the implementation of the VHDLstandard:
VHDL-2001: 64-bit representationVHDL-87, VHDL-93: 32-bit representation
ECEU530
ECE U530 F’0645lect08.ppt
Real literals - examples23.1 23.1
46E5 46 ⋅⋅⋅⋅ 105
1E+12 1 ⋅⋅⋅⋅ 1012
1.234E09 1.234 ⋅⋅⋅⋅ 109
34.0e-08 34.0 ⋅⋅⋅⋅ 10-8
2#0.101#E5 0.1012 ⋅⋅⋅⋅ 25 =(2-1+2-3) ⋅⋅⋅⋅ 25
8#0.4#E-6 0.48 ⋅⋅⋅⋅ 8-6 = (4 ⋅⋅⋅⋅ 8-1) ⋅⋅⋅⋅ 8-6
16#0.a5#E-8 0.a516 ⋅⋅⋅⋅ 16-8 =(10⋅⋅⋅⋅16-1+5⋅⋅⋅⋅16-2) ⋅⋅⋅⋅ 16-8
ECE U530 F’0646lect08.ppt
User-defined floating-point types - Examples
type input_level is range -10.0 to +10.0
type probability is range 0.0 to 1.0;
constant max_output: real := 1.0E6;constant min_output: real := 1.0E-6;type output_range is max_output downto min_output;
ECE U530 F’0647lect08.ppt
Physical data typesTypes representing physical quantities, such as time, voltage, capacitance, etc. are referred in VHDL as physical data types.
TIME is the only predefined physical data type.
Value of the physical data type is called a physical literal.
ECE U530 F’0648lect08.ppt
Time values (physical literals) - Examples
7 ns1 minmin
10.65 us10.65 fs
Unit of time(dimension)
SpaceNumeric value
ECEU530
ECE U530 F’0649lect08.ppt
Units of timeUnit DefinitionBase Unitfs femtoseconds (10-15 seconds)Derived Unitsps picoseconds (10-12 seconds)ns nanoseconds (10-9 seconds)us microseconds (10-6 seconds)ms miliseconds (10-3 seconds)sec secondsmin minutes (60 seconds)hr hours (3600 seconds)
ECE U530 F’0650lect08.ppt
User-defined physical types (1)
type resistance is range 0 to 1E9units
ohm;kohm = 1000 ohm;Mohm = 1000 kohm;
end units resistance;
ECE U530 F’0651lect08.ppt
User-defined physical types (2)
type length is range 0 to 1E10units
um; -- primary unit: micronmm = 1000 um; -- secondary metric unitsm = 1000 mm;inch = 25400 um; -- secondary English unitsfoot = 12 inch;
end units length;
ECE U530 F’0652lect08.ppt
Attributes of all scalar typesT’left first (leftmost) value in TT’right last (rightmost) value in TT’low least value in TT’high greatest value in T
type index_range is range 21 downto 11;
index_range’left = 21index_range’right = 11index_range’low = 11index_range’high = 21
ECEU530
ECE U530 F’0653lect08.ppt
Subtype
• Defines a subset of a base type values• A condition that is used to determine which values
are included in the subtype is called a constraint• All operations that are applicable to the base type
also apply to any of its subtypes -- inheritance• Base type and subtype can be mixed in the
operations, but the result must belong to the subtype, otherwise an error is generated.
ECE U530 F’0654lect08.ppt
Predefined subtypes
natural integers ≥ 0
positive integers > 0
ECE U530 F’0655lect08.ppt
User-defined subtypes - Examples
subtype bit_index is integer range 31 downto 0;
subtype input_range is real range 1.0E-9 to 1.0E+12;
ECE U530 F’0656lect08.ppt
One-dimensional arrays – Examples
type controller_state is (initial, idle, active, error);type state_counts_imp is array(controller_state range idle to error) of
natural;type state_counts_exp is array(controller_state range idle to error) of
natural;type state_counts_full is array(controller_state) of natural;
…..variable counters: state_counts_exp;…..counters(active) := 0;…..counters(active) := counters(active) + 1;
ECEU530
ECE U530 F’0657lect08.ppt
One-dimensional array – Initialization (1)
type point is array (1 to 3) of real;
constant origin_point : point := (0.0, 0.0, 0.0);variable view_point : point := (10.0, 20.0, 45.0);
ECE U530 F’0658lect08.ppt
One-dimensional array – Initialization (2)
type coeff_ram_address is integer range 0 to 63;type coef_array is array (coeff_ram_address) ofreal;
variable coeff1: coeff_array := (0 => 1.6, 1=>2.3, 3 to 63 => 0.0);
variable coeff2: coeff_array := (0 => 5E-8, 1=>6E3, others => 0.0);
variable coeff3: coeff_array := (0 | 5 | 6 => 5E-8, 1 | 2=>6E3, others => 0.0);
ECE U530 F’0659lect08.ppt
Multidimensional arrays – Example (1)
type matrix is array (1 to 3, 1 to 3) of real;
variable transform: matrix;…..transform(2, 3) := 4.5E3;
ECE U530 F’0660lect08.ppt
Multidimensional arrays – Example (2)
type symbol is (‘a’, ‘t’, ‘d’, ‘h’, digit, cr, error);type state is range 0 to 6;type transition_matrix is array (state, symbol)of state;
variable transform: transition_matrix;…..transform(5, ‘d’) := 6;
ECEU530
ECE U530 F’0661lect08.ppt
Array Attributes
A’left(N) left bound of index range of dimension N of A
A’right(N) right bound of index range of dimension N of A
A’low(N) lower bound of index range of dimension N of A
A’high(N) upper bound of index range of dimension N of A
A’range(N) index range of dimension N of A
A’reverse_range(N) index range of dimension N of A
A’length(N) length of index range of dimension N of A
A’ascending(N) length of index range of dimension N of A
ECE U530 F’0662lect08.ppt
Array Attributes - Examples
type A is array (1 to 4, 31 downto 0);
A’left(1) = 1
A’right(2) = 0
A’low(1) = 1
A’high(2) = 31
A’range(1) = 1 to 4
A’length(2) = 32
A’ascending(2) = false
ECE U530 F’0663lect08.ppt
Predefined Unconstrained Array Types
Predefined
bit_vector array of bits
string array of characters
Defined in the ieee.std_logic_1164 package:
std_logic_vector array of std_logic
type std_logic_vector is array (natural <>) of std_logic;
ECE U530 F’0664lect08.ppt
Using Predefined Unconstrained Array Types
subtype byte is bit_vector(7 downto 0);….variable channel_busy : bit_vector(1 to 4);….constant ready_message :string := “ready”;….signal memory_bus: std_logic_vector (31 downto 0);
ECEU530
ECE U530 F’0665lect08.ppt
User-defined Unconstrained Array Types
type sample is array (natural range <>) of integer;
….variable long_sample is sample(0 to 255);….constant look_up_table_1: sample := (127, -45, 63, 23, 76);….constant look_up_table_2: sample := (1=>23, 2=>100, 3=>-16, 4=>11);
ECE U530 F’0666lect08.ppt
Array Attributes
• Most attributes are not synthesizable• Useful for writing simulation code
• These attributes can be determined statically
subtype WORD is std_logic_vector(7 downto 0);
WORD’range 7 downto 0WORD’reverse_range 0 to 7WORD’length 8WORD’high 7WORD’low 0WORD’left 7WORD’right 0
ECE U530 F’0667lect08.ppt
Array attributes
• Assign Thigh the highest and Tlow the lowest bit value in word:
signal Thigh, Tlow: std_logic;
signal Word1: Word;
Thigh <= Word1(Word’high);
Tlow <= Word1(Word’low);
ECE U530 F’0668lect08.ppt
Automatic Resource Sharing
PROCESS(OP, PC)BEGINIF OP = skip THEN
PC <= PC + 2;
-- Skip next instructionELSE
PC <= PC + 1;-- Normal sequenceEND IF;
END PROCESS;
PROCESS(OP, PC)
VARIABLE bump_val: integer RANGE 1 TO 2;
BEGIN
IF OP = skip THEN bump_val := 2;
ELSE bump_val := 1;
END IF;
PC <= PC + bump_val;
END PROCESS;
2
1
PC 2
1PC
ECEU530
ECE U530 F’0669lect08.ppt
Automatic Resource Sharing
PROCESS(A, B, C, D,
SEL)
BEGIN
IF SEL = '0' THEN
SUM <= A + B - C;
ELSE
SUM <= D + A + B;
END IF;
END PROCESS;
PROCESS(A, B, C, D, SEL)
VARIABLE temp:std_logic_vector(2 DOWNTO 0);
BEGIN
temp := A + B;IF SEL = '0' THEN
SUM <= temp - C;ELSE
SUM <= temp + D;END IF;END PROCESS;
Share
ECE U530 F’0670lect08.ppt
Example: Resource sharingprocess(OpSel, A, B, C, D, E, F, G, H)
begin
case OpSel is
when ”00” => Z <= A + B;
when ”01” => Z <= C + D;
when ”10” => Z <= E + F;
when ”11” => Z <= G + H;
when others => Z <= (others => ’X’) ;
end case;
end process;
• How many adders are inferred ?
ECE U530 F’0671lect08.ppt
To Guarantee Resource Sharing
• Create a function called Mux4
X <= Mux4(OpSel, A, C, E, G);
Y <= Mux4(OpSel, B, D, F, H);
Z <= X + Y;
• Function is NOT a component• more on functions and procedures later
• This guarantees one adder is inferred
ECE U530 F’0672lect08.ppt
Example: Resource sharingprocess(OpSel, A, B, C, D, E, F, G, H)
begin
if (OpSel = ”00”) then Z <= A + B; end if;
if (OpSel = ”01”) then Z <= C + D; end if;
if (OpSel = ”10”) then Z <= E + F; end if;
if (OpSel = ”11”) then Z <= G + H; endif;
end process;
• How many adders are inferred ?
ECEU530
ECE U530 F’0673lect08.ppt
Example: Resource sharingprocess(OpSel, A, B, C, D, E, F, G, H)
begin
if (OpSel = ”00”) then Z <= A + B;
elsif (OpSel = ”01”) then Z <= C + D;
elsif (OpSel = ”10”) then Z <= E + F;
elsif (OpSel = ”11”) then Z <= G + H;
endif;
end process;
• How many adders are inferred ?
ECE U530 F’0674lect08.ppt
Functions and Procedures
• Functions take parameters and return a value• In procedures, the return value is on the list of
arguments• For most CAD tools,
• functions are synthesizable–expand them in line
• Procedures are not synthesizable
• Functions, procedures are useful for • type conversion, bus resolution, ... • often appear in packages• testbenches
ECE U530 F’0675lect08.ppt
Functions
• Declared by specifying:
1)The name of the function
2)The input parameters, (if any), and their type
3)The type of the returned value
4) Any declarations required by the function itself
5)An algorithm for the computation of the returned value
ECE U530 F’0676lect08.ppt
Example 1 – Maj3
• Declaration:function MAJ3(X: STD_LOGIC_VECTOR(0 to 2)) return STD_LOGIC is
begin
return (X(0) and X(1)) or (X(0) and X(2))
or (X(1) and X(2));
end MAJ3;
• Use:C(1) <= MAJ3(A);
• Where to declare ?• Can be done within any declarative portion
(architecture, process etc.)
ECEU530
ECE U530 F’0677lect08.ppt
Wired AND Resolution Functiontype TS is (‘0’, ‘1’, ‘Z’);type TSV is (NATURAL range <>) of TS;function WIRED_AND(S: TSV) return TS is
variable RESOLVED_VALUE := ‘Z’;begin
for I in S’range loopif S(I) = ‘0’ then
RESOLVED_VALUE := ‘0’;exit;
elsif S(I) = ‘1’ thenRESOLVED_VALUE := ‘1’;
end if;end loop;return RESOLVED_VALUE;
end WIRED_AND;
ECE U530 F’0678lect08.ppt
Procedure
• Declared by specifying1) The name of the procedure2) The input and output parameters, (if any) and their types3) Any declarations required by the procedure itself4) An algorithm
• Difference between functions and procedures:• Functions evaluate to a value• Procedures have input and output parameters
ECE U530 F’0679lect08.ppt
Exampleprocedure ONES_AND_ZEROS_CNT
(variable X: in STD_LOGIC_VECTOR(0 to 2);
variable N_ONES, N_ZEROS: out STD_LOGIC_VECTOR(0 to 1)) is
variable NUM1: INTEGER range 0 to 3 := 0;
variable NUM0: INTEGER range 0 to 3 := 0;
begin
for I in 0 to 2 loop
if X(I) = ‘1’ then
NUM1 := NUM1 + 1;
else
NUM0 := NUM0 + 1;
end if;
end loop;
ECE U530 F’0680lect08.ppt
Example (contd.)case NUM1 is
when 0 => N_ONES := “00”
when 1 => N_ONES := “01”
when 2 => N_ONES := “10”
when 3 => N_ONES := “11”
end case;
case NUM0 is
when 0 => N_ZEROS := “00”
when 1 => N_ZEROS := “01”
when 2 => N_ZEROS := “10”
when 3 => N_ZEROS := “11”
end case;
end ONES_AND_ZEROS_CNT;
ECEU530
ECE U530 F’0681lect08.ppt
Usageprocess(INP)
variable N1, N0: STD_LOGIC_VECTOR(0 to 1);variable Z: STD_LOGIC_VECTOR(0 to 2);
beginZ := INP;
ONES_AND_ZEROS_CNT(Z, N1, N0);OUT1 <= N1;
OUT0 <= N0;end process;
• A variable is declared within a block, process, procedure, or function, and is updated immediately when an assignment statement is executed. Useful for functions and procedures.
• Procedures are usually not synthesizable• Functions are synthesizable: expanded in-line
ECE U530 F’0682lect08.ppt
Example: Type Conversiontype byte is array(7 downto 0) of bit;
procedure byte_to_integer (ib: IN byte;
oi: out integer) is
variable result: integer:= 0;
begin
for I in 0 to ib’range loop
if ib(I) = ‘1’ then
result := result + 2**i;
end if;
end loop;
oi := result;end byte_to_integer;
variable abyte: byte;
variable anint: integer;
byte_to_integer(abyte,anint);