Leadless Devices4 QFN Challenges that will Make you Scream!

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Bottom Terminated ComponentsThe 4 “Biggies” Void Reduction Cleaning Inspection Rework

1. Void ReductionAchieve Reliable Assembly with Minimal Voiding

Large area in thermal ground, lots of volume of flux, lots of outgassing

Voiding impedes thermal transfer, reducing the efficiency and lifetime of the package

No single approach has proven to be the solution Important to reduce overall % voids and size of largest void Try combinations of proven approaches to achieve the best

possible process

Solder paste is ~50% flux by volume

• Large paste deposit contains volatiles• During reflow volatiles must escape to accomplish

complete coalescence• Low standoff leaves no exit for excess volatiles

Strategies to Reduce Voiding

Thermal pad and via design Stencil design Reflow profile optimization

Thermal Pad Design Considerations

Strategy: break up thermal pad to discourage large voids and facilitate venting

“Window paning” creates pathways to vent volatiles

Reduced pockets of volatiles cause smaller voids and less overall voiding

Downside: Vent channels result in less solder joint continuity

Split Thermal Pads

Split thermal pads reduce the size of voids, but do not significantly reduce the total voiding area

For thermal transfer, large voids are more disruptive -> smaller voids allow for more transfer

Solder mask defined pads offer further improvement

Dr. Lee et al. study this in “The Effect of Thermal Pad Patterning on QFN Voiding”

Dr. Lee et al. study this in “The Effect of Thermal Pad Patterning on QFN Voiding”

Voiding in QFN Unfilled Via-in-pad

This is why you must “seal” via-in-pad !

Voiding + Via in Pad

• Voiding even with Pad window Paning! • Excessive voids can also cause co-planarity issues and open QFN joints• IPC & JEDEC stipulates at least 50% coverage criteria for the thermal pad.

Stencil Design

Instead of printing one large square at the center of QFNs: With greater paste volume, voiding increases, so aperture

designs that limit paste volume will reduce voiding Break up this square into smaller apertures Spaces between printed areas leave paths for volatiles to

escape

“Influence of Reflow Profile and Pb-free Solder Paste in Minimizing Voids for QFN Assembly” by T. Jensen, E. Briggs et al.

Effects of Window Paning

W Coleman; “Printing and Assembly Challenges for QFN Devices”; SMT Magazine, 4/11

Voiding vs. Stencil Thickness

Songninluck, et al; “QUAD FLAT NO LEAD (QFN) PACKAGE PROCESSING IN HIGH THERMAL MASS ASSEMBLY”; SMTAI-10

Voiding vs. Window Pane

Songninluck, et al; “QUAD FLAT NO LEAD (QFN) PACKAGE PROCESSING IN HIGH THERMAL MASS ASSEMBLY”; SMTAI-10

“Focal Dot”8mil spacing

Reflow Profiling There is no “magic” reflow profile to

minimize voiding For each assembly, the best profile will

balance several requirements: Thermal requirements of assembly Optimal profile for the chosen solder paste Requirements of other components (ie BGAs)

There will be an optimal profile, it may or may not minimize voiding

Profiling must be considered but not a solution

Low clearance Large center pad

High paste/flux volume Difficult cleaning flow path

2. Cleaning Underneath BTCs

BTC: No-Clean Residue Issues

No-Clean: Solvents can’t escape => residue not safe (even though full time/temp exposure)

Flux volatilization is a critical factor with regard to the complexity of the flux residue so that it becomes benign

The fluxes are not benign until they have seen enough heat to volatilize

the solvents create the insulative residue this can only be done with enough heat and

removal of the flux carrier

Courtesy of Foresite Inc

BTC No-Clean Residue Issue In a no-clean process, when the flux

is activated and fully volatilizes, it leaves a benign residue with no impact on field performance.

But when this solvent is not allowed to release: Flux residue is conductive and

moisture absorbing. Product in the field for 9 months to still

have gooey conductive flux causing performance problems.

BTC: No-Clean Residue Issues

T Munson; “ELECTRICAL LEAKAGE FAILURES DUE TO ENTRAPPED FLUX BELOW A QFN PACKAGE”; SMTAI-06

BTC Cleaning Need to have enough standoff

distance (min’m 2.5mils) Need to have pathways for the

cleaning solutions to get enough impingement energy to the “soils”

Need to have enough kinetic energy to break soils free

Measure using ion chromatography

Courtesy Zestron

BTC Cleaning Study

AOI: Pretty worthless Manual: Depends on wettable

surface Endoscope (edge viewing optical

microscope) reasonable for edge joints

X-Ray: good for voiding, bridges, wetting only method for central pad

3. Inspection

IPC Inspection Criteria

Pullback vs. No-pullback

V Solberg; “ PCB Design Principles for QFN and Other Bottom Termination Components”; APEX-11

Metallization-easier inspection

Shadowing; Solder Balls

Multiple pads different AOI Algorithms

Bastin & Krastev; “QFN PROCESS CONTROL VIA 2D AND 3D CT X-RAY INSPECTION TECHNIQUES “; SMTAI-11

More Defects; CT Scan

IPC 7711 3.11

4. ReworkHigh Yield, Simple and Fast

Rework TechniqueIPC 7711 3.11

Rework TechniqueIPC 7711 3.11

Step #1

Align and apply stencil to device. Roll solder paste through apertures.

Part Bumping Using a PolyimidePeel-n-Stick Stencil(s)IPC 7711 5.8.1.2.

Step #2

Reflow per solder mfr’s profile recommendations

Part Bumping Using a PolyimidePeel-n-Stick Stencil(s)

Step #3

Remove stencil and clean. Surface now is “bumped”

Part Bumping Using a PolyimidePeel-n-Stick Stencil(s)

Inspection of “bumped” device

Part Bumping Using a PolyimidePeel-n-Stick Stencil(s)

Step #4

Prep land area on PCB where device is to be placed

Part Bumping Using a PolyimidePeel-n-Stick Stencil(s)

Step #5

Align and adhere board stencil on PCB. Roll solder paste into apertures and clean off residue.

Part Bumping Using a PolyimidePeel-n-Stick Stencil(s)

Step #6

Place “bumped” QFN into stencil apertures. Feel the “bumps” fit into the apertures

Part Bumping Using a PolyimidePeel-n-Stick Stencil(s)

Step #7

Reflow as per solder paste manufacturers’ profile recommendations. Perform visual inspection. Perform X-ray inspection.

Part Bumping Using a PolyimidePeel-n-Stick Stencil(s)

Print Quality

Print Reliability

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