layout technique for double-gate silicon nanowire fet with...
TRANSCRIPT
![Page 1: Layout Technique for Double-Gate Silicon Nanowire FET with ...demichel/si.epfl.ch/files/content/sites/si/files/shared/Events/... · High-K Metal Gate Source Gate Drain Tri-gate aka](https://reader033.vdocuments.us/reader033/viewer/2022042108/5e87c8b983cc360672503883/html5/thumbnails/1.jpg)
Layout Technique for Double-Gate Silicon Nanowire FET with an Efficient
Sea-of-Tiles Architecture
Shashikanth Bobba
Prof. Giovanni De Micheli March 25, 2013
Pierre-Emmanuel, Jian Zhang, Luca, Michele, Davide, Prof. Yusuf Leblebici
![Page 2: Layout Technique for Double-Gate Silicon Nanowire FET with ...demichel/si.epfl.ch/files/content/sites/si/files/shared/Events/... · High-K Metal Gate Source Gate Drain Tri-gate aka](https://reader033.vdocuments.us/reader033/viewer/2022042108/5e87c8b983cc360672503883/html5/thumbnails/2.jpg)
Functionally Enhanced Device
Source
Drain
Gate
High-K Metal Gate
Gate Source Drain
Tri-gate aka FinFET Vertically stacked SiNW FET
Source Drain Gate
PG
CG S D C
ontr
ol g
ate
Polarity gate
Sour
ce
Dra
in
Sour
ce
32nm 16nm 10nm
Enhanced Functionality
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Double-gate Silicon Nanowire FET
! Dynamic control on the polarity of the device
! Promising feature for future reconfigurable circuits
! Ambipolar logic circuits
CG PG
S
D
CG S
D
CG S
D
p-FET
n-FET
PG
CG S D
Con
trol
gat
e Polarity gate
Sour
ce
Dra
in
![Page 4: Layout Technique for Double-Gate Silicon Nanowire FET with ...demichel/si.epfl.ch/files/content/sites/si/files/shared/Events/... · High-K Metal Gate Source Gate Drain Tri-gate aka](https://reader033.vdocuments.us/reader033/viewer/2022042108/5e87c8b983cc360672503883/html5/thumbnails/4.jpg)
Ambipolar Logic Circuits ! Circuits based on double gate ambipolar transistors with
controllable polarity (CNFET, SiNW FET, Graphene, …)
! Optimal for XOR and XNOR dominated circuits
XOR2
Only 4 transistors
M-H. Ben Jamaa, PhD Thesis
CNT-DR8F
O’Connor, ICECS 07
ULM (5,3)
K. Mohanram, DAC 12
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Fewer transistors for XOR operation
Every transistor has two gates to route
Motivation
XOR2 ??
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Physical Design Challenges
Manufacturing
Design and Architecture
Physical Synthesis
Logic Synthesis
DFM
Verification
Arithmetic circuits
Reconfigurable blocks
Universal logic modules
CNFET SiNW FET Graphene MoS2
E D A
! Can we use existing layout techniques?
! Logic bricks for improved Yield
CG PG
S
D
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! Introduction
! Layout Technique for DG-SiNW FET " Motivation
" Layout algorithm for XOR embedded Boolean functions
! Sea-of-Tiles
! Simulation Results
! Conclusion
Outline
![Page 8: Layout Technique for Double-Gate Silicon Nanowire FET with ...demichel/si.epfl.ch/files/content/sites/si/files/shared/Events/... · High-K Metal Gate Source Gate Drain Tri-gate aka](https://reader033.vdocuments.us/reader033/viewer/2022042108/5e87c8b983cc360672503883/html5/thumbnails/8.jpg)
Symbolic layouts : Dumbell-stick diagrams ! Need for new symbolic layouts for ambipolar circuits
!"#$%&&'()*+,,
!"#$%&%'(")*#&"&$+)
!"#$%"&'()$*+',"##*,$*-'$"(*$.*%'
!"#$%&%'(")+"(,*&$+)
/"&)%0$1'()$*+',"##*,$*-'$"(*$.*%'
Con
trol
gat
e
Polarity gate
Sour
ce
Dra
in
![Page 9: Layout Technique for Double-Gate Silicon Nanowire FET with ...demichel/si.epfl.ch/files/content/sites/si/files/shared/Events/... · High-K Metal Gate Source Gate Drain Tri-gate aka](https://reader033.vdocuments.us/reader033/viewer/2022042108/5e87c8b983cc360672503883/html5/thumbnails/9.jpg)
Layout technique for Unate logic functions ! Negative Unate functions: NAND, NOR, AOI, OAI
! Polarity gates are biased to either Vdd or Gnd
-'./0"1,232!,451%,
Vdd
A
A
Vdd
Gnd
Gnd
B
B
Out
-$./)($0)*(.#"&'/)+#'0)1(")234)#$5)264)
A
A
B
B
Vdd
Gnd Out
6,780..9%:;<)5&#+"#7)
t1 t2
t3
t4
t1 t2
t3
t4
t1 t2
t3 t4
![Page 10: Layout Technique for Double-Gate Silicon Nanowire FET with ...demichel/si.epfl.ch/files/content/sites/si/files/shared/Events/... · High-K Metal Gate Source Gate Drain Tri-gate aka](https://reader033.vdocuments.us/reader033/viewer/2022042108/5e87c8b983cc360672503883/html5/thumbnails/10.jpg)
Layout technique for Binate logic functions
=&7*.&>05)"(,:$+)
678,451%,?@-=)%'/.0).#/(,')
4(A0.)#**"(#;B)
!"#$%&%'(")+"(,*&$+)
?(7*.0C)"(,:$+)
A
Y
B
B A
A
B
B A
t1 t2
t3 t4
t1 t2
t3 t4
t2 t4
t1 t3
![Page 11: Layout Technique for Double-Gate Silicon Nanowire FET with ...demichel/si.epfl.ch/files/content/sites/si/files/shared/Events/... · High-K Metal Gate Source Gate Drain Tri-gate aka](https://reader033.vdocuments.us/reader033/viewer/2022042108/5e87c8b983cc360672503883/html5/thumbnails/11.jpg)
Complex gates with embedded XOR/XNOR
#D !"#$%&%'(")+"(,*&$+))
))))))6,780..9%:;<)5&#+"#7)
F1 = (A + B)(C + D)
Gnd B
Gnd A
CD
C D
Vdd A B
Vdd
C D
C D
F1
t1
t2
t3
t4
t5
t6
t7
t8
group D : {t4, t6}
group D : {t3, t5}
group Vdd : {t7, t8} group Gnd : {t1, t2}
8D))))!"#$%&%'(")*#&"&$+);D))))!"#$%&%'(")("50"&$+)
5D))))!"#$%&%'(");B#&$&$+)
![Page 12: Layout Technique for Double-Gate Silicon Nanowire FET with ...demichel/si.epfl.ch/files/content/sites/si/files/shared/Events/... · High-K Metal Gate Source Gate Drain Tri-gate aka](https://reader033.vdocuments.us/reader033/viewer/2022042108/5e87c8b983cc360672503883/html5/thumbnails/12.jpg)
Layout Extraction
6,780..9%:;<)5&#+"#7)
!"#$%&%'(")%&E&$+)F)G#/(,')+0$0"#:($)
VDD
GND
![Page 13: Layout Technique for Double-Gate Silicon Nanowire FET with ...demichel/si.epfl.ch/files/content/sites/si/files/shared/Events/... · High-K Metal Gate Source Gate Drain Tri-gate aka](https://reader033.vdocuments.us/reader033/viewer/2022042108/5e87c8b983cc360672503883/html5/thumbnails/13.jpg)
! Introduction
! Layout Technique for DG-SiNW FET
! Sea-of-Tiles " Tiles as basic blocks
" Optimal Tile
" Power distribution for SoT
! Simulation Results
! Conclusion
Outline
![Page 14: Layout Technique for Double-Gate Silicon Nanowire FET with ...demichel/si.epfl.ch/files/content/sites/si/files/shared/Events/... · High-K Metal Gate Source Gate Drain Tri-gate aka](https://reader033.vdocuments.us/reader033/viewer/2022042108/5e87c8b983cc360672503883/html5/thumbnails/14.jpg)
Sea-of-Tiles (SoT)
![Page 15: Layout Technique for Double-Gate Silicon Nanowire FET with ...demichel/si.epfl.ch/files/content/sites/si/files/shared/Events/... · High-K Metal Gate Source Gate Drain Tri-gate aka](https://reader033.vdocuments.us/reader033/viewer/2022042108/5e87c8b983cc360672503883/html5/thumbnails/15.jpg)
Layout regularity with Tiles
232!-, 678-,
!H()'"#$%&%'(")*#&"%)+"(,*05)'(+0'B0")
9.&%,
![Page 16: Layout Technique for Double-Gate Silicon Nanowire FET with ...demichel/si.epfl.ch/files/content/sites/si/files/shared/Events/... · High-K Metal Gate Source Gate Drain Tri-gate aka](https://reader033.vdocuments.us/reader033/viewer/2022042108/5e87c8b983cc360672503883/html5/thumbnails/16.jpg)
Sea-of-Tiles (SoT)
! Gate to Tile mapping
:51%(, /;, /-, /<, /=, />, /?, :;, :-, 4;, 4-,
6@A-, I$5) -,') J55) I$5) -,') J55) K) KL) ML) M)
6/@A-, I$5) -,') J55) I$5) -,') J55) K) KL) M) ML)
25/B-, -,') J55) -,') -,') 9) I$5) K) M) I$5) J55)
2@A-, J55) 9) -,') -,') I$5) -,') K) M) I$5) J55)
C/D-6, J55) -,') J55) I$5) -,') I$5) K) K) I$5) J55)
E"F, -N) J55) -O) -O) I$5) -N) K) -N) I$5) J55)
![Page 17: Layout Technique for Double-Gate Silicon Nanowire FET with ...demichel/si.epfl.ch/files/content/sites/si/files/shared/Events/... · High-K Metal Gate Source Gate Drain Tri-gate aka](https://reader033.vdocuments.us/reader033/viewer/2022042108/5e87c8b983cc360672503883/html5/thumbnails/17.jpg)
Various logic Tiles as basic building blocks
9.&%:-,
9.&%:;,
9.&%:<,
9.&%:;G-, 2314%0-'50&*6'
3
![Page 18: Layout Technique for Double-Gate Silicon Nanowire FET with ...demichel/si.epfl.ch/files/content/sites/si/files/shared/Events/... · High-K Metal Gate Source Gate Drain Tri-gate aka](https://reader033.vdocuments.us/reader033/viewer/2022042108/5e87c8b983cc360672503883/html5/thumbnails/18.jpg)
Design flow for determining the Optimal Tile
Generate Tiles
Synopsys Design Compiler Library of Tiles
TECHNOLOGY MAPPING
Physical Synthesis onto
Sea-of-Tiles
Benchmark Circuits
Area
![Page 19: Layout Technique for Double-Gate Silicon Nanowire FET with ...demichel/si.epfl.ch/files/content/sites/si/files/shared/Events/... · High-K Metal Gate Source Gate Drain Tri-gate aka](https://reader033.vdocuments.us/reader033/viewer/2022042108/5e87c8b983cc360672503883/html5/thumbnails/19.jpg)
Design flow for determining the Optimal Tile
Generate Tiles
Synopsys Design Compiler Library of Tiles
TECHNOLOGY MAPPING
Physical Synthesis onto
Sea-of-Tiles
Benchmark Circuits
Area
P
P
K M
+
A
A
+
?
A
+
+ P
TileG2 #1 TileG2 #2
Unmapped active area
![Page 20: Layout Technique for Double-Gate Silicon Nanowire FET with ...demichel/si.epfl.ch/files/content/sites/si/files/shared/Events/... · High-K Metal Gate Source Gate Drain Tri-gate aka](https://reader033.vdocuments.us/reader033/viewer/2022042108/5e87c8b983cc360672503883/html5/thumbnails/20.jpg)
Result: Impact on Area
9.&%:-,9.&%:;, 9.&%:<,9.&%:;G-,
Area across various benchmarks 2@A#5&.H%B
,3A%5 ,
- 14% - 16%
! TileG2 and TileG1h2 optimal for mapping logic gates, with respect to reduced routing complexity thereby reducing in the overall active area
![Page 21: Layout Technique for Double-Gate Silicon Nanowire FET with ...demichel/si.epfl.ch/files/content/sites/si/files/shared/Events/... · High-K Metal Gate Source Gate Drain Tri-gate aka](https://reader033.vdocuments.us/reader033/viewer/2022042108/5e87c8b983cc360672503883/html5/thumbnails/21.jpg)
Sea-of-Tiles Power Distribution… VDD
VDD
GND
GND
Too much requirements in wiring
NAND XOR
Vdd
A
A
Vdd
Gnd
B
B
Y
NAND2 XOR2
Source: S. Bobba et al, NANOARCH’12
![Page 22: Layout Technique for Double-Gate Silicon Nanowire FET with ...demichel/si.epfl.ch/files/content/sites/si/files/shared/Events/... · High-K Metal Gate Source Gate Drain Tri-gate aka](https://reader033.vdocuments.us/reader033/viewer/2022042108/5e87c8b983cc360672503883/html5/thumbnails/22.jpg)
Sea-of-Tiles Power Distribution VDD
VDD
GND
GND
GND
GND
GND
GND
VDD VDD VDD
Lower wiring requirements
Source: S. Bobba et al, NANOARCH’12
![Page 23: Layout Technique for Double-Gate Silicon Nanowire FET with ...demichel/si.epfl.ch/files/content/sites/si/files/shared/Events/... · High-K Metal Gate Source Gate Drain Tri-gate aka](https://reader033.vdocuments.us/reader033/viewer/2022042108/5e87c8b983cc360672503883/html5/thumbnails/23.jpg)
! Introduction
! Layout Technique for DG-SiNW FET
! Sea-of-Tiles
! Simulation Results " Arithmetic Circuits
" Circuit level Benchmarking
! Conclusion
Outline
![Page 24: Layout Technique for Double-Gate Silicon Nanowire FET with ...demichel/si.epfl.ch/files/content/sites/si/files/shared/Events/... · High-K Metal Gate Source Gate Drain Tri-gate aka](https://reader033.vdocuments.us/reader033/viewer/2022042108/5e87c8b983cc360672503883/html5/thumbnails/24.jpg)
Case study: Arithmetic Circuits
Arithmetic Cell Library Logic Gates (FO4 delay)
0 100 200 300 400 500 600 700 800
5-bit ripple-carry adder
16-bit carry-select adder
(29, 3)-compressor
(11, 2)-reduction tree (16 x 16 MAC)
Wallace tree (54 x 54 multiplier)
(31, 5) Parallel counter
Area 22.7%
22%
40%
45%
38%
22%
PG
CG S D
Con
trol
gat
e
Polarity gate
Sour
ce
Dra
in
Sour
ce
![Page 25: Layout Technique for Double-Gate Silicon Nanowire FET with ...demichel/si.epfl.ch/files/content/sites/si/files/shared/Events/... · High-K Metal Gate Source Gate Drain Tri-gate aka](https://reader033.vdocuments.us/reader033/viewer/2022042108/5e87c8b983cc360672503883/html5/thumbnails/25.jpg)
0 10 20 30
5-bit ripple-carry adder
16-bit carry-select adder
(29, 3)-compressor
(11, 2)-reduction tree (16 x 16 MAC)
Wallace tree (54 x 54 multiplier)
(31, 5) Parallel counter
Case study: Arithmetic Circuits
Arithmetic Cell Library Logic Gates
Delay 66%
71.7%
66%
57.6%
61.8%
63.8%
2.8x improvement
![Page 26: Layout Technique for Double-Gate Silicon Nanowire FET with ...demichel/si.epfl.ch/files/content/sites/si/files/shared/Events/... · High-K Metal Gate Source Gate Drain Tri-gate aka](https://reader033.vdocuments.us/reader033/viewer/2022042108/5e87c8b983cc360672503883/html5/thumbnails/26.jpg)
Circuit Level Benchmarking
Generate Tiles
Synopsys Design Compiler Encouter Library
Characterizer TECHNOLOGY MAPPING
Physical Synthesis onto
Sea-of-Tiles
Benchmark Circuits
Delay
TCAD-based table model
Leakage
1.8x improvement
![Page 27: Layout Technique for Double-Gate Silicon Nanowire FET with ...demichel/si.epfl.ch/files/content/sites/si/files/shared/Events/... · High-K Metal Gate Source Gate Drain Tri-gate aka](https://reader033.vdocuments.us/reader033/viewer/2022042108/5e87c8b983cc360672503883/html5/thumbnails/27.jpg)
! Introduction
! Layout Technique for DG-SiNW FET
! Sea-of-Tiles
! Simulation Results
! Conclusion
Outline
![Page 28: Layout Technique for Double-Gate Silicon Nanowire FET with ...demichel/si.epfl.ch/files/content/sites/si/files/shared/Events/... · High-K Metal Gate Source Gate Drain Tri-gate aka](https://reader033.vdocuments.us/reader033/viewer/2022042108/5e87c8b983cc360672503883/html5/thumbnails/28.jpg)
Conclusion
! Proposed a novel layout methodology and algorithm for Boolean functions with embedded XOR
! Showed an efficient implementation of Ambipolar circuits with Sea-of-Tiles design methodology
# Area optimal tiles TileG2 and TileG1h2
! Circuit Level Benchmarking
# Maximum improvement for Arithmetic circuits (2.8x)
# Reduction in Leakage power (16x)
![Page 29: Layout Technique for Double-Gate Silicon Nanowire FET with ...demichel/si.epfl.ch/files/content/sites/si/files/shared/Events/... · High-K Metal Gate Source Gate Drain Tri-gate aka](https://reader033.vdocuments.us/reader033/viewer/2022042108/5e87c8b983cc360672503883/html5/thumbnails/29.jpg)
Thank You