layout of mosfet

8/11/2019 Layout of mosfet

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ANALOG & DIGITAL VLSI

DESIGN

EEE/ INSTR C443/F313

MWF 11-12 noon, 1223

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ADVD

NALANDA


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Their work spawned themicroelectronicsrevolution that has changed forever theway we live, work, and communicate."

INTEGRATED CIRCUIT

George H. Heilmeier, Bell Communications

Research.


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INTEGRATED CIRCUIT

Our world is full of integrated circuits. You find

several of them in computers.

The microprocessor is an integrated circuit that

processes all information in the computer. It

mouse has been moved. It counts numbers and

runs programs, games and the operating

system. Integrated circuits are also found in almost every

modern electrical device such as cars, television

sets, CD players, cellular phones, etc4ANU GUPTA BITS PILANI,

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INTEGRATED CIRCUIT

They were born four years apart in two distant places, and yet they

were destined to start a technological revolution that changed the

world.

Without knowing each other, through two independent paths, bothinvented, almost at the same time, the Integrated Circuit (IC)

The invention of Jack Kilby and Robert Noyce, also known as "the

chip", has been recognized as one of the most important

innovations and significant achievements in the history of

humankind. 5ANU GUPTA BITS PILANI,PILANI


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Need of IC technology

Electrical engineers were aware of the potential of digital

electronics, however, they faced a big limitation known

as the "Tyranny of Numbers." This was the metaphor

that described the exponentially increasing number of

components required to design improved circuits,

of components that could be assembled together.

Both, Kilby at Texas Instruments, and Noyce at FairchildSemiconductor, were working on a solution to this

problem during 1958 and 1959.


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Tyranny of numbers

When building a circuit, it is very important that all connections areintact. If not, the electrical current will be stopped on its waythrough the circuit, making the circuit fail. Before the integratedcircuit, assembly workers had to construct circuits by hand,soldering each component in place and connecting them withmetal wires. Engineers soon realized that manually assembling the

vast number of tiny components needed in, for example, acomputer would be impossible, especially without generating as ng e au y connec on.

Another problem was the size of the circuits. A complex circuit, likea computer, was dependent on speed. If the components of thecomputer were too large or the wires interconnecting them too

long, the electric signals couldnt travel fast enough through thecircuit, thus making the computer too slow to be effective.

So there was a problem of numbers. Advanced circuits containedso many components and connections that they were virtuallyimpossible to build. This problem was known as the tyranny ofnumbers. 7ANU GUPTA BITS PILANI,

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INTEGRATED CIRCUIT DESIGN

The solution was found in the monolithic (meaning

formed from a single crystal) integrated circuit.

Instead of designing smaller components, they found the

way to fabricate entire networks of discrete components

in a single sequence by laying them into a single crystal

(chip) of semiconductor material.

Kilby used germanium and Noyce used silicon

Texas Instruments filed for a patent in February 1959.

Fairchild Semiconductor did the same in July 1959.Naturally, both firms engaged in a legal battle that lasted

through the decade of the 60s until they decided to

cross-license their technologies.


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JACK KILBY

The Patent No. 3,138,743 for Miniaturized ElectronicCircuits, were issued to Jack S. Kilby and TexasInstruments in 1964.

Kilby holds patents on sixty inventions, including the

invention of the electronic hand-held calculator in 1967. ,

and was inducted into the National Inventors Hall ofFame in 1982

In October 10, 2000, The Royal Swedish Academy of

Sciences awarded Jack Kilby the Nobel Prize in Physicsfor 2000 "for basic work on information andcommunication technology."


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ROBERT NOYCE

The Patent No. 2,981,877 for the silicon based ICwas granted to Robert Noyce,

In 1968, He founded INTEL, the companyresponsible for the invention of the microprocessor.

Dr. Noyce was issued 16 patents in the area of,

Inventors Hall of Fame in 1983. He died on June 3,1990.

Noyces circuit solved several practical problemsthat Kilbys circuit had, mainly the problem ofinterconnecting all the components on the chip.This was done by adding the metal as a final layerand then removing some of it so that the wiresneeded to connect the components were formed.10ANU GUPTA BITS PILANI,

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Moores lawdriving force


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Moores law

The law is named afterIntel co-founderGordon E.

Moore, who described the trend in his 1965 paper.

The paper noted that number of components in

integrated circuits had doubled every yearfrom the

invention of the integrated circuit in 1958 until 1965 andpredicted that the trend would continue "for at least ten

years".[10]

His prediction has proved to be uncannily accurate, in

part because the law is now used in the semiconductorindustry to guide long-term planning and to set targets

forresearch and development.


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an ou


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Previous knowledge

Digital electronics

Micro electronic circuits

Electronic devices


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Objective

VLSI circuit design and verification

Silicon implementation

Usa e of EDA tools


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Goals of this Course

Learn to design and analyze state-of-the-art digital VLSI chips using CMOStechnology

Understand design issues at the layout,, -

Performance analysis and optimization

Use commercial design software in the lab

Complexity management Understand the complete design flow


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VLSI DESIGN

Panoramic View


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What is VLSI design?

A way to design electronic circuits

Dimensionally micron, submicron, nano

range


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Why VLSI imp?

Current day technology

Micro electronics creeping in alldisciplines--- (merger of various disciplines in

system design) ra n mapp ng, ar c a

intelligence

Electromechanical systemsrobotics

Communication, Smart and secure homes,

Identification , vehicular electronics,process control 21ANU GUPTA BITS PILANI,

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Uniqueness of VLSI Design

HIGH INTEGRATION DENSITY

INTERCONNECT CROSS TALK,

MISMATCH (ON CHIP, DIE TO DIE),

COMPLEX DESIGNS,

DESIGN VERIFICATION & TESTABILITY

are important design issues now

FAST CHANGING TECHNOLOGY

PORTING DESIGN TO NEW TECH GENERATION ,

NEW SET OF DESIGN RULESmake design indep. of design rulesleverage existing work: programs ,building blocks


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VLSI design flow--Y chart (D.GJASKI)


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VLSI Design Concerns

VLSI design evolution

VLSI Design Methodologies

Structures design techniques

Design Quality

Packaging technology


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Microprocessors--------1970---- progrm/software

Digital signal processor---1980prog/hard wired

FPGA/ASIC--1990---prog, specific/ specific, vol

produc.

SOC---------------------2000

SIP------------SYSTEM in PACKAGE


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SIP/ SOC

System-on-chip (SOC) is an integrated circuit thatincludes a processor, a bus, and other peripheral

elements on a single monolithic substrate

System on Chip (SOC) design is implemented in which

various components, such as volatile memory systems,- ,

systems, mixed signal circuits and logic circuits are each

formed into units and integrated on a single chip.

The primary advantages of SOC devices are lower

costs, greatly decreased size, and reduced powerconsumption of the system

A system-on-chip is designed by stitching together

multiple stand-alone VLSI designs (cores) to provide full

functionality for an application 27ANU GUPTA BITS PILANI,PILANI


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SIP SiP permits high levels of functional density by incorporating

combinations ofwirebond, flip-chip, stacked devices,embedded devices, MEMS, and package-on-package .

This allows designers to use SiP implementation for

subsystems and systems that are not technically viable in a .

Packaging concepts include chip stacked on-chip, flip-chip

stacked on-chip, chips placed side by side in a package, as

well as other concepts. These complicate the design

partitioning process


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SIP

Additionally, SiP technology allows lower power and less

noise at the interconnect level, flexibility in mixing and

matching IC technologies, and reduced board size and

cost through inclusion of passive components,

consolidation of packaging and reduction of layers. And, ,

can be much quicker to develop.

SiP designs are typically only attempted when a wall is

reached-such as size or performance constraints-and

conventional system-on-chip (SoC) solutions are too

expensive to implement


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VLSI Design Methodology

Design MethodologyIt is a combination

of CAD tools, design strategies,

verification strategies

Strategies to ensure successful design Is

mainly guided by physical technology

(silicon implementation of the design)


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VLSI Design Styles

Programmable Logic Devices

Programmable Logic Device (PLD)

Field Programmable Gate Array (FPGA)

Standard Cell (Semi-Custom Design)

Full-Custom Design


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IMPACT OF VLSI DESIGN STYLES ON DESIGN

CYCLE TIME AND ACHIEVABLE CHIP PERFORMANCE


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PERFORMANCE IMPROVEMENT OF A

VLSI PRODUCT FOR EACH NEW GENERATION

OF MANUFACTURING TECHNOLOGY


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Analog Design

Only Full custom

Fully handcrafted design

Each design requires specific performance

Lack of Automation supporting CAD tools


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DIGITAL CMOS CHIP DESIGN

OPTIONS


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Field Programmable Gate

Arra FPGA


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Introduction

User / Field Programmability.

Array of logic cells connected via

routing channels.

.

Logic cells are mainly lookup tables

(LUT) with associated registers.

Interconnection on SRAM basis or

antifuse elements.


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Xilinx XC4000 Architecture

CLB

CLB

CLB

CLB

Switch

Matrix D Q

SlewRate

Control

PassivePull-Up,

Pull-Down

Delay

Vcc

Output

Buffer

Input

Buffer

Q D

Pad

rogramma e

Interconnect I/O Blocks (IOBs)

Configurable

Logic Blocks (CLBs)

D Q

SD

RD

EC

S/R

Control

D Q

SD

RD

EC

S/R

Control

1

1

F

G

H

DIN

F

G

H

DIN

F

G

H

H

H

Func.Gen.

GFunc.Gen.

FFunc.Gen.

G4G3G2G1

F4F3F2F1

C4C1 C2 C3

K

Y

X

H1 DIN S/R EC


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XC4000E Configurable Logic

Blocks

D Q

SD

EC

S/RControl

F

G

H

DIN

GFunc.Gen.

G4G3

G2G1

C4C1 C2 C3

YQ

H1 DIN S/R EC

2 Four-input function

generators (Look Up

Tables)

- 16x1 RAM or

Logic function

RD

D Q

SD

RD

EC

S/RControl

1

1

F

G

H

DIN

F

G

H

H

HFunc.Gen.

FFunc.Gen.

F4F3F2F1

K

Y

XQ

X

2 Registers

- Each can be

configured as Flip

Flop or Latch

- Independentclock polarity

- Synchronous and

asynchronous

Set/Reset


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Look Up Tables

Combinatorial Logic is stored in 16x1 SRAM Look Up

Tables (LUTs) in a CLB

Example:

A B C D Z

Look Up Table

Combinatorial Logic

AB

4-bit address

Capacity is limited by number ofinputs, not complexity

Choose to use each function

generator as 4 input logic (LUT) or

as high speed sync.dual port

RAM

0 0 0 1 0

0 0 1 0 0

0 0 1 1 1

0 1 0 0 1

0 1 0 1 1. . .1 1 0 0 0

1 1 0 1 0

1 1 1 0 0

1 1 1 1 1

CD

GFunc.Gen.

G4G3G2G1

WE


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XC4000X I/O Block Diagram

Shaded areas are not included in XC4000E family. 42ANU GUPTA BITS PILANI,

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Xilinx FPGA Routing

1) Fast Direct Interconnect - CLB to CLB

2) General Purpose Interconnect - Uses switch matrix

CLB CLB

CLB CLB

Switch

Matrix

Switch

Matrix


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Programmable Switches


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Design Flow

Design Entry in schematic, ABEL, VHDL,and/or Verilog. Vendors include Synopsys,

Aldec (Xilinx Foundation), Mentor,Cadence, Viewlogic, and 35 others.

Implementation includes Placement &Routing and bitstream generation using

1

XC4000XC4000XC4000

3

nx s ec no ogy. so, ana yze t m ng,view layout, and more.

Download directly to the Xilinxhardware device(s) withunlimited reconfigurations* !!

*XC9500 has 10,000 write/erase cycles

M1 Technology


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Gate Array

In view of the fast prototyping capability, thegate array (GA) comes after the FPGA. Design implementation of

FPGA chip is done with user programming,

Gate array is done with metal mask design and processing.

Gate array implementation requires a two-stepmanufacturing process:1. The first phase, which is based on generic (standard)

masks, results in an array of uncommitted transistorson each GA chip.

2. These uncommitted chips can be customized later,which is completed by defining the metalinterconnects between the transistors of the array


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Channeled vs. Channel-less(SoG) Approaches


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Small Section of a Semi-custom Base

Array Without Interconnect


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Section of Semi-custom Array with

Single Level Metal Interconnect


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The GA chip utilization factor is higher

than that of FPGA.

The used chip area divided by the total chip

area.

Chip speed is also higher.

More customized design can be achieved with

metal mask designs.

Current gate array chips can implement as

many as hundreds of thousands of logic

gates.52ANU GUPTA BITS PILANI,

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Standard Cell Based Design


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CBIC

One of the most prevalent custom design styles.

Also called semi-custom design style.

Requires development of a full custom mask set.

All of the commonly used logic cells are developed,

characterized, and stored in a standard cell library.

A typical library may contain a few hundred cells

including inverters, NAND gates, NOR gates,complex AOI, OAI gates, D-latches, and flip-flops.


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Characteristic of the Cells

Each cell is designed with a fixed height.

To enable automated placement of the cells, and

Routing of inter-cell connections.

A number of cells can be abutted side-by-side to form

rows.

The power and ground rails typically run parallel to the

upper and lower boundaries of the cell.

Neighboring cells share a common power and ground bus.

nMOS transistors are located closer to the ground rail while the

pMOS transistors are placed closer to the power rail.

The input and output pins are located on the upper and

lower boundaries of the cell. 55ANU GUPTA BITS PILANI,PILANI


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Standard Cells


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Standard Cell Layout


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Fl l f St d d C ll


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Floor-plan for Standard Cell

Design

Inside the I/O frame which is reserved for I/O

cells, the chip area contains rows or columns of

standard cells.

Between cell rows are channels for dedicated inter-

.

Over-the-cell routing is also possible.

The physical design and layout of logic cells

ensure that

When placed into rows, their heights match.

Neighboring cells can be abutted side-by-side, which

provides natural connections for power and ground

lines in each row. 58ANU GUPTA BITS PILANI,PILANI


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Full Custom Design


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Introduction

The standard-cells based design is oftencalled semi custom design.

The cells are pre-designed for general use andthe same cells are utilized in many different

chip designs. In the full custom design, the entire mask

design is done anew without use of anylibrary. The development cost of such a design style is

prohibitively high.

The concept of design reuse is becoming popular in

order to reduce design cycle time and cost.61ANU GUPTA BITS PILANI,

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Contd.

The most rigorous full custom design canbe the design of a memory cell.

Static or dynamic.

Since the same layout design is replicated,

density memory chip design.

For logic chip design, a good compromise

can be achieved by using a combination ofdifferent design styles on the same chip.

Standard cells, data-path cells and PLAs.62ANU GUPTA BITS PILANI,

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In real full-custom layout in which the

geometry, orientation and placement of every

transistor is done individually by the designer,

Full-custom layout

.

Typically 10 to 20 transistors per day,

per designer.


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Continued

In digital CMOS VLSI, full-custom design is

rarely used due to the high labor cost.

Exceptions to this include the design of high-

volume products such as memory chips, high-

masters.

Next slide shows the full layout of the Intel 486

P chip. Good example of a hybrid full-custom design.


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Small Section of a Typical Full Custom


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Small Section of a Typical Full Custom

Layout


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Comparison Among Various


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Comparison Among Various

Design Styles

Design Style

FPGA Gate

array

Standard

cell

Full

custom

Cell size Fixed Fixed Fixed Variable

Cell type Program

mable

Fixed Variable Variable

Cell

placement

Fixed Fixed In row Variable

Interconnectio

ns

Program

mable

Variable Variable Variable

Design time Very fast Fast Medium Slow


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Some important issues

Highly complex design--- structured design

strategies

Packaging


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Managing design complexity

Hierarchydivide and conquer

Regularityrepetition of blocks

Modularity---each block complete in itselfexternal details

Locality---connections are mostly between

neighboring modules (internal details)


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Structured Design Strategies

Strategies common for complex hardwareand software projects.

-> Hierarchy: Subdivide the design intomany levels of sub-modules

-> -unambiguously & well defined interfaces

-> Regularity: Subdivide to max numberof similar sub-modules at each level

-> Locality: Max local connections,keeping critical paths within moduleboundaries


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Regularity

Design the chip hierarchy into many modules ifpossible identical

Extended use of a single design simplifies thedesign process

Regularity can exist at all levels of designhierarchy

Circuit Level: uniform transistor sizes rather than

manually optimizing each device. Logic Level: identical gate structures rather than

customize every gate.

Architecture Level: construct architectures that

use a number of identical processor structures


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Modularity

Adds to hierarchy and regularity the qualities of

Well defined functions and interfaces is a must

Unambiguous functions

Well defined behavioral, structural, andphysical interfaces

Enables modules to be individually designedand evaluated.


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Locality

TIME LOCALITY: modules see a common clockand synchronous timing is applied.

Robust clock generation and distribution is

critical Critical paths, where possible, are to be kept

within module boundaries

Any global module to module signal should have

an entire clock cycle to traverse the chip. Replicate logic, if necessary, to alleviate cross-

chip crossings.

Locate modules in layout to minimize large or"global" routes between modules.


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Design for manufacturability

Design goal: All fabricated circuits meet all

performance specs under all operating

conditions.

Impediments:

Random variations in fabrication process.

Random variations in operating conditions,e.g. VDD, Temp. ambient.


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Reality: Excessive deviations of

erformance cause ield loss and increase

Why DFM important?

the

unit cost of the chip increases


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DFM Issues:

1. Parametric yield estimation.

2. Parametric yield maximization.

. - .

4. Variability Minimization.


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DFM

DFM Practice:

Consider the effects of expected randomness in

processing and operating conditions early in thedesign process.

Circuit made as insensitive to these variations as

is practical.

Design to performance specs with sufficientmargins that a large fraction of the manufactured

chips pass the chip acceptance criteria.


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Design cycle time-definition

Time period from the start of chip development until the

mask tape delivery time.

-------

desired level of chip performance.

-------Level of circuit performance achieved dependsstrongly on the design methodology


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Design Success parameters

Design is a continuous tradeoff to achieveperformance specs with adequate results in allthe other parameters.

Design Parameters By Which Design Success Is

Performance Specs - function, timing, speed, power

Size of Die - manufacturing cost

Time to Design - engineering cost and schedule

Ease of Test Generation & Testability - engineeringcost, manufacturing

cost, schedule

Manufacturability - resilient to circuit/processvariabilities 79ANU GUPTA BITS PILANI,

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Design Quality

ACHIEVE SPECIFICATIONS (Static & Dynamic)

DIE SIZE---less

POWER DISSIPATION---less

TESTABILITY--- 100% YIELD AND MANUFACTURABILITY100%

RELIABILITY

TECHNOLOGY UPDATABLE/ PORTABLE


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TESTABILITY

generation of good test vectors

availablity of reliable test fixture at speed

Contd.

YIELD AND MANUFACTURABILITY

functional yield

parametric yield


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Contd.

RELIABILITY premature aging (Infant mortality)

ESD ELECTROSTATIC DISCHARGE.

latchup

-

power and ground bouncing

TECHNOLOGY UPDATABLE Easily updated to new design rules


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ESD


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ESD ESD is a transient discharge of static charge that arises from either

human handling or a machine contact.

Although ESD is the result of a static potential in a charged object,

the energy dissipated and damages made are mainly due to the

current flowing through ICs during discharge.

interconnect burn-out or oxide break-down. The basic phenomenon

of ESD is that is a large amount of heat is generated in a localized

volume significantly faster than it can be removed, leading to a

temperature in excess of the materials safe operating limits. ESD Damages

pn-junction may melt., Gate oxide may have void formation., Metal

interconnects & Vias may melt or vaporization, leading to

shorts or opens, Gate-oxide breakdown is another form of ESD damage.83ANU GUPTA BITS PILANI,

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Packaging Technology

Include important package related

parasitics in the chip design and

simulation

Packa e Power & Ground Planes On-chip power and ground bounce

Bond Wire Lengths -> on-chip inductive

effects Thermal Resistance -> temp rise due to

on-chip power dissipation

Package Cost84ANU GUPTA BITS PILANI,

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WIRE BONDINGS


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WIRE BONDINGS


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Important package design concerns:

hermetic seals to prevent penetration of

moisture

thermal conductivity shd be high

pin densityhigh keeping small size

parasitic inductance and capacitance--low

alpha-paricle protection ( especially inmemories)


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Package types


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Custom Integrated Circuit

Specific purpose


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C t i t ti


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Custom integration

An integrated circuit that requires a full set

of masks specifically designed for a

particular function or application.

A custom IC is usually developed for a

specific customer and may have to

withstand harsh environments .


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Wh consider c stom integration?


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Why consider custom integration?

There are a number of reasons why

developing a custom Integrated Circuit is

an appropriate and often essential

ingredient to the development of asuccessful product


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Reasons


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Reasons

Size. The continued market demand to

reduce the size of electronic devices, in

particular portable and hand-held devices,

requires ever higher levels of integration. Replacing functions requiring the use of a

number of discrete components with one

IC helps achieve this goal.


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Contd.

Performance. By utilizing the superior

matching and tracking characteristics of

integrated circuit components, manual

adjustment of circuit parameters can oftenbe eliminated, while maintaining tighter

spread on key system performance specs

over the full range of operating conditions.

Additionally, critical or high-precision

specs can be trimmed at wafer test.


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Contd


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Contd.

Cost. Replacing a number of discrete

components with a pre-tested IC

significantly reduces the test time and the

number of rejects. For large production quantities the initial

development cost will be amortized in a

short period of time, resulting in a lower

cost per unit.


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Contd


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Contd.

Reliability.An IC is significantly more

reliable than a PCB populated with the

devices necessary to provide the

equivalent functionality using discretecomponents or multiple ICs.


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Contd


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Contd.

Copy protection. This can be the most

important incentive to consider custom

integration. Simple hardware copying is

prevented because of the exclusivity of thecustom IC.


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What are the fab technology options?


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What are the fab. technology options?

The three principal technologies which are

readily accessible for custom integration

are Biploar, CMOS and BiCMOS

Choice between using a prefabricated

semi-custom array or undertaking a full

custom development


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CMOS processing


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CMOS processing

N-WELL

P-WELL

TWIN-TUB


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Wafer preparation


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Wafer preparation

defect free single crystalline lightly dopedWAFER.

Metallurgical grade silicon-electronic grade

silicon(99.99% pure) Single crystalline structure obtained bymelting and then cooling ---Czochralskimethod

Ingot cut into wafers using diamond saw Wafers are than polished to mirror finish


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Process involved


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Process involved

Photolithography

Deposition

Oxidation

Diffusion/ion implantation


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General Principles


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General Principles

Technology changes fast, so it is importantto understand the general principles whichwould span technology generations

optimization, tradeoffs

wor as par o a group

leverage existing work: programs ,buildingblocks

Concepts remain the same: Example: relays -> tubes -> bipolar transistors-> MOS transistors

layout of mosfet

Documents