Latch-TDC

Da-Shung SuSu-Yin Wang, Jia-Ye Chen

Ting-Hua Chang, Wen-Chen Chang2011/06/08

The Drift Time of Hits

RF20 ns

Tmax. drift = 1-2 s, depending on the gas used for the proportional tubes.

Timing Relations Between Hits and Trigger

RF

“Latch”-TDC• Each channel consists of a shift register with a depth longer than 64 clocks.

Whenever there comes a wire chamber signal, a hit is registered. The actual depth of the shift register is determined by the need of trigger latency.

• The signal of one channel will be sampled by the clock with four different phases and be placed in four shift registers respectively. We use both rising and falling edges of the clock for the sampling. The final timing resolution of sampling will be in principle 1/8 of the period of clock source.

• The hit pattern sampled by four PLLs is represented by 4 bits for each channel, as shown in the table.

• Upon the arrival of a trigger, the hit pattern of an accepted window of 64-step width in the shift register, 64*4=256 bits=32 bytes, will be copied to the output memory for each channel. This CIP action introduces the dead time of TDC module.

• The timing information could be retrieved from the "position" of the hit in the shift register and the preset delay time. Multi-hit information is also preserved.

Design of Clock Lines

Sampling Results and Output

Sampling Results for Output

Q3 Q2 Q1 Q0 Y2 Y1 Y0

0 0 0 0 0 0 0

X X 1 0 0 0 1

X 1 0 0 0 1 0

1 0 0 0 0 1 1

1 1 1 1 1 0 0

X X 0 1 1 0 1

X 0 1 1 1 1 0

0 1 1 1 1 1 1

•At each time bin, Q0, Q1, Q2 and Q3 are the sampling results of the input signal with the four different phases of the clock. •Q0 is the starting phase, i.e. t(Q0) is earlier those of the others. •“x” stands for either 0 or 1.•We assume that two hits are separated from each other more than 1 clock away, and a valid hit sustains more than 1-clock wide.

Leading edge detected.

Signal on.

Trailing edge detected.

No signal

Data Throughput

• Assume each channel will output 32 bytes per event• For each card: 32*64 = 2048 bytes per event• For a more-full VME crate: 2048*15 ~ 30K bytes per event• For the system of total of 100 cards: 200KB per event• Assume Trigger rate 2KHz : 2000* 200 = 400 MB per sec• A Gigabit Ethernet support at 1 Gbps (1000 Mbps=125

MBps) is preferred.• If zero suppression is implemented, the data rate can be

further reduced, perhaps by a factor of 2 or 3.

David Christian’s commentsThis sounds like a very good idea. I suggest using slightly wider timebins for the first two options... 2.5ns & 5ns rather than 2ns & 4ns. Ifwe use slow gas, with average drift velocity ~ 40 microns/ns = .04mm/ns,then the maximum drift time in station 2 (~10mm drift) will be about10/.04 = 250ns. This will be difficult to fit into a 256ns time window,but easy to fit into a 320ns time window. The resolution will still bepretty good, since (sigma=bin/root(12)) 5ns/root(12) = 1.44ns, whichcorresponds to ~60 microns at 40 microns/ns. If we use fast gas, withave drift velocity 80-100 microns/ns, we may be able to use 64 2.5nsbins even for Stations 2 & 3 (& still have a contribution to themeasurement error from TDC binning < 100 microns)... If the driftvelocity is 100 microns/ns & we have to use 5ns bins, the TDC binningerror would still be only 500u/root(12) ~ 150 microns.

I'm not sure what the maximum drift time in the station 4 chambers isgoing to be... Ming measured 2.3 microseconds using Ar/C02 (80/20). Ifwe have only 3 options of time bin width, I think the third optionshould give us a time window of about 2.5 usec. 64 bins each 40ns widewould give 2.56usec. That gets my vote.

Ting-Hua Chang’s Comments

Regarding the maximum delay time, assume at t0 the particle hit H1 hodo, the TDC stop goes into the TDC module will be ~t0+1100 ns (using 350ns for 1 layer of V1495), while the signals from chamber will be t0+ TOF(ranging from 0 to 50ns ) + ~100 ns cable + drift time. So the maximum delay time should be increased for ST 1, and very marginal for station 2 & 3. We will need to increase the maximum delay to or provide an time window offset of ~1000 ns in the final version.

Current Design Specification I

Station 1 Station 2 &3

Station 4

Time bin 10 ns 10 ns 40 ns

Width of accepted window

64*10=640 ns 64*10=640 ns(>250 ns)

64*40=2,560 ns

Maximum Delay of shift register

128*10=1,280 ns(>1,100 ns)

128*10=1,280 ns 128*40=4,096 ns

Time resolution of TDC

2.5 ns 2.5 ns 10 ns

Two-hit resolution 10 ns 10 ns 40 ns

Frequency of clock source: 100 MHz

Current Design Specification II

• Width of accepted window: 64 time bins.• Depth of shift register: 128 time bins.• The start time of the accepted window (or the

relative position of the accepted window in the shift register) can be controlled via a register value set by the user. The value is from 0 to 64 with a step of 2.

• For the purpose of zero suppression, we are considering setting up a flag bit in the register if all bits for 64 channels are all ZERO.

Address MapOffset Access Data width Description

0x000 R/W D32 Control and Status Register (CSR)

0x004 R D32 PCB serial number and Revision date code

0x008 R D32 FIFO status register

0x00C R/W D32 Control and Status Register (CSR2)

0x010 W D32 FIFO test mode enable

0x014 W D32 FIFO test mode disable

0x020 W D32 Clear

0x028 W D32 Latch mode enable

0x02C W D32 Latch mode disable

0x050 W D32 Reserved

0x054 W D32 Reserved

0x060 W D32 Reset

0x068 W D32 Generate output pulse

0x100|

0x1FC R/W, BLT D32 128KB FIFO memory space, (32K x 32)

CSR2 0x0c (32 bits)D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Spare Delay Time (Write) Spare

Gate (128 clocks)

Time window (64 clocks)

Delay TimeCSR2

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16X Trig

Y2TrigY1

TrigY0

X TrigY2

TrigY1

TrigY0

X TrigY2

TrigY1

TrigY0

Trigger Timing (Read)

Data structure for one time binD31 D30 D29 D28 D27 D26 D25 D24 … D7 D6 D5 D4 D3 D2 D1 D0X Ch7

Y2Ch7Y1

Ch7Y0

X Ch6Y2

Ch6Y1

Ch6Y0

… X Ch1Y2

Ch1Y1

Ch1Y0

X Ch0Y2

Ch0Y1

Ch0Y0

1st 32-bit data

D31 D30 D29 D28 D27 D26 D25 D24 … D7 D6 D5 D4 D3 D2 D1 D0X Ch15

Y2Ch15Y1

Ch15Y0

X Ch14Y2

Ch14Y1

Ch14Y0

… X Ch9Y2

Ch9Y1

Ch9Y0

X Ch8Y2

Ch8Y1

Ch8Y0

2nd 32-bit data

D31 D30 D29 D28 D27 D26 D25 D24 … D7 D6 D5 D4 D3 D2 D1 D0X Ch55

Y2Ch55Y1

Ch55Y0

X Ch54Y2

Ch54Y1

Ch54Y0

… X Ch49Y2

Ch49Y1

Ch49Y0

X Ch48Y2

Ch48Y1

Ch48Y0

7th 32-bit data

D31 D30 D29 D28 D27 D26 D25 D24 … D7 D6 D5 D4 D3 D2 D1 D0X Ch63

Y2Ch63Y1

Ch63Y0

X Ch62Y2

Ch62Y1

Ch62Y0

… X Ch57Y2

Ch57Y1

Ch57Y0

X Ch56Y2

Ch56Y1

Ch56Y0

8th 32-bit data

…..