Programming Language Interface (PLI)Pedram A. RiahiTest SeminarAugust 11th, 2004

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ContentsPLI HistoryVerilog PLI OverviewVerilog VPI RoutinesCadence VPI EnvironmentMentor Graphics VPI EnvironmentReferences

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PLI History1985 - The PLI was developed by Gateway Design Automation as part of the proprietary Verilog-XL simulator1990 - The PLI standard was released to the public domain along with the Verilog HDL and Verilog SDF standards by Cadence Design System1990 - Open Verilog International (OVI) owned the Verilog HDL, the OVI version of the PLI was called PLI 1.01993 - OVI released PLI 2.0, a completely new interface, intended to replace PLI 1.01993 - OVI submitted Verilog to the IEEE for standardization1995 -The IEEE-1364-1995 Verilog PLI standard was released2001 -The IEEE-1364-2001 Verilog HDL & PLI standard updated with many new language features many new language features

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Verilog PLI OverviewIEEE Std Verilog HDL LRM Clauses 20-27 and Appendices E-GVerilog PLI Generations:Task/Function Routines (TF Routines, tf_)Access Routines (ACC Routines, acc_) Verilog Procedural Interface Routines (VPI Routines, vpi_)

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Verilog PLI OverviewUser-Defined System Tasks and FunctionsNames ($)TypesOverridingUser-Supplied PLI ApplicationsArgumentsInterface MechanismInclude Filesacc_user.hveriuser.hvpi_user.hMemory Restriction

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Verilog VPI RoutinesSystem Tasks and Functionsvpi_register_systf()vlog_startup_routines[]InterfaceCall-backsvpi_register_cb()Access to HDL and Simulation Objectsmodule m, wire w: m1.w, m2.wError HandlingFunction AvailabilityTraversing Expressions

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Verilog VPI RoutinesCall-backsSimulation Call-backsSimulation Action and FeaturesSimulation TimesSimulation EventsStatement Call-backsRemoving Call-backs

Time Queue

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Verilog VPI RoutinesDiagram Key for Objects and Classes

Object Definition

Object Reference

Class Definition

Class Reference

Unnamed Class

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Verilog VPI RoutinesDiagram Key for Traversing Relationships

obj_h = vpi_handle (obj, ref_h);

obj_h = vpi_handle (Tag, ref_h);

obj_h = vpi_handle (obj, NULL);

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Verilog VPI RoutinesDiagram Key for Traversing Relationshipsitr = vpi_iterate (obj, ref_h);while (obj_h = vpi_scan (itr)){ process obj_h}

itr = vpi_iterate (Tag, ref_h);while (obj_h = vpi_scan (itr)){ process obj_h}

itr = vpi_iterate (obj, NULL);while (obj_h = vpi_scan (itr)){ process obj_h}

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Verilog VPI RoutinesDiagram Key for Accessing Properties

PLI_INT32 vect_flag = vpi_get (vpiVector, obj_h);

PLI_INT32 size = vpi_get (vpiSize, obj_h);

PLI_INT8 *name = vpi_get_str (vpiName, obj_h);

Identified Routines

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Verilog VPI RoutinesObject Relationships and Properties

modH = vpi_handle (vpiModule, netH);

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Verilog VPI RoutinesObject Relationships and Properties

vpiHandle net, mod;net = vpiHandle_by_name (top.m1.w, NULL);mod = vpi_handle (vpiModule, net);

vpi_handle (vpiExpr, partH);

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Verilog VPI RoutinesObject Relationships and Properties

PLI_BYTE8 *name = vpi_get_str (vpiFullName, mod);

vpiHandle itr;itr = vpi_iterate(vpiNet, mod);while (net = vpi_scan (itr))vpi_printf(%s\n, vpi_get_str (vpiFullName, net));

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Verilog VPI RoutinesObject Relationships and Properties

void traverseExpr (vpiHandle expr) { vpiHandle subExprI, subExprH; switch (vpi_get (vpiExpr, expr)) { case vpiOperation: subExprI = vpi_iterate (vpiOperand, expr); if (subExprI) while (subExprH = vpi_scan (subExprI)) traverseExpr (subExprH); default: break; }}

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Verilog VPI RoutinesObject Relationships and PropertiesType Properties-> typeint: vpiType

vpi_get (vpiType, H);vpi_get_str (vpiType, H);

File and Line Properties-> locationint: vpiLineNostr: vpiFile

Delays and Values

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Verilog VPI RoutinesVPI Routines for Simulation Related Call-backsvpi_register_cb(): Register a simulation-related call-back vpi_remove_cb(): Remove a simulation-related call-backvpi_get_cb_info(): Get information about a simulation-related call-back

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Verilog VPI RoutinesVPI Routines for System Task/Function Call-backsvpi_register_systf(): Register a system task/function call-back vpi_get_systf_info(): Get information about a system task/function call-back

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Verilog VPI RoutinesVPI Routines for Traversing Verilog HDL Hierarchyvpi_handle():Obtain a handle for an object with a one-to-one relationshipvpi_iterate(), vpi_scan():Obtain handles for objects in a one-to-many relationshipvpi_handle_multi():Obtain a handle for an object in a many-to-one relationship

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Verilog VPI RoutinesVPI Routines for Accessing Properties of Objectsvpi_get():Get the value of objects with types of int or bool vpi_get_str():Get the value of objects with types of string

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Verilog VPI RoutinesVPI Routines for Accessing Objects from Propertiesvpi_handle_by_name():Obtain a handle for a named object vpi_handle_by_index():Obtain a handle for an indexed object vpi_handle_by_multi_index():Obtain a handle to a word or bit in an array

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Verilog VPI RoutinesVPI Routines for Delay Processingvpi_get_delays():Retrieve delays or timing limits of an object vpi_put_delays():Write delays or timing limits to an object

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Verilog VPI RoutinesVPI Routines for Logic and Strength Value Processingvpi_get_value():Retrieve logic value or strength value of an object vpi_put_value():Write logic value or strength value to an object

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Verilog VPI RoutinesVPI Routines for Simulation Time Processingvpi_get_time():Find the current simulation time or the scheduled time of future events

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Verilog VPI RoutinesVPI Routines for Miscellaneous Utilitiesvpi_printf()vpi_vprintf()vpi_flush()vpi_mcd_open()vpi_mcd_close()vpi_mcd_printf()vpi_mcd_vprintf()vpi_mcd_flush()vpi_mcd_name()vpi_get_vlog_info()vpi_compare_objects()vpi_chk_error()vpi_free_object()vpi_put_data()vpi_get_data()vpi_put_userdata()vpi_get_userdata()vpi_sim_control()

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Verilog VPI RoutinesModule Data Model

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Verilog VPI RoutinesNet Data Model

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Verilog VPI RoutinesReg Data Model

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Verilog VPI RoutinesCadence PLI Environment

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Verilog VPI RoutinesCadence PLI EnvironmentCreating a C Function

#include #include vpi_user.hint hello_task () {vpi_printf (Hello from a new VPI task \n);}

Creating a C++ Function

extern C void ncmain (int, char **);main(argc, argv)int argc;char* argv[];{ ncmain(argc, argv); }

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Verilog VPI RoutinesCadence PLI EnvironmentAssociating C Function with a new System Task

void register_my_systfs () {s_vpi_systf_data task_data_s;p_vpi_systf_data task_data_p = &task_data_s;task_data_p->type = vpiSysTask;task_data_p->tfname = $hello ;task_data_p->calltf = (int(*)()) hello_task;task_data_p->compiletf = NULL;vpi_register_systf (task_data_p); }

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Verilog VPI RoutinesCadence PLI EnvironmentRegistering Users New System Task

/* vpi_user.c */#include vpi_user.h#include vpi_user_cds.hvoid (*vlog_startup_routines[]) () = {register_my_systfs, 0};

Invoking Users System Task

module top;Initial begin $hello; endendmodule

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Verilog VPI RoutinesCadence PLI EnvironmentCompiling C Files (vconfig)Static/Dynamic

cc -KPIC -c ~/vpi_user.c -I/include cc -KPIC -c ~/hello.c -I/include ld -G vpi_user.o hello.o -o libvpi.so executable file Compiling and Simulating Verilog File

setenv LD_LIBRARY_PATH \ ~/:$LD_LIBRARY_PATHncelab access+rwc worklib.top:vncverilog +ncaccess+rwc +plinowarn hello.v

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Verilog VPI RoutinesMentor Graphics PLI EnvironmentCompiling C Files

cc -c ~/vpi_user.c -I/include cc -c ~/hello.c -I/include ld -G vpi_user.o hello.o -o vpi_lib.so Compiling and Simulating Verilog File (modelsim.ini)

vlib workvlog hello.vvsim -c -pli vpi_lib.so top

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ReferencesCadence Design Systems, Inc., VPI User Guide and Reference, Product Version 3.2, Dec. 2000.Cadence Design Systems, Inc., NC-Verilog Simulator Help, Product Version 3.2, Dec. 2000.Cadence Design Systems, Inc., Verilog-XL User Guide and Reference, Product Version 2.8, Aug. 1999.Mentor Graphics, ModelSim SE User's Manual, Version 5.7a, Jan. 2003Stuart Sutherland, The Verilog PLI Handbook, Kluwer Academic Publishers, 2002.Swapnajit Mittra, Principles of Verilog PLI, Kluwer Academic Publishers, 1999.

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