lab_wk1.pdf

8/14/2019 lab_wk1.pdf

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Techniques for Digital Systems Lab

Introduction

Tajana Simunic Rosing

1

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Welcome to CSE 140L!• Course time: W 2-2:50pm, WLH 2205• -

,

• Instructor: Tajana Simunic Rosing• Email: [email protected]; please put CSE140L in the subject line• Ph. 858 534-4868•

- ,• Instructor ’s Assistant: Sheila Manalo

– Email: [email protected]

– Phone: (858) 534-8873•

– Email: [email protected]

– Office hours: M 2-3pm; W 10-11am in CSE 3219• TA: Chun Chen Liu

–

. – Office hours: T 10am-12pm in CSE 3219

• Class Website:

– http://www.cse.ucsd.edu/classes/sp08/cse140L/•

2

. .

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Course Descri tion• Prerequisites:

– CSE 20 or Math 15A, and CSE 30.

– CSE 140 must be taken concurrently

• Objective: –

hands-on experience in a lab

• Grading – Labs 4 : 70% • We have 15 Xilinx platforms with PCs – organize in teams of two• Schedule for lab access; need to schedule a demo to TA by lab due date• Go to Robin Knox [[email protected]] office in CSE 2248 to program

– Monday-Thursday 10-12:30 and 2:00-4:00

– Final exam: 30% – Regrade requests: turn in a written request at the end of the class

3

where your work is returned

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Textbook and Recommended Readin s• Required textbook:

–

R. Katz & G. Borriello

• Recommended textbook:

– Digital Design by F. Vahid

• Lecture slides are derived from the

4

slides designed for both books

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Hardware we will use• Freely available in CSE 3219 lab:

– -

(XUPV2P)http://www.xilinx.com/univ/xupv2p.html

– .

You can program boards in the lab only!

– You can download on your own PC Webpack

programming the board

www.xilinx.com/ise/logic_design_prod/webpack.htm

• Alternative: Altera Board you can buy in thebookstore for $100

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Outline• Introduction to Xilinx board & tools

• Transistors

– How they work – How to build basic gates out of transistors

– How to evaluate dela

• Pass gates

• Muxes

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Basic FPGA

Architecture

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Overview• All Xilinx FPGAs contain the same basic

– Slices grouped into configurable logic blocks - CLBs• Contain combinatorial logic and register resources

– Input/Output Blocks - IOBs

• Interface between the FPGA and the outside world – rogramma e n erconnec

– Other resources•

• Memory

• Multipliers

• o a c oc u ers

• Boundary scan logic

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Virtex-II Architecture

I/O Blocks (IOBs)I/O Blocks (IOBs)Block SelectRAM™Block SelectRAM™

resourceresource

Dedicated

multipliers

Dedicated

multipliers

interconnect

interconnect

on gura e

Logic Blocks

(CLBs)

on gura e

Logic Blocks

(CLBs)

Clock Management

DCMs BUFGMUXes

Clock Management

DCMs BUFGMUXes

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Slices and CLBs• Each Virtex™-II CLB

conta ns our s ces

– Local routing provides

BUFT

BUF T

Slice S3

in the same CLB, and it

provides routing to SwitchMatrix

Slice S2

SHIFT

ne g or ng s

– A switch matrix providesSlice S1

to general routingresources CIN

Slice S0 Local Routing

CIN

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Sim lified Slice Structure• Each slice has four

Slice 0

outputs – Two registered outputs,

two non-re istered out uts

LUTLUT CarryCarry D Q

CE

PRE

CLR

– Two BUFTs associatedwith each CLB, accessibleby all 16 CLB outputs

PRE

• Carry logic runsvertically,

QCE

CLR

up only – Two independent

Basic Architecture 11

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Detailed Slice Structure• The next few slides

features – LUTs

– MUXF5, MUXF6,MUXF7, MUXF8

(only the F5 andF6 MUX are shownin this diagram)

– Carry Logic

– MULT_ANDs – Sequential Elements


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Look-U Tables• Combinatorial logic is stored in Look-Up

– Also called Function Generators (FGs)

– Capacity is limited by the number of inputs,

0 0 0 0 0

0 0 0 1 0

not by the complexity

• Delay through the LUT is constant0 0 1 0 0

0 0 1 1 1

Combinatorial Logic

A

0 1 0 1 1

. . .

B

CD

Z 1 1 0 0 0

1 1 0 1 0

Basic Architecture 13 1 1 1 1 1

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Connectin Look-U Tables

F 5

F 8CLB

Slice S3

MUXF7 outputs (from theCLB above or below)

F 5

F 6

Slice S2

com nes s ces

S2 and S3

Slice S1 F 5

F 7

MUXF7 combines the two

MUXF6 outputs

Slice S0 F 5

F 6 MUXF6 combines slices S0 and S1

MUXF5 combines LUTs in each slice


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Fast Carr Lo ic

• Sim le fast and COUT COUT

complete arithmeticLogic

– Dedicated XOR ate

To S0 of the

next CLB

To CIN of S2 of the next

CLB

SLICES3

for single-level sumcompletion

– Uses dedicated

Chain

SLICE

COUTCIN

rou ng resources

– All synthesis toolscan infer carry logic

SLICES1

SecondCOUT

CIN

SLICES0

CarryChain


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Flexible Se uential Elements

FDRSE1

• Either flip-flops or latches

DCE

S

R

Q

_

• wo n eac s ce; e g n

each CLB

•

DCE

PRE Q

FDCPE

from an independent CLB

inputCLR

LDCPE

• eparate set an resetcontrols – Can be s nchronous or

D

CE

PRE

CLR

Q

G

asynchronous

• All controls are shared within

– Control signals can be invertedlocally within a slice

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MULT_AND Gate• Highly efficient multiply and add implementation

– Earlier FPGA architectures re uire two LUTs er bit to erform themultiplication and addition

– The MULT_AND gate enables an area reduction by performingthe

LUT

multiply and the add in one LUT per bit

CODI CI

S_

CY_XOR

MULT_AND

LUT

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IOB Element• Input path

– Two DDR re isters

DDR: double data rate• Output path Reg DDR MUX

OCK1 Re

Input

– wo reg s ers

– Two 3-state enable

DDR registers

Reg3-stateOCK2

Reg

ICK1

ICK2

• Separate clocks andclock enables for I and O Reg DDR MUX

OCK1

are shared RegOutputOCK2


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Distributed SelectRAM Resources• 1 LUT = 16 bits RAM

RAM16X1S

• Asynchronous read – Accompanying flip-flops

O

D

WE

WCLKA0

A1

A2

LUTLUT

can e use o crea esynchronous read

• RAM and ROM are

RAM32X1S

D

WE

RAM16X1D

D

WE

n a ze ur ngconfiguration – Data can be written to RAM

OA0

A1

A2

A3

A4

SPOA0

A1

A2

A3

DPRA0 DPO

DPRA1

ce

LUT

a er con gura on• Emulated dual-port RAM

– One read/write port

DPRA2

DPRA3

LUT

– One read-only port

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Block SelectRAM Resources• Up to 3.5 Mb of RAM in 18-

– Synchronous read and write

• True dual- ort memor

DIA

DIPA

ADDRA

WEA

-

– Each port has synchronousread and write capability

–

ENA

SSRA

CLKA

DOA

DOPA

• Supports initial values

• Synchronous reset on

DIB

DIPB

WEB

ADDRB

ENB

output latches• Supports parity bits

CLKB DOPB

DOB

–bits

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Dedicated Multi lier Blocks• 18-bit twos complement signed operation

•

functions• Multipliers are physically located next to block

SelectRAM™ memory

Data_A18 bits

18 x 18Multiplier 18 x 18Multiplier

Output(36 bits)

8 x 8 signed

12 x 12 signed

Data_B(18 bits)

18 x 18 signed

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Virtex-II Pro Features• 0.13 micron process

• ™ -

blocks – Serializer and deserializer (SERDES)

– re anne , ga erne , , n n an comp antransceivers, and others

– 8-, 16-, and 32-bit selectable FPGA interface – 8B/10B encoder and decoder

• PowerPC™ RISC processor blocks – - -

– Low power consumption: 0.9mW/MHz

– IBM CoreConnect bus architecture support


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ISE Proect Navi ator

•

Xilinx design flow – Access to synthesis

• Including third-party synthesistools

– Implement yourdesign with a simpledouble-click

• Fine-tune witheasy-to-accesssoftware options

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Xilinx Desi n Flow

Plan &

Budget

Simulation

Implement

Schematic

Translate

Map

to create netlistSimulation

Place & Route

CreateBIT File

Attain TimingClosure

TimingSimulation

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Download & Run!!• Once a design is implemented, you must create a file that

the FPGA can understand

– This file is called a bitstream: a BIT file (.bit extension)• The BIT file can be downloaded directly into the FPGA, or

e e can e conver e n o a e, w cstores the programming information

• Execute!!! – You will be responsible for a demo to TA

– Turn in a report with answers to questions asked, schematics,truth tables, equations etc.

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Combinational circuit building blocks: ,

Tajana Simunic Rosing

27

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The CMOS Circuit

• CMOS circuit – Consists of N and PMOS transistors

– Both N and PMOS operate similar to basic switches

A positive ...attracts electrons here, 01

nMOS

gate

...

between source and drain

into aconductor.

does notconducts

source drainIC packag

1

pMOS

0

(a) IC

does notconduct

conductsSilicon -- not quite a conductor or insulator:

28

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N-MOS Tutorial – channel formation

• The Semiconductor-Oxide-Metal Combination in the Gate is effectivelya Parallel Plate Capacitor

gate

nMOS

• Vgs = 0 -> lots of positive charge in p-type material, no current

29

• Source: http://www.netsoc.tcd.ie/~mcgettrs/hvmenu/tutorials/TOCcmostran.htm

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N-MOS Tutorial –channel formation cont.

• Vgs >0 -> + charge on the gate, - charge attracted to the oxide, +charge chased away from the oxide

• Vgs=Vt -> channel of negative charge forms under the oxide; the oxideis depleted of + charge; Vt = threshold voltage

30

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N-MOS Tutorial –channel formation cont.

• Vgs>Vt -> negative charge carriers form under the oxide; free electronsare thermally generated and form a conduction channel through whichcurren can ow

• Vgs>Vt & Vds = 0 -> channel present, but no current flows

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N-MOS Tutorial: Current flow

• Vds >= Vgs-Vt -> channel pinched off, saturated; constantcurrent flows from drain to source – Cox : oxide capacitance = εox / tox (oxide permittivity εox and thickness tox);

μ: mobility of charge carriers; W/L gate width and length

33

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How about P-MOS?

• Everything is the same, but polarities of voltages reverse.Mobilit is 2x smaller, so 2x less current is enerated ifall other parameters are kept constant – e.g. PMOS turns on when Vgs < Vt and both are <0

gate

pMOS

34

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Resistance

• Resistivity – Function of:

• resistivity r, thickness t : defined by technology

• Width W, length L: defined by designer

–

• R = r’ L/W

• L is usually minimum; change only W

35Source: Prof. Subhashish Mitra

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Ca acitance & Timin estimates

• Capacitor – Stores char e Q = C V ca acitance C volta e V

– Current: dQ/dt = C dV/dt

• Timing estimate – = = trans = trans

• Delay: time to go from 50% to 50% of waveform


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Char e/dischar e in CMOS

• Calculate on resistance

•

• Get RC delay & use it as an estimate of circuit delay – Vout = Vdd ( 1- e-t/RpC)


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Inverter delay

• Delay: estimate using RC time constants

Fx

NOT

x

0

1

F

1

0

1

F = x’

1 11 1

0 0 00 0

1

380

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Di ital lo ic abstraction

• Real transistors: voltage at the gate controlsthe current between source and drain

• Too complex! Simplify!

• Guarantee that voltage always falls within tworegions: logic 0 and logic 1

• Level restore

Noise• Great to filter out noise (noise margins)

• Use RC time constants to approximate delaySource: Prof. Subhashish Mitra

B i CMOS t

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Basic CMOS gates

• e ay: es ma e us ng me cons an s

Fxx

F

NORNOT

Fx

NAND 1

x y

1

y

x

0

0

1

y

0

1

0

F

1

1

1

x

0

0

1

y

0

1

0

F

1

0

0

x

0

1

F

1

0

y

F

y

x

x

x

y

F

1 1 01 1 00

01

F = x’

0

40

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CMOS Example

• The rules: – NMOS connects to GND PMOS to ower su l Vdd

– Duality of NMOS and PMOS

– Rp ~ 2 Rn => PMOS in series is much slower than NMOS in series

’• mp emen us ng : =

41

P t i t

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Pass transistor

• Connects X & Y when A=1, else X & Y disconnected – A_b = not(A)

42

Fig source: Prof. Subhashish Mitra

M

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Mux

• Selects input to connect to Y –

– selB == 1: connects B to Y

43

Fig source: Prof. Subhashish Mitra

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lab_wk1.pdf

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