laboratory manual cadence

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LABORATORYMANUAL

TSTE80 ATIC, 2007

Erik Sll

Robert Hgglund

K Ola Andersson

Niklas U Andersson

J Jacob Wikner

M1 M2

M3 M4

M5

Vin+Vin-

Vout

Vbias1

CL

M6M7

M8 M9

M10 M11

Vbias0 Vbias2

Vbias2 M12 M13

M14 M15


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TSTE80 ATIC Introduction Page 3

ES, ISY, Linkpings universitet

1 Introduction

The purpose of these laboratories is to get an insight in the design procedure of analog cir-cuit as well as using a circuit simulator in order to estimate the behavior of a few analogcircuits. The tools used in the laboratory is Cadence and the transistor-level simulatorSpectre. An introduction on how to run these tools are given in this manual as well.

For some of the exercises you will find a sign (as shown to the right). This impliesthat you should do some preparatory exercises that are found in the ExerciseManual. This is important due to a number of reasons, since it will...

reduce the time for you in front of the computer screen

help you understand some of the issues much better

... and therefore read this note:

Although it may be somewhat frustrating, some of the specifications in this laboratoryexercise cannotbe met. Unfortunately, this is the only way to see how far you can pushthe limits of a process, and to understand the basic limitations for the analog buildingblocks. If a specification cannot be met, you should explain why and then relax the speci-fication, redesign and try to meet your new specification.7

2 Initiating your LINUX environment

In this laboratory we will use a tool called Cadence. The Cadence program package con-tains many application for example transistor-level simulation, layout, verification pro-

grams and so on. Here, we only consider the circuit-level simulation. When a circuit iscreated as a graphical netlist different types of transistor-level simulators can be used forexample HSPICE, Spectre and SpectreS. The transistor-level simulators offers severalanalysis such as DC, AC, transient, noise, etc. The speed and accuracy of the simulationsalso varies between the simulators. In this laboratory the Spectre simulator is used.

We will know setup the Cadence environment for the AMS 0.35um CMOS process. First,create the following directories in your home directory using themkdircommand.

cadence/CSI.AMS.035/

Load the modules required by Cadence and the AMS 0.35um CMOS process using the com-mands below. Make sure that no other cadence or process modules are loaded.If

there are other loaded modules you must unload them before entering the commandsbelow.

module load cadence

module load ams

Then go to the CSI.AMS.035 directory and initialize Cadence with the following command.

ams_cds -tech c35b4 -mode fb &

This command will also start Cadence.

PressOKin the window asking about process option.

It is requiredthat the student isprepared when arriving at the lab.


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TSTE80 ATIC Getting started with Cadence Page 4


For the lab, you may need additional tools like Matlab and Mathematica for computationsof for example the small-signal transfer function. Mathematica is a powerful tool when youwant to derive an analytical expression to a given circuit topology.

You should now copy the netlist file to you lab directory. It is found at

cp -R /proj/tde/TSTE80/Lab/ANTIKlab ~/cadence/CSI.AMS.035/cp -R /proj/tde/TSTE80/Lab/.artist_states $HOME

In the library manager choose the menu alternativeEdit->Library Pathand add thelibraryANTIKlab with the path$HOME/cadence/CSI.AMS.035/ANTIKlab. Save ascds.liband exit theLibrary Path Editor. A new library will now be visible in theLibrary Manager.

Starting Cadence the next time

The next time you start Cadence you just have to go to the directory

cadence/CSI.AMS.035/

and then load the required modules and use the ams_cds-command to start Cadence,according to below. It could therefore be practical to save these commands in a text-file.You can then copy the commands from that file to the terminal window the next time youstart Cadence. Also make sure that no other cadence modules or technology modules areloaded. If this is the case you have to unload them before entering the commands below.

3 Getting started with Cadence

When the program is started there will be two windows visible. The first one is theicfbwindow where information about what you are doing, errors and warning messages willbe displayed. The second one is thelibrary managerfrom where you can select whichcircuit you would like to work with. When you start the Cadence program the library man-ager will display several libraries. The only libraries used in these exercises arePRIMLIBandanalogLib. InPRIMLIBwe have process specific components like transistors, resis-tors and capacitors and inanalogLib we have ideal components like voltage sources, cur-rent sources, capacitors, etc.

Creating a library

When you start a project you need to create a new directory that is linked to a specific pro-cess. SelectNew>Library in the Filemenu. Enter a name for the new directory and pressOK. A new dialog window will appear where you should select a technology to attach to yourlibrary. SelectAttach to an existing techfile and pressOK. ChooseTechnologyLibrarytoTECH_C35B4and pressOK. Now you have a new library where you can createyour design in.

Creating a cell view

Select the directory where you like to have your cell view. SelectNew->Cell Viewin theFilemenu. Enter aCell Nameand choose aTool. The tools we are using here are:

Composer-Schematicto design a circuit in the schematics mode.

module load cadence

module load ams

ams_cds -tech c35b4 -mode fb &


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TSTE80 ATIC Getting started with Cadence Page 5


Composer-Symbolto create symbols for a schematic to be used in hierarchical designs.

The tool you have selected will then be loaded and it is possible to start designing your cir-cuit.

Schematic

The schematic composer is a graphical interface to design circuits. From the schematicview transistor-level simulations can be performed to evaluate the performance of thesized circuit. The simulator uses accurate device models. No wire capacitors or resistorsare used in this model, since it depends of the layout. Post-layout simulations can also beperformed to further include effects of parasitic elements, and thereby come even closertowards a real implementation.

Fetching an element to be used in the schematic

Elements such as voltage sources, transistors, and capacitors are predefined buildingblocks that can be inserted in the schematic by either the menu alternative

Add>instance or by the short cuti. A subwindow will appear where you can add a com-

ponent by specifying the library, cell and view. The view should be symbol. You can eitheradd a process defined cell for example the ones listed in Table 1, or a component of yourown.

When a component is chosen to be placed in the schematic, by either writing the names of

the libraries and the cell view or by using thebrowsebutton, the properties of the selected

Component Library Cell View

Vdd analogLib vdd symbol

Ground analogLib gnd symbol

DC voltage source analogLib vdc symbol

DC current source analogLib idc symbol

Sinusoidal voltage source analogLib vsin symbol

Sinusoidal current source analogLib isin symbol

Pulse voltage source analogLib vpulse symbol

Pulse current source analogLib ipulse symbol

Voltage controlled voltage source analogLib vcvs symbol

Ideal resistor analogLib res symbol

Ideal capacitor analogLib cap symbol

Non ideal resistor PRIMLIB rpoly symbol

Non ideal capacitor PRIMLIB cpoly symbol

NMOS transistor PRIMLIB nmos4 symbol

PMOS transistor PRIMLIB pmos4 symbol

Table 1: Predefined components in Cadence and for the used process.


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TSTE80 ATIC Simulating a circuit schematic Page 6


components will appear further down in theAdd instancewindow. For example thewidth and length of a transistor can be defined or the voltage of a voltage source.

Defining design variables

During the circuit designing procedure it is common that, for example, transistor widths,bias currents, and voltage values must be adjusted to ensure that all transistors are oper-

ating in their desired operation region and to meet a certain specification. In this case, itis easier to define variables for parameters that you frequently will adjust. Defining vari-ables is just to write a parameter name in the desired field of a component, for example thewidth of a specific transistor is set to the parameterW1.

4 Simulating a circuit schematic

The simulations are controlled from the Cadence Analog Design Environment (CADE),which is started using the menu alternativeTools->Analog Environmentfrom the

Virtuoso Schematic Editingwindow containing the schematic to simulate.

If you do not change the project directory to /tmp/sim you will have to restart Cadenceevery time you forget to save the schematic before starting the simulation.

As stated earlier, the simulation environment can use several different types of simula-tors. The functionality, i.e., the types of analysis method, the speed, and the approximationmethods when solving the system of differential equations, differs between the simulators.Analysis methods that can be used are, for example, DC analysis, small-signal analysis,

transient analysis, different type of noise analysis, distortion analysis and sensitivityanalysis. In the laboratories we will use the three most commonly used analysis methodsnamely DC, AC and transient analysis

The simulation setup can be divided into three parts namely the analysis setup, the setupof the output signals, and adding the design variables of the simulation.

Analysis setup

DC

The analysis part is like the ones in Spice, you can either check the DC behavior of the cir-cuit and check that your components are operating correctly, i.e., all transistors are oper-

ating in the correct operation region and so on. Here you can for example sweep aparameter like the bias current in your amplifier so that all transistors are operating inthe saturation region.

AC

The properties of the circuit with respect to a small change in the DC operating point canbe evaluated by linearizing the transistors around the DC operation point. This lineariza-tion as well as the simulation of the linearized circuit is performed in the AC analysis.

Transient

The transient analysis is used when the time response of a circuit is of interest. This anal-ysis method takes into account clipping of the circuit.

Parametric analysis

! When the CADE has started change theProject Directoryto/tmp/simby the menu alternativeSetup->Simulator/Directory/Host... inCADE and pressOK.


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TSTE80 ATIC Results Page 7


Parametric analysis are used when two or more parameters are to be swept independentlyof each other. For example, the current into a simple current mirror and the width of theoutput transistor. In this case sweep the current in the DC analysis and add a parametricsweep using the menu alternative in the CADE.

Tools->Parametric Analysis

Enter the name of the variable for the output transistor width into the fieldVariableName. Add the ranges of the sweep and start the analysis by selecting

Analysis->Start

Defining output signals

The outputs of the simulation can, for example, be the output voltage from an amplifier,the current through a current mirror or a mathematically defined function to calculate theunity-gain frequency of a circuit. These outputs can be selected from the schematic byusing the menu command Output->To Be Plotted->Select On Schematic and thenselect the output to be plotted each time you do a simulation. Note that by selecting a wire,

the node voltage for that node will be plotted, by selecting a node the current through thatnode will be plotted.

Define design variables

The variables defined in the schematic view can be imported into the simulation environ-ment. This is done by using the menu alternative

Variables->Copy from Cellview

All the variables will now appear in the variable field in the Cadence Analog Design Envi-ronment window. To assign a value to one of the parameters just double click on the vari-able and enter the desired value.

5 Results

The DC operation conditions of a circuit are computed when a DC simulation has been per-formed. If you like to display the result directly in the schematic use the menu alternative

Result->Annotate->

If you like to display a complete list of the operation condition use

Result->Print->

Different alternative in the submenu of the print and annotate menu are listed below witha short explanation.

6 The calculator

The calculator can be used to, for example, add, subtract, multiply, or divide two waves,take the discrete fourier transform or efficiently compute the DC gain, unity-gain fre-

Menu alternative Description

DC node voltage The voltage in a specific node or all

nodes.

DC operating point Operating point of a device ( , ,

, , operation region,...).

gm gdscgs id


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TSTE80 ATIC Usable shortcuts in the schematic view Page 8


quency, phase margin and slew rate of a circuit. It is very handy when you are trying toincrease the performance of a circuit.

Plotting the derivative of a wave can be done in the following way. The calculator can bestarted from the toolbar in theWaveform Window. Press theWavebutton and select awave in theWaveform Window. Click on the Special Functions selection box and choose

thederivcommand. To plot the derivative just select toPlotbutton.

Commands to use

7 Usable shortcuts in the schematic view

There are many shortcuts in the program to speed up the design process of a circuit. Someof the most useful are listed below. Together with commands such as move and copy a dou-ble click at the middle mouse button will make it possible to rotate and flip as well as cop-ing an object several times.

Command Description

phase Computes the phase of the output.

phaseMargin Computed the phase margin of the cir-

cuit. (lookout for a 180 degrees phase

shift and mag or db commands)

cross Returns the x-value when the waveformreaches a certain y-value.

mag To display the magnitude response of the

wave.

dB The quantity expressed in decibel.

value Returns the y-value for a certain x-value

Shortcut Description

B Return from hierarchy

descendent

c Copy. Press c then choose

object to move

delete key Delete

E Descend in the hierarchy

escape End last command

f Zoom out to full view

i Insert component

l (small L) Add a label to a wire

m Move an object


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TSTE80 ATIC An example circuit Page 9


8 An example circuit

The task is to design a common source amplifier to be used in an operational amplifier.First we start by drawing the circuit in the schematic composer. The design parameterswill be defined as variables. To use the common source circuit in a hierarchical mannerwhen implementing the operational amplifier we like to have a symbol for the circuit. Fur-ther, a test bench for the common source circuit must be designed to evaluate the perfor-

mance of the circuit.

The first thing to do is to create a library and a schematic cellview in the library manager.A good name for the library islab1 and for the schematic cellview use the nameCommon_source. How to create the cellview and the library was shown in Section 3.

Drawing the schematic

When you created the cellview an empty window will appear calledVirtuoso SchematicEditing. In this window we will create the circuit shown in Figure 1.

Start by inserting the transistors by pressing the shortcut for insert instanceiand thenchoose the NMOS transistor from the libraryPRIMLIB, cellnmos4, and viewsymbol

which from now on will be written asPRIMLIB/nmos4.

The add instancewindow will now be updated and more fields will appear. In theWidthandWidth Stripefield insert the variable win.In theLengthfield add the variable L.The NMOS transistor can now be placed in the schematic window.

Continue with the PMOS transistors from the libraryPRIMLIB/pmos4and the currentsource from libraryanalogLib/idcdo not forget to add variable names as in Figure 1. Ifyou would like to change the properties of the components in the schematic, click on thecomponent and pressq.

Connect the components by using wires. The shortcut w can be handy. Do not forget to con-nect the bulks of each transistor to the correct supply voltage.

p Add a pin (needed only for

hierarchical objects)

q Properties of an object

r Rotate an object

u Undo

w Add a wire

X Save the cellview

z Zoom in a box

F1 Help

F6 Redraw

8 Zoom out9 Zoom in


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The last step is to addpins.This is done by the shortcutp. A new window will appearand you can add the pin names and then place them in the schematic. Use inputOutputpins.

Your schematic should look like the one in Figure 1. The last step is to save the schematicby pressingX (shift+x). If there are any errors in the schematic then a dialog box will

appear and there will be some crosses that are flashing on the schematic. An explanationto the errors will be shown in theicfbwindow. Correct the errors and warnings and savethe schematic. The schematic is finished.

Creating a symbol for the circuit

The next step is to create a symbol of your circuit so that it can be used several times in ahigher level of the hierarchy. This can be done by the menu alternative

Design->Create Cellview->From Cellview

A dialog box will appear. Convince yourself that you are creating a symbol to the correctschematic, then pressOK. A new dialog box namedSymbol Generation Options willappear. Here you define where to place your pins on the symbol. Choose for example

A symbol appears which consists of a green rectangle that will be visible when used in aschematic view, a red rectangle surrounding the green one which is the selection box of thecircuit, and some solid red squares, pins. In this view you can change the appearance of it.For example, it can be changed to the one shown in Figure 2. A new shape can be drawnthrough the menu alternative

Add->Shape

When the symbol is ready and you do not have the large red rectangle in the symbol usedthe command.

Add->Selection Box

Left Vin

Right Vout

Top AVDD

Bottom AGND

Figure 1: The common source amplifier with an NMOS transistor as input device.


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and then select to add it automatically. The symbol must be checked and saved by themenu alternative

Design->Check and Save

Setting up the test bench

The last part is to setup the test bench of the common source circuit. The test bench shouldbe able to evaluate the small-signal gain from the input to the output, the slew rate of thecircuit and the DC operation region of the transistors. This can be done by creating a newschematic cellview calledCommon_source_Testbench in thelab1library. The testbench is shown in Figure 3.

The leftmost circuit is used to define the voltage between and . The parts for thisstructure are analogLib/vdd,analogLib/gndandanalogLib/vdc. In the vdc symbolset the parameterDC voltageto 3.3V which is used in this example. Leave the otherfields in the vdc symbol empty.

A voltage source is connected at the input, it is found in analogLib/vpulse enter the fol-lowing parameters into the component properties.

Parameter Value Explanation

AC magnitude 1 V Using 1 V gives the transfer function at the output.

AC phase 0 The phase of the AC sinusoide.

DC voltage Vindc The DC input voltage to the common source circuit.

Voltage 1 3.3 V Start voltage for the pulse in the transient analysis.

Voltage 2 0 V Second voltage for the pulse in the transient analysis.

Figure 2: The symbol of a common source amplifier.

Selection box

Pin

Figure 3: The test bench of the common source amplifier.

Vdd gn d


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The common source stage can be found in the librarylab1/Common_sourceno parame-ters can be set to this component. At the output of the gain stage we have the capacitorwhich is found inanalogLib/capadd the variableCLas the capacitance value.

Add labels to the input and output wires by using the shortcutl(lower-case L).

Save the test bench (shift+x).

Simulation of the common source amplifier

To start the simulation environment use the menu alternativeTools->Analog Envi-ronment from theVirtuoso Schematic Editing window containing theCommon_source_Testbench. A new window calledCadence Analog Design Envi-ronment (CADE) will appear.

In this window we first get the design variables from the schematic by the commandVariables->Copy From Cellview. Set the variables to the following values

Continue to add the output that you like to have from the simulation. This is done by thecommandOutputs->To Be Plotted->Select On Schematic. Select the output nodeand end the selection by pressingescape. If you are selecting a wire the voltage of thatwire will be displayed, the current can be displayed by choosing a node.

The last part is to choose the analysis types to be used by the menu alternative

Analysis->Choose...

In this case we would like to have a DC analysis. Check thedcanalysis button in theappearing window andSave DC Operating Point. In this case we do not like to haveany type of sweep so click on theapplybutton.

Delay time 0.1n s Delay from start of simulation.

Rise time 1p s Rise time from voltage 1 to voltage 2.

Fall time 1p s Fall time from voltage 2 to voltage 1.

Pulse width 10u The width of the pulse (time it will be 0 V)

Period 20u Time between repetition of the sequence.

! Remember to change theProject Directoryto/tmp/simby theSetup->Simulator/Directory/Host...menu in CADE.

Variable Value Unit

win 100 M

wbias 100 M

Vindc 0.65 V

L 0.7 M

Ibias 126 A

CL 10p F


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TSTE80 ATIC Transistor circuit for simulation Page 13


To compute the small-signal transfer function an AC analysis must be performed. Checkthe ac analysis button and since we like to do a frequency sweep we just enter the startfrequency for example 1 and the stop frequency at 500M and then clickApply.

The last analysis method is the transient analysis. Select thetrananalysis and set thestop time to 10ns.

The definition of the simulation is now complete. The simulation is started by clicking onthe traffic light with green light. Possible errors will be shown in theicfbwindow and inaspectre.outwindow. One source of errors is that you havent saved the schematic.

The following performance parameters is achieved with all transistors operating in thesaturation region.

What will happen with the bandwidth and the slew rate if the output capacitance, CL, isincreased? Perform an analysis by hand and compare the results with simulations.

9 Transistor circuit for simulation

Transistor models

In this lab a 0.35um CMOS process from Austria MicroSystems (AMS) is used. The tran-

sistors are characterized by a large number of parameters that the simulator uses.

Common-source amplifier with passive load

Consider the circuit in Figure 4 (a). A resistor is connected to the drain of the NMOS tran-sistor. At the input we have to apply a voltage source. In the circuit, we have four nodes;in,out,ground, andvdd.

Initiate the tools

Close all schematics you have created. Open the fileANTIKlab->firstsimulation->schematicfrom theLibrary Manager. Start the

Performance parameters Value

DC gain 43.6 dB

Unity-gain frequency 32 MHz

Slew rate 14.4 V/us

Figure 4: Transistor view of single-stage common-source amplifier stage.

R

M1

Vout

Vin


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TSTE80 ATIC Transistor circuit for simulation Page 14


Analog Environment from theToolsmenu. Load the statefirst-setupfrom theSession->Load Statein theCadence Analog Design Environment, CADE, win-dow.

Try to understand how to set the analysis types, the variables and the outputs.

Run the simulator by pressing the green traffic light. Check that there are no errors orwarnings inicfbwindow.

The output current from the transistor is a highly nonlinear function with respect to theapplied voltages on source, gate, drain, and bulk. Hence, we have to be careful with theoperating points of the transistors. The same argument holds since the gain of the transis-tor can be high, hence a small shift in the DC operating point may force the transistor outof its wanted operating region. Therefore, we always run careful DC analyses first.

Secondly, although we only have one transistor, you will discover that a large number ofparameters that can be changed in order to get a correct DC operating point for the tran-sistor. We have the resistance, the input DC voltage, the transistor channel width and

length, etc. Mostly, we will fix the transistor length and the input and output voltages aregiven by a specification. Then the transistor width is the first parameter that should bevaried.

The third, note that when you change a parameter, you do not only change the DC voltage,you also change the gain of the circuit, bandwidth, etc. There is a delicate relation betweena large number of factors.

The input DC voltage is 1 V. Which value on the transistor width should you have in orderto get 1.5 V at the output of the circuit?

Go back to CADE and change the design variablewincsto this new value. Rerun andcheck the AC output instead.

Determine the DC gain and the -3dB frequency.

Now, go back to CADE and change the DC input voltage (VariableVindc) to 1.5V. Rerunthe simulation and find the DC gain and -3dB frequency. Comments?

This is what happens when you get out of the correct DC operating region, the gain is dras-tically changing (why?). Check the DC output voltage by using the menuResults->Annotate->DC Node Voltages.

Change back to a 1-V DC level at the input. What is the output resistance, and DC outputvoltage? (Hint: use the commandResults->Print->DC Node VoltageandResults->Print->DC Operation Point.)

What is the total power consumption? It is found using the menu

Results->Print->DC Operation Pointfollowed by clicking on the power supply volt-age source,V0.

DC gain -3dB frequency

DC gain -3dB frequency


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TSTE80 ATIC Analog Simulation Techniques Page 15


Is the transistor operating in its saturation region? Check that andusing the command Results->Print->DC Operation Point followed by

clicking on the transistor.

Check if the simulated gain is reasonably aligning with the derived -ratio.

10 Analog Simulation Techniques

To avoid simulation problems we mostly try to not use too ideal components in our simu-lations. Therefore it is convenient to define the signal sources to have an output impedanceof say 50 ohms and 100 fF, see Figure 5 (a). In the same way we have to add a load imped-

ance to the test circuits. Mostly, we deal with CMOS circuits and the gates of the transis-tors are used as input stages. This implies that the load resistance is infinite, but the loadcapacitance can be something in the order of 25 pF.

In analog design we never use the minimum channel length, , of the transistors. Theminimum channel length is not guaranteeing a proper , it is too poorly modeled in thesimulator. Instead, we use a minimum channel length of approximately to

. Hence, for our process we will in the exercises use . However, shorterchannel lengths can be used in order to increase some performance metrics while still haveacceptable circuit yield.

The RC-filter is already design in this laboratory and it is found inANTIKlab->RC-Voltage-input. To use this subcircuit it is just to connect the inputvoltage source to the input terminal and the output terminal is connected to the input ofthe circuit under test.

11 CMOS Gain Stages

In amplifier design on a printed circuit board (PCB) resistive load is often used. The dis-advantage with using a resistive load is that the gain cannot be very high, since the resis-tance must be large. This will cause the current to be small in order to keep the voltagelevels at descent values. Therefore, active loads are preferred. This will significantlyincrease the gain and hence the DC levels are very important. Adjustments in the order ofmV will completely change the transfer function of the gain stage.

In this exercise we use single-stage amplifiers as given in Figure 6. The resistive loadshave been replaced by active loads. Further, the channel length is 1 um. You should use

the voltage source with an internal capacitance and resistance as well as the 25 pF capac-itive load on each amplifier. All transistors must be in their saturation regions. The powersupply voltage is 3.3 V.

VDS VDS sa t,>VGS VT 0>

gm gou t

Figure 5: Non-ideal voltage source (a) and capacitive load added to the test circuit (b).

Rsrc

Csrc

a) b)

Cload

Vsrc

RC-Voltage-input

Lmi nL

1.5 Lmi n4 Lmi n L 1m=


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TSTE80 ATIC CMOS Gain Stages Page 16


Preparation!

Derive the small-signal models for the three circuits in Figure 6. Derive theinput and output impedances, the DC gain, and the bandwidth. Solve exercise 7

in Exercise Manual.Modify the schematics starting withActive_load_in the libraryANTIKlabto simulatethese building blocks instead. Note that you have to add a number of bias voltage sourcesfor the added transistors.

The specifications on the circuits are given in Table 2 below.

Once again when you simulate be very careful with the DC analyses. You may have toincrease the accuracy, i.e., more points in the parameter sweep, to find proper values.

When finding the proper signal swings at input and output we sweep the DC level from 0to 3.3 V.

The input- and output ranges are defined as the voltage ranges for which all the transis-tors are saturated.

We will also investigate the settling time of the circuits as well as the general time-domainbehavior. By using thevpulsesource we can apply a voltage step at the input. Select theinput source and pressqand enter the following values in thevpulsefield.

Common source(a) Common drain(b) Common gate(c) Unit

Bias DC voltage 2.3 0.6 2.3, 2.3 V

Input DC voltage 1 2 1 V

Output DC voltage 1.65 1.15 2 V

DC gain 40 1.8 40 dB

Table 2: Specification on amplifiers.

Voltage 1 Vindc

Voltage 2 Vindc+0.001

Delay time 1u

Rise time 10n

Figure 6: Transistor view of single-stage amplifier stages including active load; common source (a),

common drain (b), and common gate (c).

M1

Vout

Vin

M1

Vout

Vin

M1

Vout

Vin

Vbias1

Iin

M2

M2

M2

(a) (b) (c)

Vbias2Vbias

Vbias


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TSTE80 ATIC Current Mirrors and Cascoded transistors Page 17


Let the simulation go to 4us by changing adding a transient analysis in the CADE window.

Note that for the low-gain stages you may have to change the +0.001 to a somewhat largervalue, like 0.01 to 0.1, in order to see good output results. Run and plot the input and out-put signals. Measure the time constant. When a small step is applied to the input of a cir-cuit with a dominating pole the output signal will have the form

. (1)

where is a function of the DC gain of the circuit times the size of the step at the input.In other words the final output voltage is . The time constant is defined as

. (2)A graphical representation is shown in Figure 7.

Compare the time constant with the output pole of your system as

. (3)

Comments?

Fill in the simulated results in Table 3 below and save all states.

12 Current Mirrors and Cascoded transistors

When designing for example a simple gain stage we want to control the current going

through the circuit ( ) very carefully. This is because many performance measuresdepends on , e.g., gain, bandwidth, and slew rate. In order to avoid changing the bias

Fall time 10n

Pulse width 8u

Period 10u

V t( ) V 0( ) V 1 e t /( )+=

VV 0( ) V+

V ( ) V 0( ) V

1 e

1

( )+ V 0( ) V

0.63+=

t

Vou

t(t)

0

V0

V0+ 0.63V

V0+ V

Figure 7: Step response of a single-pole system.

1

p1

------= CL Rou t

iDiD


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voltages controlling when changing as for example the width of the bias transistor weare going to use current mirrors instead. Later in the laboratory we will see how we canincrease the gain in a gain stage by the use of cascodes.

The current sources are widely used as bias sources and we shall now add them as biassources to our amplifier stages. In order to simplify our circuits, we only use the simplecurrent mirror (Figure 8a). The other (Figure 8b) will work even better due to the higheroutput impedance, but we have more transistors and bias voltages to control. The simplecurrent mirror also simplifies the understanding of the circuit building block.

As you may have found out through calculations the DC gain of an amplifier stage is givenby

. (4)

Common-

Source (a)

Common-

Drain (b)

Common-

Gate (c)

Bias DC voltage

Input DC voltage

Output DC voltage

DC gain

Bandwidth

Unity gain frequency ( )

Phase at

Time constant

Output voltage range

Input voltage range

Table 3: Simulated results.

u

u

iD

Figure 8: Simple (a) and cascode (b) current mirror.

Iin Iout

Iin Iout

M1 M2

M3 M4

M1 M2

A0

gm

gou t

---------=


18/26



At a higher level, we see that we have two approaches to increase the DC gain of the cir-cuit; by increasing or decreasing . We also know that for a common-source ampli-fier we have and , which tells us how to increase/decrease

/ . However, we also see that

. (5)

Hence, by decreasing the bias current by a factor of 4 the DC gain is doubled. However, ifwe want to reach very high gain we have to make the current very small or the transistorvery large. This is not attractive due to more inherent noise in the circuit and lower unity-gain frequency. Instead we use cascodes, and you should now compare the common-sourcewith and without cascodes as illustrated in Figure 9 (a) and (b).

We solve the biasing problem of the bias transistor with a somewhat messy method. At thisstage though, the understanding of the operation is more important. We have two currentmirrors as shown in the figure. You can choose whatever current mirror rate, but the mir-rors should be matched and give 100 uA in their output branches. The input DC voltagesshould be equal to 0.63 V in both cases. The output DC voltages should be 1.65 V (or atleast very close to).

Preparation!

Derive the output DC gain of the stages. Solve exercise 9 in the Exercise Man-ual.

The schematic of the amplifiers is calledANTIKlab->Cascode. All variablesstarting withcs belongs to the simple common-source amplifier. Let the sizes of both inputtransistors be equally large using the variablew1.

Use subcircuits for the current and voltage sources and do not forget the capacitive load asdiscussed in (Figure 5)

gm gou tgds Id gm W L( ) Id

gm gou t

A0W L( ) I

d

Id-------------------------------- W L( )

Id---------------------- WL

Id-------- =

Figure 9: Current mirror as biasing circuit.

M1

Vout

Vin

M2M3

Ibias

M1

Vout

Vin

M4

M5

Ibias1

Ibias2

M2M3

M6

M7

M8


19/26



To simplify your design, start with letting the mirror rates of the current mirrors be unity.Note that it is important that you have the same current through the amplifier stages.This may imply that the sizes of the sources are not completely equal.

Let all bulks be connected to the vdd / ground for the PMOS / NMOS transistors.

Use the values shown in Table 4 to start the simulation with.

Choose all channel lengths to .

Start with the DC simulation and sweep for example the input transistor size,win, from100u to 150u. Plot the output voltages and compare them. How can you from this simula-tion directly see that the cascoded stage has a higher gain?

When you simulate the circuit, you will find that the cascode stage is extremely sensitiveto variations in transistor sizes, you may notice that changes in the order of only 0.01umgive rise to drastical changes. This is due to the very high gain. However, truncate thetransistor sizes to multiples of 0.2 um.

Size the bias currents very carefully, they may have to be determined in the order of nA.This is however only for the simulator. In reality anamplifier like this is used in a feedbackconfiguration, the gain is significantly reduced and it becomes less sensitive to bias varia-tions.

When you have tuned in the DC operating points to be very close to each other, run the ACanalysis and find the gain, bandwidth, unity-gain bandwidth, phase margin for a capaci-tive load of 5 pF. Fill in Table 5.

Conclusions?

Now, try to half the DC gain in the cascoded amplifier by only changing the sizes of thetransistors M4/M7 and M5/M6. What should you do according to the theory (the prepara-tory questions). Is it possible? If not, what do you have to change as well, and why? Whatabout the DC output voltage?

Determine the time constants of the two circuits and relate these to the simulated pole fre-quencies. Use thevpulseblock to add a 1mV input step to your input DC.

This step will probably directly overdrive your cascode stage since this stage has a gain ofapproximately 10000 and you may have to add a 50uV step instead. Investigate if you

even have slew-rate limiting.

What should the slew rate limit be and what are the requirements for linear settling?

Single transistor Cascode transistor Unit

Input DC voltage 0.63 0.63 V

Bias DC current 100u 100u A

and 150u 150u M

and 300u 300u M

and 120u M

and 200u M

Table 4: Start values for common-source amplifiers.

Ibias

W1

W8

W2

W3

W4

W7

W5

W6

L 1m=


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TSTE80 ATIC Intermediate wrap-up Page 21


Finally, find the voltage operation ranges for the both amplifier stages. Hence, for whichinput and output voltages do the transistors operate in their saturation regions?

Although it is a tedious work to find the ranges, it is very important to determinethem.

13 Intermediate wrap-upWe have now simulated the most simplest amplifier stages. Hopefully, you have alsolearnt some simulation techniques. For example

first DC, then AC, finally transient analysis.

You have hopefully learned some useful simulation tricks, such as

use variables and/or parameters

simulate several types of analyses at the same time

You have noticed that when simulating analog circuits, we should not use too ideal com-

ponents and you have

used subcircuits for the current and voltage sources

added capacitive loads

You have hopefully also noted that

there is a large number of different specification parameters to simulate, such assettling time, slew rate, unity-gain frequency, phase margin, output conductance,DC gain, DC voltages, transistor sizes, load capacitances, bias resistors, etc.

the number of parameters to modify in order to meet specification is huge

we have to cut down the number of parameters by fixing bias currents, DC voltages,etc.

Single transistor Cascode transistor Unit

Input DC voltage 0.63 0.63 V

Output DC voltage 1.65 1.65 V

DC current

DC gain

Bandwidth

Unity-gain frequency

Phase at

Table 5: Simulation results.

u

u

W L( )1

L 1=( )

W L( )2 L 1

=( )

W L( )3

L 1=( )


21/26

TSTE80 ATIC Differential stages, OPs, and OTAs Page 22


You have found that to increase the gain we can

decrease the current, modify the DC voltages, increase transistor sizes, etc.

use gain enhancement techniques, such as cascoded transistors

Now, we are going to make this laboratory somewhat tougher.

14 Differential stages, OPs, and OTAs

Now we move on to the design of the differential stage, operational amplifiers (OPs) andoperational transconductance amplifiers (OTAs). Use the material as a help for yourproject. Good Luck.

15 Simulation of Opamps

First, we start with a brief overview of different simulation techniques for the OP/OTA. In

Figure 10 we find several circuits using an OP.

(a) Open-loop. Used to find the DC gain, bandwidth, phase margin, unity-gain band-

width, slew rate (SR), etc. (b) Closed-loop and inverting amplifier, . Notice that the DC

voltage source has to be used for single-ended OP. Used to find the output range(OR) but also to simulate the OP in a context.

(c) Common-mode simulation. To investigate the common-mode range.

(d) Offset simulation. Used only when simulating influence of matching errors.

In open-loop configuration we have to be very careful when simulating the circuit, sincethe gain is very high. This implies that small changes to transistor sizes, DC voltages, etc.,will give strange outputs. First, we consider the open-loop simulations, (a) and (c), then wecare about the closed-loop, (b). The common-mode range, i.e., the possible common input

DC points, can be found by simulating the configuration in (c). However, an OP is alwaysused in a closed-loop configuration. In Figure 10(b) we show the inverting amplifier con-

Figure 10: OP/OTA simulation setups.

(a)

VDC

Vin

Vout

Z1

Z2

Vin

Vout

Vin Vout

(c)

(b)

Vin

Vout

Vos

(d)

Vou t Vin Z2 Z1=


22/26

TSTE80 ATIC Differential stage Page 23


figuration, where the feedback factor is given by . If , e.g., byremoving and replacing by a short circuit, we have the buffer configuration. This isthe worst-case configuration for the OP, when considering stability issues.

The power supply rejection ratios (PSRR) are simulated by adding a voltage source at thepower supply (PSRRp) as well as the ground terminal (PSRRn) of the OP (connect the load

capacitor directly to the ground). The PSRR of the OP is the minimum of PSRRp andPSRRn. The common mode rejection ratio (CMRR) is simulated partly by applying an ACvoltage as Vinin Figure 10(c). Hence, to derive PSRR and CMRR you must perform foursimulations where you just have an AC voltage at one of the voltage inputs (differentialinput, common-mode input, power supply input, and ground input) at a time.

Since process variations will cause mismatch between transistors, it is important to alsodetermine the offset voltage of the OP. This is found by using the setup in Figure 10(d), wewill not address this more in this course. More information on the simulation techniquescan be found in J&M.

Do not forget that virtual ground is the DC offset of the input signals, and not necessarily

equal to real ground.

16 Differential stage

In high-performance circuits it is advantageous to use differential circuits, since it willincrease the linearity and make the circuit less sensitive to noise. A simple example of afully differential circuit is the CMOS differential pair as illustrated in Figure 11. The pairhas a resistive load. Let the bias current be 250 uA and the load resistances, , be8 kohms. The power supply voltage should be 3.3 V and the DC output voltage will end upat 2.3 V. (Why?) Connect all bulks to ground.

Preparation!

Derive the differential and common-mode gains of the stage. Solve exercise 11in the Exercise Manual.

The schematic of the circuit is found in the libraryANTIKlab->diff_stage_resistive_loadand the testbench is called

ANTIKlab->diff_stage_resistive_load_TB. We shall now focus on simulating the

Z2

Z1

Z2

+( )= 1=Z1

Z2

RL

Figure 11: CMOS differential stage.

M1 M2

M4 M3

Vin+ Vin-

Vout+

Vbias

RLRL

Vout-

Ibias


23/26



differential as well as the common-mode gain of a circuit, and therefore we need also toplot the differential output voltage

, (6)

as well as the common-mode output voltage

. (7)

The differential output voltage can be obtained by using the converter circuit inFigure 12a, and the common-mode output voltage using the circuit in Figure 12b.

The circuit elements in these circuits are voltage controlled voltage sources. The convert-ers are calleddifferential_out andcommon_mode_outand they are found in the

ANTIKlablibrary.

Differential input sourceIn order to simplify the simulation of the differential input signal we are going to useanother subcircuit. Since the input signal can consist of a DC operating point, differentialsignal, and common-mode signal it is convenient to have a sub circuit as illustrated in Fig-ure 13.

This circuit together with the concept of an internal resistance and capacitance of the volt-age sources is found in the libraryANTIKlab->differential_input.

Vdiff Voutpos Voutneg=

VcmVoutpos Voutneg+

2------------------------------------------=

Vdiffout

internal

posin

negin

Figure 12: Converters for a) differential output and b) common-mode output.

Vcmout

internal

posin

negin

Gain =1

Gain =-1

Gain =.5

Gain =.5

Figure 13: Differential input signal.

Voutp Voutn

common

Vdiff Vdiff

Vcm

Gain=0.5 Gain=0.5


24/26



Start to simulate. Size the transistors so that V and the width of the input tran-sistors are 200 um.

Find the DC operating point for maximum gain! All transistors must be saturated. Assumethat you sweep the input common DC level (the variableVcm), what do you actually see atthe outputs?

Use this operation point when simulating the small-signal behavior of the circuit. Further,determine the bandwidth, DC gain, phase-margin, etc., for the differential output signal.

Common-mode signals

Further, we have the common-mode range (CMR). This describes the possible voltagerange for the input DC voltage (of course you should have the same DC voltages at thegates of the input transistors). Determine the CMR by sweeping the input DC voltage, usethe subcircuit from Figure 12b to plot the common-mode output signal.

Derive the common-mode rejection ratio (CMRR). CMRR is a measure of how much thecommon-mode input voltage is amplified compared with the differential input signals, i.e.,

(8)

and should be as large as possible. Unfortunately and must be simulated in twodifferent circuits, but can, with the correct schematic, be simulated in the same run (usesubcircuits). Apply a differential input to the first differential stage to get and a com-mon-mode signal to the second differential stage (see Figure 10c) to get . Note that wein both cases are interested in the differential output (Eq. 6).

Determine the bandwidth, unity-gain frequency and CMRR at low frequency.

Influence from power supplyTo determine the disturbance from the power supply lines (or bias wires) on the circuit per-formance we have the power supply rejection ratio (PSRR) measure. This is simulated byadding a sinusoidal source to the positive and negative supplies. We then measure thetransfer functions from these sources to the output. These functions are compared with thedifferential gain of the circuit. For the positive supply we only have to add an AC source inseries with the symbol that is connected to the differential gain stage

Vsin with the following voltageAC 1andDC 0

Notice that you have to cancel all other AC sources in your schematic.

Simulate and determine the transfer function from the power supply to output.

For the ground node, add a voltage source with 1 volt ac and no DC voltage. The voltagesource should be connected between the ground and theAGNDnode of the differential gainstage. Modify the schematic so that you are able to measure the influence of AC sourcesfrom the ground to the output.

Finally, PSRR is determined by the worst case, i.e., is the positive or negative supply dom-inating the induced disturbance. Determine the PSRR for the circuit.

Differential stage with current mirror load and single-ended output

The circuit we have simulated is a differential-pair with passive load. We know since pre-

viously that passive load will give us a poor gain. Now, we add an active load in terms of a

Vbias 0.7

CMRRAdiff

Acm-----------=

Adiff Acm

Adiff Acm

Vdd


25/26



PMOS current mirror as illustrated in Figure 14. Notice now that the circuit is single-

ended.

Preparation!

Derive the differential and common-mode gains of the stage. Solve exercise 10in the Exercise Manual.

The same set up as earlier is used, but the testbench is calleddiff_stage_single_endedin theANTIKlablibrary, hence the same bias current andsame transistor sizes. Your objective is now to determine the sizes of M3 and M4 that max-imizes gain and voltage swing at the output. You have the DC input voltage to vary as well.

Simulate and determine the

possible input and output swing

slew rate

common-mode gain

differential gain

common-mode rejection ratio

Differential stage with transistor load and fully-differential

The next issue is to increase the gain even more and make the circuit fully differential.Consider the circuit in Figure 15. Find the bias voltages by using current mirrors for bias-ing. The current through M5 should be 250 uA and use the same transistor sizes as before.Simulate the stage and complete the table below. The circuit can be found in the testbench

ANTIKlab->diff_stage_fully_differential.

Fully differential stage

Input DC voltage

Output DC voltage



M1 M2

M3 M4

M5

Vin+ Vin-

Vout

Vbias


26/26


If you would like to double the -3dB frequency, what would you do? (Of course, we do notchange the load capacitance). What should you do to double the DC gain?

CONGRATULATIONS!

You have just made your first operational transconductance amplifiers. Hopefully youhave seen how the list of things to simulate has grown very fast. This will hopefully inspireyou to start to make template files and use lots of parameters, etc., to speed up your sim-ulations.

However, the gain of the amplifiers in the previous is not high enough for our applications.We have to use other tricks, such as multi-stage amplifiers in order to have good opera-

tional amplifiers (OP) and operational transconductance amplifiers (OTA).

DC gain

Bandwidth

Unity gain frequency

Phase margin ( )

CMR

Output range

CMRR

PSRR

Output resistance

Slew rate

Settling time (90%)

Fully differential stage



M1 M2

M3 M4

M5

Vin+ Vin-

Vout+

VbiasN

Vout-

VbiasP

1=

laboratory manual cadence

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