Lab 4 Comments:

• The Main Points: The Main Points: – Simulation: Simulation:

• allowed you to test a circuit before you actually built the allowed you to test a circuit before you actually built the circuitcircuit

• Simulator was based on device modelsSimulator was based on device models• Device Device modelsmodels were used to simulate propagation delays in were used to simulate propagation delays in

actual devicesactual devices• Static logic hazards were located, tested (they caused Static logic hazards were located, tested (they caused

glitches), and removed. glitches), and removed.

Lab 5 Comments:

• The Main Points: The Main Points: – The logic analyzer is a test device that is used to view the The logic analyzer is a test device that is used to view the

signal activity of an signal activity of an actual circuitactual circuit • as opposed to the simulated circuit of Lab 4 as opposed to the simulated circuit of Lab 4

– The Xilinx Design Methodology was the steps you took to: The Xilinx Design Methodology was the steps you took to: 1.1. model a circuit model a circuit 2.2. simulate the model (verify how it will behave)simulate the model (verify how it will behave)3.3. implement a circuit (on the FPGA) with the same output characteristics implement a circuit (on the FPGA) with the same output characteristics

as the modelas the model

– Implementing circuits on the FPGA was much easier than Implementing circuits on the FPGA was much easier than wiring the circuit using discrete logic gates (previous wiring the circuit using discrete logic gates (previous experiments). experiments).

Combinational Building Blocks: Encoders and Decoders

Experiment 6

Instructional Objectives:

• To learn concurrent statements in VHDL.To learn concurrent statements in VHDL.

• To design combinational building blocks in To design combinational building blocks in VHDL and to implement them on the VHDL and to implement them on the Spartan 3 (Nexys) or Spartan 3E (Nexys 2) Spartan 3 (Nexys) or Spartan 3E (Nexys 2) FPGA.FPGA.

VHDL Basics

• ENTITY– black box description of circuit – declares inputs and outputs, their type, and their

size

• ARCHITECTURE – what’s inside the box– Specifies the implementation of your circuit

VHDL Entity

ENTITY modulename ISPORT ( input1 : IN STD_LOGIC;

input2 : IN STD_LOGIC;output1 : OUT STD_LOGIC_VECTOR(0 TO

7);output2 : OUT STD_LOGIC);

END modulename;

VHDL Architecture

ARCHITECTURE myarch OF modulename ISinternal signal declarations;

BEGIN

concurrent statement1;concurrent statement2;concurrent statement3;

END myarch;

Concurrent Statements:Signal Assignment (<=)

ARCHITECTURE my_arch OF module_name ISSIGNAL internal_sig : STD_LOGIC;

BEGIN

-- a comment begins with two hyphensinternal_sig <= input1 AND input2;output1 <= “10101010”;output2 <= internal_sig XOR output1(3);

END my_arch;

Concurrent Statements:Conditional Signal AssigmentARCHITECTURE myarch OF modulename ISBEGIN

output2 <= b WHEN (sel = “01”) ELSEc WHEN (sel = “10”) ELSEd WHEN (sel = “11”) ELSEa; -- default

END myarch;

Concurrent Statements:Selected Signal Assignment

ARCHITECTURE myarch OF modulename ISBEGIN

WITH sel SELECToutput2 <= b WHEN “01”,

c WHEN “10”,d WHEN “11”,a WHEN OTHERS;

END myarch;

Experiment 6 Overview

P1: Design and implement a Binary-Coded-Decimal

(BCD) to 7-segment Display Decoder

P2: Design and implement an 8:3 Priority Encoder

P3: Integrate the circuit from the two previous steps and use the BCD-7seg Decoder to display your output

Nexys Development Board

a

b

c

d

e

fg

Four 7-segmentLED Displays

See Reference Manual(ignore multiplexing)

7-Segment Display Control

1 = Vcc

1

0 = Gnd

0

COMMON-CATHODE Display

COMMON-ANODE Display(Works like you expect: 1 = ON)

Nexys Board: (0 = ON!)

So the 7 segment cathode signals (CA..CG) on Nexys Bd are active low

CE CF CD CA CG CB CC DP

AN0 AN1 AN2

CE CF CD CA CG CB CC DP CE CF CD CA CG CB CC DP

CA(from

FPGA)

• The individual display segment cathode signals from FPGA (CA..CG and DP) connect to ALL 4 displays at the same time (!!)• You must use the common anode signals (AN0..AN3) to turn ON the 1 display you want to use, and turn OFF the rest.

Nexys Development Board

CB

Nexys Development Board

Need 1 or 0 (?)from FPGAto Turn ONa Display??

Common anodes (AN0..AN3)connected to Vcc via a transistorControlled by FPGA outpus

1

0

3.3V

Lab Report Comments:

VHDL CODE:VHDL CODE:• Use the title banner in all your source Use the title banner in all your source

code files code files

-- Company: Cal Poly SLO-- Engineer: Stu Dent & Labpa R. Tner ---- Create Date: 10-06-07-- Design Name: BCD-to-7 Segment Decoder-- Component Name: -- Target Device: Digilent Nexys Development Board-- Tool versions: ISE 9.1-- Description: CPE 169 Experiment #6 – Procedure #1-- This device converts a single-digit (0-9) 4-bit BCD code to the control -- signals to display the digit on 1 of 4 available 7-seg. displays-- Dependencies: -- Revision:-- 10-13-07: added a few comments (like the instructor said we should!)-- -- Additional Comments:

Example VHDL Code Header

Lab Report Comments:

VHDL CODE:VHDL CODE:• Use the title banner in all your VHDL files Use the title banner in all your VHDL files • Put some comments into your VHDL codePut some comments into your VHDL code• Use indents, spacing, skipped lines to make Use indents, spacing, skipped lines to make

structure obvious and code readable.structure obvious and code readable.• Don’t allow your VHDL code to wrap around Don’t allow your VHDL code to wrap around

between lines between lines – examine your outputs before you submit them!examine your outputs before you submit them!

• Print your VHDL code from Xilinx environment Print your VHDL code from Xilinx environment and include with your report and include with your report

– don’t put code into the body of the reportdon’t put code into the body of the report

Lab Report Comments:

Circuit Diagrams:Circuit Diagrams:– Titled with a descriptive name for the circuitTitled with a descriptive name for the circuit– BriefBrief verbal description of the circuit's verbal description of the circuit's

function / purpose (what does it do?)function / purpose (what does it do?)– Circuit schematic and/or block diagramCircuit schematic and/or block diagram

• Include all input/output signalsInclude all input/output signals– When circuits are implemented in VHDL, When circuits are implemented in VHDL, signal names on signal names on

schematics should match signal names used in your schematics should match signal names used in your VHDL codeVHDL code

• Show allShow all input/output input/output signal sources / destinationssignal sources / destinations on the Development Board (switches, LEDs, etc.)on the Development Board (switches, LEDs, etc.)

Lab Report Comments:

Timing Diagrams / ModelSim:Timing Diagrams / ModelSim:

• TitleTitle and and annotateannotate allall timing diagrams timing diagrams – and and allall diagrams for that matter! diagrams for that matter!

• Show and explain your “Test Vectors”Show and explain your “Test Vectors”– Make clear how you verified proper operationMake clear how you verified proper operation

– If not clear, annotate your If not clear, annotate your test input valuestest input values and and resultsresults

(1’s and 0’s, BCD code,…whatever appropriate format for the (1’s and 0’s, BCD code,…whatever appropriate format for the signals/vectors.)signals/vectors.)

– Annotate Annotate expected outputsexpected outputs where actual outputs displayed where actual outputs displayed

• Print timing simulations from ModelSim and include Print timing simulations from ModelSim and include with your reportwith your report

– Annotated!Annotated!

Test Vectors & Simulation

Objective: Objective: Verify that each device Verify that each device

functions as specifiedfunctions as specified– ThoroughlyThoroughly Verify Verify

• ALLALL important functions / behaviors important functions / behaviors demonstrateddemonstrated

• ALL output signals operate properlyALL output signals operate properly• Common errors / problems shown NOT to occurCommon errors / problems shown NOT to occur

– EfficientlyEfficiently Verify Verify• Test all possible cases (truth table) only if Test all possible cases (truth table) only if

number of inputs reasonablenumber of inputs reasonable• Else, devise more clever subset of test Else, devise more clever subset of test

conditions that are “thorough enough”conditions that are “thorough enough”

Xilinx Notes

• Try placing your Xilinx Projects on the lab computer “C:” drive while you work in lab

– Choose this location when you create your new ISE Project

– Default Xilinx directory will be used if you don’t redirect your project file storage when you create the project

Goes to C:\Xilinx\... by default

Set up your own subdirectory on C: drive

C:/Stu_Mary

Xilinx Notes• Try placing your Xilinx Projects on the lab

computer “C:” drive while you work in lab

– DO NOT put ISE Projects in folders / directories that have any blank spaces in their names!!

• Xilinx ISE will have trouble finding the files• …and you will get totally FRUSTRATED !!!

– Avoid using the “Desktop” • Pathname has spaces C:\Documents and Settings\...\Desktop

• If they’re on C: drive, your files may not be available to you later!– You will need to reuse them for future labs!!!– COPY whole project to your own FlashDrive before leaving

DIGITAL ALARM SYSTEM(Experiment #9)

TODAY!TODAY!

NextWeek

Exp 9

1) VHDL source code is used to generate a description of your circuit design.

2) The VHDL source code generated in step 1) is translated into a form which can be used by other software used in the design flow.

3) The Test Bench Waveform software is used to generate signals which are used to verify proper circuit operation in the ModelSim XE simulator.

4) The circuit inputs and outputs are internally “mapped” to FPGA pins which are externally hardwired to input and output devices on the Nexys board.

5) The circuit design is downloaded into the FPGA.

6) Proper operation of the circuit is verified.

Xilinx Design Methodology

Download to FPGA (ExPort)

1) BE SURE TO PERFORM ALL STEPS IN THE PROPER ORDER TO AVOID PROBLEMS USING THE XILINX TOOLS

2) REFER TO THE DETAILED PROCEDURES IN LAST WEEK’S LAB (Experiment #5) AND THIS WEEK’S LAB (Experiment #6)

3) IF (When!!) YOU ENCOUNTER A PROBLEM, REFER TO #2 ABOVE! - Make sure that you have followed the proper procedures in the proper order before asking (and waiting!) for help.

IN CASE YOU DO NOT FINISH

• The Xilinx and Digilent Tools are all available on-line for FREE

Procedure for Downloadingthem is posted on theCPE-169 Website