1 | H a v e r

Lab #13: FPGA Circuit Realization

ECE/COE 0501

Date of Experiment: 4/12/2017

Report Written: 4/17/2017

Submission Date: 4/19/2017

Nicholas Haver

nicholas.haver@pitt.edu

2 | H a v e r

PURPOSE

In this lab, the arithmetic logic unit constructed in labs 11 and 12 was programmed onto a field programmable gate array,

or FPGA. Based on the schematic designed in lab 12, a description of the circuit, in the form of an input/output instruction

set, was downloaded onto the FPGA and could be manipulated and understood using the FPGA’s built-in switches, buttons,

LEDs, and 7-segment displays.

Throughout the lab, various discrete circuit components were replaced with a written hardware description language,

VHDL. After each component was replaced with its VHDL equivalent, the circuit was re-compiled, downloaded to the

FPGA, and tested.

METHOD

1) First, the 4-bit latch created with D flip-flops in Lab 12 was replaced with a set of 4 individual latch components, shown

in Figure 1. The latches were compiled into a single 4-bit latch component in the main schematic, as shown in Figure

2. 2) The BCD to 7-segment display decoders were removed from the circuit, and replaced with display decoder components

with VHDL, shown in Figure 3. The display outputs, along with the remaining inputs and outputs, were assigned the

appropriate pins on the FPGA for switches or buttons for inputs, and displays or LEDs for outputs, seen in Table 1. 3) To improve ease of readability, the 7-segment display decoder VHDL was modified to display hexadecimal values A –

F for decimal values 10 – 15, as shown in Figure 4. Table 2 shows the decimal values and their corresponding

hexadecimal values. 4) The 4x2:1 MUX, 4-bit latch, and address counters were replaced with their VHDL equivalents. To simplify the 4-bit

aspect of the MUX, its VHDL was written as structural type, first as a 1-bit data selector, and then iterated to create the

4-bit data selector. The VHDL code is shown in Figures 5 and 6. The MUX VHDL was added to the schematic, and the

FPGA was updated and tested using the verification operations from Lab 12.

5) The 4-bit latch VHDL was written as behavioral type, first as a 1-bit latch, and then iterated to create the 4-bit latch,

shown in Figures 7 and 8. The latch VHDL was added to the schematic, and the FPGA was updated and tested using

the verification operations from Lab 12.

6) The counter VHDL, shown in Figure 9, was written as dataflow type. The counter VHDL was added to the schematic,

and the FPGA was updated and tested using the verification operations from Lab 12.

7) VHDL circuit components for the MUX, 4-bit latch and counters were created from the VHDL. The complete schematic

with VHDL equivalent circuits is shown in Figure 10.

8) The final schematic with VHDL equivalents was tested on the FPGA using each of the operation from Lab 12 to verify

that everything was working properly.

3 | H a v e r

RESULTS

Figure 1: 4-Bit Latch Utilizing Individual Latch Components

Figure 2: 4-Bit Latch Component in Main Schematic

Figure 3: VHDL Code for 7-Segment Decoder with Decimal Characters

4 | H a v e r

The initial 7-segment display scheme illuminated the decimal for values greater than 9. For a value of ‘12’, the ‘2’ and

decimal point are illuminated. This display scheme was later modified to produce hexadecimal characters A – F

corresponding to values 10 – 15.

To Value Type To Value Type

ALU_Disp[1] PIN_V20 7-Segment C_n PIN_B13 Toggle Switch

ALU_Disp[2] PIN_V21 7-Segment IN_SEL PIN_A13 Toggle Switch

ALU_Disp[3] PIN_W21 7-Segment L_ENABLE PIN_N1 Toggle Switch

ALU_Disp[4] PIN_Y22 7-Segment M PIN_P1 Toggle Switch

ALU_Disp[5] PIN_AA24 7-Segment UP_R PIN_N23 Push Button

ALU_Disp[6] PIN_AA23 7-Segment UP_W PIN_G26 Push Button

ALU_Disp[7] PIN_AB24 7-Segment W_en_bar PIN_P23 Push Button

Out_Disp[1] PIN_AF10 7-Segment D_input[0] PIN_N25 Toggle Switch

Out_Disp[2] PIN_AB12 7-Segment D_input[1] PIN_N26 Toggle Switch

Out_Disp[3] PIN_AC12 7-Segment D_input[2] PIN_P25 Toggle Switch

Out_Disp[4] PIN_AD11 7-Segment D_input[3] PIN_AE14 Toggle Switch

Out_Disp[5] PIN_AE11 7-Segment F_SEL[0] PIN_AF14 Toggle Switch

Out_Disp[6] PIN_V14 7-Segment F_SEL[1] PIN_AD13 Toggle Switch

Out_Disp[7] PIN_V13 7-Segment F_SEL[2] PIN_AC13 Toggle Switch

B[0] PIN_AD23 LED - Red F_SEL[3] PIN_C13 Toggle Switch

B[1] PIN_AD21 LED - Red Q_output[0] PIN_AE22 LED - Green

B[2] PIN_AC21 LED - Red Q_output[1] PIN_AF22 LED - Green

B[3] PIN_AA14 LED - Red Q_output[2] PIN_W19 LED - Green

COUNT_R[0] PIN_AE23 LED - Red Q_output[3] PIN_V18 LED - Green

COUNT_R[1] PIN_AF23 LED - Red Latch_Output[0] PIN_AA13 LED - Red

COUNT_W[0] PIN_AB21 LED - Red Latch_Output[1] PIN_AC14 LED - Red

COUNT_W[1] PIN_AC22 LED - Red Latch_Output[2] PIN_AD15 LED - Red

Latch_Output[3] PIN_AE15 LED - Red Table 1: FPGA Input and Output Pin Assignments

5 | H a v e r

Figure 4: VHDL Code for 7-Segment Decoder with Hexadecimal Characters

The table below shows the hexadecimal characters that were generated on the 7-segment display, instead of the previous

display scheme using decimal values and a decimal point.

Decimal Hexadecimal

10 A

11 b

12 C

13 d

14 E

15 F Table 2: Decimal Values and Corresponding Hexadecimal Display Characters

6 | H a v e r

Figure 5: VHDL Code for 1-Bit Data Selector

Figure 6: VHDL Code for 4x2:1 Data Selector

Figure 7: VHDL Code for 1-Bit Latch

7 | H a v e r

Figure 8: VHDL Code for 4-Bit Latch

Figure 9: VHDL Code for 2-Bit Up Address Counter

8 | H a v e r

Figure 10: ALU Schematic with VHDL Equivalent Circuit Components

CONCLUSION

The purpose of this lab was to take the arithmetic logic unit constructed in Labs 11 and 12, and program it onto a

single chip, called a Field Programmable Gate Array (FPGA). While doing so, several of the circuit components

were replaced with a hardware description language, VHDL. Once the VHDL was written, equivalent circuit

components were generated and replaced the existing components in the schematic. The 4x2:1 data selector, 4-

bit latch, and address counters were replaced with VHDL equivalents. After each replacement, the FPGA was

updated, and everything was tested using the same procedure as Lab 12.

This lab demonstrated the convenience of using FPGAs over discrete circuit components thanks to their easy

reconfigurability, smaller size, and ability to hold components such as buttons, switches, LEDs, and displays on

a single device.

REFERENCES

• Dr. Alex Jones’s laboratory instructions

• ECE/COE 0501 Lab Manual

• Altera DE2 FPGA Board Manual

• Lab Partner: Jenn Gingerich