Lab 1: 8-bit Latch using Quartus II and ModelSim

CpE 214: Digital Engineering Lab II

Last revised: February 26, 2013 (CAC)

Latches and flip-flops are examples of sequential logic circuits. Unlike combinational logic circuits, which depend onlyon the current state of the inputs, sequential circuits also depend on the past sequence of inputs to determine the outputs.The basic difference between the two being that, flip-flops in general, refer to a sequential device that samples its inputs andonly changes its outputs at times determined by a clock signal. Latches on the other hand are also sequential devices whichsample their inputs, but change output states without regard to any clocking signal. In this lab we are going to develop an8-bit latch which latches the 8-bit inputs to the output only when the enable signal is asserted. For this purpose we use a3:8 decoder to select between the individual 1-bit latches.

0.1 Outline and Concepts

1. Developing the module for the 3:8 decoder

2. Developing a module for the 8-bit latch

3. Integrating the 2 modules into a new schematic

4. Simulate the design using ModelSim

5. Testing the design on the Cyclone II FPGA

1 Developing the module for the 3:8 decoder

Let us first consider the truth table for a 3:8 decoder:

A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D00 0 0 0 0 0 0 0 0 0 10 0 1 0 0 0 0 0 0 1 00 1 0 0 0 0 0 0 1 0 00 1 1 0 0 0 0 1 0 0 01 0 0 0 0 0 1 0 0 0 01 0 1 0 0 1 0 0 0 0 01 1 0 0 1 0 0 0 0 0 01 1 1 1 0 0 0 0 0 0 0

Depending upon the input patterns and the corresponding output, a logic circuit can be constructed in Quartus II usingthe Schematic Capture functionality of the software as outlined in Appendix A. Just to make you familiar with the varioussteps to be followed, they are listed below:

1. Open Quartus II and create a new project and follow the basic steps as listed in Appendix A. Name this project aslab1. Make sure you choose the correct Device ID: Cyclone II Family->EP2C35F672C6. Make sure later on that thename of the top level schematic (entity) and that of the project are the same to avoid compile problems.

1

2. In order to develop a 3:8 decoder, we have to make the schematic of the 3:8 decoder and then its corresponding symbol.Click on File->New and select Block Diagram File (bdf). Now draw the schematic as shown in the figure below, byfollowing the various steps to include the logic by referring to the Appendix ’A’. Using the Drawing Tools, draw a boxat the bottom of your design and type your name and the date in the box. Save the schematic as 3_8dec.bdf.

3. Now create a symbol for this particular schematic by clicking on File->New -> Create update->Create Symbol filesfor current file. In this way a symbol is created for your schematic.

Figure 1 shows the schematic block diagram file for the circuit.

FIG. 1: 3:8 Decoder Schematic

2 Developing a module for the 8-bit latch

For developing this module, the latch that is already available or defined in the component list of the Quartus II is to beused. This module utilizes an 8-bit bus and an enable signal which when asserted, the inputs are latched and we get theoutput. In case the enable signal is de-asserted in between, the output should retain the previous state of the logic.

2

Follow the various steps as listed below to create this schematic:

1. Create a schematic for a 8-bit latch by wiring an input bus and an enable line to D flip flops. These elements are alreadyin the Quartus library, and can be added by right-clicking, choosing Insert->Symbol, and looking Storage->Latch.

2. Save the schematic as 8latch.bdf, and then create a symbol with the same name.

The schematic of this module is illustrated in Figure 2:

FIG. 2: Schematic for 8-bit latch

3 Integrating the 2 modules

Now follow the steps as listed below to integrate the models:

1. Again create a new Block diagram file. Double click anywhere on the schematic sheet and then from the Project dropdown box select the two symbols for the 3_8dec and for the 8latch and integrate them as shown in the Figure 3 below.

2. Save this top level block diagram file as lab1.bdf and compile the design. Now the test bench of an 8-bit latch is createdsuccessfully.

FIG. 3: Top-level schematic for lab1

3

4 Simulate the design using ModelSim

Before we move over to ModelSim (Quartus’s sister simulation package), we need to make sure we are creating a VHDLlanguage file(s) of our design so far. To do this, go to Assignments->Settings, and then in the Simulation window from theleft hand pane, choose ModelSim-Altera. It should look like below in Figure 4.

FIG. 4: Compile Settings to create VHDL objects for ModelSim.

1. Open ModelSim and create a new project named “lab1”, add lab1.vho (your VHDL output file) in the your projectfolder. This is usually located in the lab1/simulation/modelsim folder.

2. Go up to Compile->Compile All, and then wait for the green checkmark for the okay.

3. In the bottom left of your screen, there’s a tab called Library. Choose this and scroll all the way to the top of the list.You should see your project file name. Expand it down, right-click on your top-level entity (lab1) and choose Simulate.

4. Of the panels that popup, we care about the Objects window. In here, you only need to CTRL-click and highlight yourInput (D), Output (Z), and Enable lines. The rest are not necessary. Right-click and choose Add->To Wave->SelectedSignals.

5. The clever way to test all 8 input combinations easiliy is to apply a different clock to each input bit. We assume thateach input combination will last for 100ps. Holding the enable low/high respectively for 800ps each (a full cycle ofinput combinations), we get a total of 1600ps simulation time. If we look at the truth table of the 3:8 decoder we willrealize that the least significant bit of the input changes every 100ps and hence 16 times. The next higher order bitchanges 8 times or every 200ps and finally the MSB changes four times every 400ps. In the wave window, right clickon the input (0) and select clock, this will bring a window box. After setting the period to be 200 and first edge to beFalling, click on OK. Repeat this procedure for the inputs (1), (2) and Enable. Thus set i(0)’s clock for 200ps, i(1) for400ps, i(2) for 800ps, and enable for 1600ps.

6. Type “run 1600ps” in the command line window at the bottom, you should be able to see the following waveform inFigure 5.

4

FIG. 5: Example ModelSim results

5 Testing the design on the Cyclone II FPGA

The input and the outputs of the design still need to be assigned to the Altera board. This is achieved by going toAssignments->Pin Planner. Before you do your pins, it’s a good idea to double-check that you have the correct Cyclone IIboard. Otherwise the pins you’ll be assigning will be to the wrong hardware address locations. Use Appendix D to determinethe pin locations, this will become your friend in each lab from here on. You will use 3 toggle switches for your input, a 4thfor your enable, and 8 LED’s (choose all Red, or all Green) for your outputs. Be sure to recompile a final time after your pinassignments are made.

In the Tools menu, choose Programmer and make sure the USB-Blaster is selected (this is called JTAG mode). You canthen choose Start to flash the FPGA. Verify the design by providing different inputs with the switches and observing theoutput on the LED’s.

6 Questions (attach at end of your report)

1. What is the difference between a flip-flop and a latch?

2. Explain in brief, the entire design flow of this lab. Why did we build things in a modular fashion?

5